UNIVERSIDAD AUTNOMA DE YUCATN

FACULTAD DE INGENIERA
Digital Sistems II

Final Proyect: Conveyor

Canch Santos Lucio, Ojeda Flores Miguel, Santamara Gonzlez Micqui ABSTRACT As a final project for the Digital Systems II optative , a prototype of a conveyor that discriminates chips in base of the image that present is made. The sensing and the mechanic operation code are implemented in one FPGA, while the selection logic has been development in LabVIEW, getting as result that both platform are integrated through a Bluetooth module. Finally, this model is a prototype because we search to connect a Digital Camera to the FPGA by Serial Communication, getting as result a Vision System implemented in one Embedded System.

INTRODUCTION The conveyors are continuous transport systems, thus it can be found in the industry and others areas, like agricultural. The present project search to adapt, the system mentioned before, an optical medium to select pieces, getting an object classifier. DEVELOPMENT The present prototype involves areas that are very important to its development and control. To get a good explanation, it will be divided in the following steps: a)Mechanic and Electronic Assembling b) The conveyors Control c)The Selection Process a) Mechanic and Electronic Assembling To the mechanic assembling, were used too many recycling things, like the rail and some supports (these were useful to hold the camera and the servomotor). The main rail has several openings to adapt sensors, the griper of the servomotor (to get out the rejected coin), and the rails where are released the processed coins.

The electronic section has optocouplers that protect the FPGA ports. Besides, it has included transistors and comparators that condition the analogic signal.
O P T O A C O P L A D O R P U E R T O S C O N T R O

CNY70 SENSOR FOTORESISTOR SERVOMOTOR

E S

Figure 2. Electronic Interface b) Conveyors Control (FPGA) The control of the conveyor involves two State Machines: The first watch the mechanisms state and the sending the byte to get the picture, that depend if the coin is in the camera focus. When the FPGA receive the high level logic, from the sensor, it sends a Byte toward LabView by the UART, keeping itself in the waiting state to receive other byte that represents the classification of that coin after analyzed. That Byte is saved in the FIFO memory from the receptor UART, to store the results in order.

Waiting the Coin

Figure 1. Mechanic Assembling

Figure 3. Taking Picture Control

Take picture

Waiting the result Saiving in FIFO

UNIVERSIDAD AUTNOMA DE YUCATN

FACULTAD DE INGENIERA
Digital Sistems II

The second control the position degree of the servomotor. This amount depends of the received Byte, while each of this will be read if the FIFO isnt empty and the coin is released.

State. 2 State Machine

Figure 4. Decision Control

Wait for answer from LabVIEW

Figure 6. Invariant Moments

coin

To Read FIFO

Rejected coin (Sensor 1)

Accepted (Sensor 2)

*State #3 After a decision was took, based in the similarity of the Invariant Moments, a byte is sending to the FPGA, backing to the first state waiting the order to process other image

c) The Selection Process (LabVIEW) The central logic of LabVIEW consists in one State Machine, which has the following 3 states: *State #1 While the buffer doesnt receive any byte, the process stays in this state, in other case, pass to the next state. This let us to have a control of the sending Bytes, because the FPGA only receive information when is necessary.

State. 3 State Machine

Figure 7. Sending Byte CONCLUSIONES The use of an FPGA in the construction of industrial systems is very efficient, because it allows control over the whole system in a coordinated and synchronized way. Additionally, it is possible to control a set of mechanisms as presented in this report, so is possible to create a synchronized and controlled industrial network. It is intended to replace the camera from the computer for a digital camera with UART communication toward the FPGA, to sorting processes are performed on this platform and get a complete Embedded Vision System.

State. 1 State Machine

Figure 5. Reception Byte *State#2 By this SubVI, is implemented the calculus of the Invariant Moments of the captured image and is compared with the pattern image. .