Professional Documents
Culture Documents
Icoupler Digital Isolator: Adum1100
Icoupler Digital Isolator: Adum1100
Icoupler Digital Isolator: Adum1100
FEATURES
High data rate: dc to 100 Mbps (NRZ) Compatible with 3.3 V and 5.0 V operation/level translation 125C maximum operating temperature Low power operation 5 V operation 1.0 mA maximum @ 1 Mbps 4.5 mA maximum @ 25 Mbps 16.8 mA maximum @ 100 Mbps 3.3 V operation 0.4 mA maximum @ 1 Mbps 3.5 mA maximum @ 25 Mbps 7.1 mA maximum @ 50 Mbps 8-lead SOIC_N package (RoHS compliant version available) High common-mode transient immunity: >25 kV/s Safety and regulatory information UL recognized 2500 V rms for 1 minute per UL 1577 CSA Component Acceptance Notice #5A VDE Certificate of Conformity DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 VIORM = 560 V peak
GENERAL DESCRIPTION
The ADuM11001 is a digital isolator based on Analog Devices Inc. iCoupler technology. Combining high speed CMOS and monolithic air core transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives, such as optocoupler devices. Configured as a pin-compatible replacement for existing high speed optocouplers, the ADuM1100 supports data rates as high as 25 Mbps and 100 Mbps. The ADuM1100 operates with a voltage supply ranging from 3.0 V to 5.5 V, boasts a propagation delay of <18 ns and edge asymmetry of <2 ns, and is compatible with temperatures up to 125C. It operates at very low power, less than 0.9 mA of quiescent current (sum of both sides), and a dynamic current of less than 160 A per Mbps of data rate. Unlike other optocoupler alternatives, the ADuM1100 provides dc correctness with a patented refresh feature that continuously updates the output signal. The ADuM1100 is offered in three grades. The ADuM1100AR and ADuM1100BR can operate up to a maximum temperature of 105C and support data rates up to 25 Mbps and 100 Mbps, respectively. The ADuM1100UR can operate up to a maximum temperature of 125C and supports data rates up to 100 Mbps.
APPLICATIONS
Digital field bus isolation Opto-isolator replacement Computer-peripheral interface Microprocessor system interface General instrumentation and data acquisition applications
VDD2
VI 2 (DATA IN)
GND2
VO (DATA OUT)
GND2
02462-001
ADuM1100
NOTES 1. FOR PRINCIPLES OF OPERATION, SEE METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY SECTION.
Figure 1.
Rev. H
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 20012011 Analog Devices, Inc. All rights reserved.
REVISION HISTORY
3/11Rev. G to Rev. H Changes to Data Sheet Title ............................................................ 1 Changes to Ordering Guide .......................................................... 18 6/07Rev. F to Rev. G Updated VDE Certification Throughout ...................................... 1 Changes to Features and Endnote 1 ............................................... 1 Changes to Table 5 and Table 6 ....................................................... 9 Updated Outline Dimensions ...................................................... 18 Changes to Ordering Guide ......................................................... 18 3/06Rev. E to Rev. F Updated Format .................................................................. Universal Added Note 1 .................................................................................... 1 Changes to Table 1 ............................................................................ 4 Changes to Table 2 ............................................................................ 6 Changes to Table 3 ............................................................................ 8 Add Table 11 .................................................................................... 13 Inserted Power Consumption Section ......................................... 18 10/03Rev. D to Rev. E Changes to Product Name, Features, and General Description. 1 Changes to Regulatory Information .............................................. 6 Changes to DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics ................................................................................... 6 Changes to Absolute Maximum Ratings ....................................... 7 Changes to Recommended Operating Conditions ...................... 7 Changes to Ordering Guide ............................................................ 8 6/03Rev. C to Rev. D Changed DIN EN 60747-5-2 (VDE 0884 Part 2) Insulation Characteristics ................................................................................... 6 Updated Ordering Guide ................................................................. 8 Updated Outline Dimensions ....................................................... 13 4/03Rev. B to Rev. C Changes to Features and Patent Note .............................................1 Changes to Regulatory Information ...............................................6 Changes to Insulation Characteristics Section ..............................6 Changes to Absolute Maximum Ratings ........................................7 Changes to Package Branding..........................................................8 Changes to Method of Operation, DC Correctness, and Magnetic Field Immunity Section ................................................ 11 Replaced Figure 9 ........................................................................... 12 1/03Rev. A to Rev. B Added ADuM1100UR Grade ........................................... Universal Changed ADuM1100AR/ADuM1100BR to ADuM1100 .......................................................................... Universal Changes to Features and General Description ..............................1 Changes to Specifications .................................................................2 Added Electrical Specifications, Mixed 5 V/3 V or 3 /5 V Operation Table .................................................................................4 Updated Regulatory Information ....................................................6 Changes to VDE 0884 Insulation Characteristics .........................6 Changes to Absolute Maximum Ratings ........................................7 Changes to Package Branding..........................................................8 Updated TPC 3 to TPC 8..................................................................9 Deleted iCoupler in Field Bus Networks Section ....................... 11 Changes to Figure 8 ........................................................................ 12 Added Figure 9 and Related Text ................................................. 12 11/02Rev. 0 to Rev. A Edits to Features.................................................................................1 Edits to Regulatory Information .....................................................4 Edits to VDE 0884 Insulation Characteristics ...............................5 Added Revision History ................................................................ 12 Updated Outline Dimensions ....................................................... 12
Rev. H | Page 2 of 20
ADuM1100 SPECIFICATIONS
ELECTRICAL SPECIFICATIONS5 V OPERATION
All voltages are relative to their respective ground. 4.5 V VDD1 5.5 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 5 V. Table 1.
Parameter DC SPECIFICATIONS Input Supply Current Output Supply Current Input Supply Current (25 Mbps) (See Figure 5) Output Supply Current 1 (25 Mbps) (See Figure 6) Input Supply Current (100 Mbps) (See Figure 5) Output Supply Current1 (100 Mbps) (See Figure 6) Input Current Logic High Output Voltage Logic Low Output Voltage Symbol IDD1 (Q) IDD2 (Q) IDD1 (25) IDD2 (25) IDD1 (100) IDD2 (100) II VOH VOL 10 VDD2 0.1 VDD2 0.8 Min Typ 0.3 0.01 2.2 0.5 9.0 2.0 +0.01 5.0 4.6 0.0 0.03 0.3 Max 0.8 0.06 3.5 1.0 14 2.8 +10 Unit mA mA mA mA mA mA A V V V V V Test Conditions VI = 0 V or VDD1 VI = 0 V or VDD1 12.5 MHz logic signal frequency 12.5 MHz logic signal frequency 50 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only 50 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only 0 V VIN VDD1 IO = 20 A, VI = VIH IO = 4 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 4 mA, VI = VIL
SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width 2 Maximum Data Rate 3 For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 Maximum Data Rate3 For All Grades Propagation Delay Time to Logic Low Output 4, 5 (See Figure 7) Propagation Delay Time to Logic High Output4, 5 (See Figure 7) Pulse Width Distortion |tPLH tPHL|5 Change vs. Temperature 6 Propagation Delay Skew (Equal Temperature)5, 7 Propagation Delay Skew (Equal Temperature, Supplies)5, 7 Output Rise/Fall Time Common-Mode Transient Immunity at Logic Low/High Output 8 Refresh Rate Input Dynamic Supply Current 9 Output Dynamic Supply Current9
PW 25 PW 100 tPHL tPLH PWD tPSK1 tPSK2 tR, tF |CML|, |CMH| fr IDDI (D) IDDO (D) 3 35 1.2 0.09 0.02 6.7 150 10.5 10.5 0.5 3
40
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V
10
18 18 2 8 6
25
Rev. H | Page 3 of 20
ADuM1100
1
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common-mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
Rev. H | Page 4 of 20
ADuM1100
ELECTRICAL SPECIFICATIONS3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V VDD1 3.6 V, 3.0 V VDD2 3.6 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = VDD2 = 3.3 V. Table 2.
Parameter DC SPECIFICATIONS Input Supply Current Output Supply Current Input Supply Current (25 Mbps) (See Figure 5) Output Supply Current 1 (25 Mbps) (See Figure 6) Input Supply Current (50 Mbps) (See Figure 5) Output Supply Current1 (50 Mbps) (See Figure 6) Input Current Logic High Output Voltage Logic Low Output Voltage Symbol IDD1 (Q) IDD2 (Q) IDD1 (25) IDD2 (25) IDD1 (50) IDD2 (50) II VOH VOL 10 VDD2 0.1 VDD2 0.5 Min Typ 0.1 0.005 2.0 0.3 4.0 1.2 +0.01 3.3 3.0 0.0 0.04 0.3 Max 0.3 0.04 2.8 0.7 6.0 1.6 +10 Unit mA mA mA mA mA mA A V V V V V Test Conditions VI = 0 V or VDD1 VI = 0 V or VDD1 12.5 MHz logic signal frequency 12.5 MHz logic signal frequency 25 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only 25 MHz logic signal frequency, ADuM1100BR/ADuM1100UR only 0 V VIN VDD1 IO = 20 A, VI = VIH IO = 2.5 mA, VI = VIH IO = 20 A, VI = VIH IO = 400 A, VI = VIH IO = 2.5 mA, VI = VIH
SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width 2 Maximum Data Rate 3 For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 Maximum Data Rate3 For All Grades Propagation Delay Time to Logic Low Output 4, 5 (See Figure 8) Propagation Delay Time to Logic High Output4, 5 (See Figure 8) Pulse Width Distortion |tPLH tPHL|5 Change vs. Temperature 6 Propagation Delay Skew (Equal Temperature)5, 7 Propagation Delay Skew (Equal Temperature, Supplies)5, 7 Output Rise/Fall Time Common-Mode Transient Immunity at Logic Low/High Output 8 Refresh Rate Input Dynamic Supply Current 9 Output Dynamic Supply Current9
PW 25 PW 50 tPHL tPLH PWD tPSK1 tPSK2 tR, tF |CML|, |CMH| fr IDDI (D) IDDO (D) 3 35 1.1 0.08 0.04 10 100 14.5 15.0 0.5 10
40
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V
20
28 28 3 15 12
25
Rev. H | Page 5 of 20
ADuM1100
1
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. 2 The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common-mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
Rev. H | Page 6 of 20
ADuM1100
ELECTRICAL SPECIFICATIONSMIXED 5 V/3 V OR 3 V/5 V OPERATION
All voltages are relative to their respective ground. 5 V/3 V operation: 4.5 V VDD1 5.5 V, 3.0 V VDD2 3.6 V. 3 V/5 V operation: 3.0 V VDD1 3.6 V, 4.5 V VDD2 5.5 V. All minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25C, VDD1 = 3.3 V, VDD2 = 5 V or VDD1 = 5 V, VDD2 = 3.3 V. Table 3.
Parameter DC SPECIFICATIONS Input Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation Output Supply Current, Quiescent 5 V/3 V Operation 3 V/5 V Operation Input Supply Current, 25 Mbps 5 V/3 V Operation 3 V/5 V Operation Output Supply Current 1 , 25 Mbps 5 V/3 V Operation 3 V/5 V Operation Input Supply Current, 50 Mbps 5 V/3 V Operation 3 V/5 V Operation Output Supply Current1, 50 Mbps 5 V/3 V Operation 3 V/5 V Operation Input Currents Logic High Output Voltage 5 V/3 V Operation Logic Low Output Voltage 5 V/3 V Operation Logic High Output Voltage 3 V/5 V Operation Logic Low Output Voltage 3 V/5 V Operation SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width 2 Maximum Data Rate 3 For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 Maximum Data Rate3 For All Grades Propagation Delay Time to Logic Low/High Output 4, 5 5 V/3 V Operation (See Figure 9) 3 V/5 V Operation (See Figure 10) Symbol IDDI (Q) 0.3 0.1 IDDO (Q) 0.005 0.01 IDDI (25) 2.2 2.0 IDDO (25) 0.3 0.5 IDDI (50) 4.5 4.0 IDDO (50) 1.2 1.0 +0.01 3.3 3.0 0.0 0.04 0.3 5.0 4.6 0.0 0.03 0.3 1.6 1.5 +10 mA mA A V V V V V V V V V V 25 MHz logic signal frequency 25 MHz logic signal frequency 0 V VIA, VIB, VIC, VID VDD1 or VDD2 IO = 20 A, VI = VIH IO = 2.5 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 2.5 mA, VI = VIL IO = 20 A, VI = VIH IO = 4 mA, VI = VIH IO = 20 A, VI = VIL IO = 400 A, VI = VIL IO = 4 mA, VI = VIL 7.0 6.0 mA mA 25 MHz logic signal frequency 25 MHz logic signal frequency 0.7 1.0 mA mA 12.5 MHz logic signal frequency 12.5 MHz logic signal frequency 3.5 2.8 mA mA 12.5 MHz logic signal frequency 12.5 MHz logic signal frequency 0.04 0.06 mA mA 0.8 0.3 mA mA Min Typ Max Unit Test Conditions
VOH VOL
PW 25 PW 50 tPHL, tPLH 13 16
40
ns Mbps ns Mbps
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
20
21 26
ns ns
Rev. H | Page 7 of 20
ADuM1100
Parameter Pulse width Distortion, |tPLH tPHL|5 5 V/3 V Operation 3 V/5 V Operation Change in Pulse Width Distortion vs. Temperature 6 5 V/3 V Operation 3 V/5 V Operation Propagation Delay Skew (Equal Temperature)5, 7 5 V/3 V Operation 3 V/5 V Operation Propagation Delay Skew (Equal Temperature, Supplies)5, 7 5 V/3 V Operation 3 V/5 V Operation Output Rise/Fall Time (10% to 90%) Common-Mode Transient Immunity at Logic Low/High Output 8 Refresh Rate 5 V/3 V Operation 3 V/5 V Operation Input Dynamic Supply Current 9 5 V/3 V Operation 3 V/5 V Operation Output Dynamic Supply Current9 5 V/3 V Operation 3 V/5 V Operation
1
Symbol PWD
Min
Max 2 3
Unit ns ns
Test Conditions CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels
ps/C ps/C
ns ns
ns ns ns kV/s
CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels CL = 15 pF, CMOS signal levels VI = 0 V or VDD1, VCM = 1000 V, transient magnitude = 800 V
Output supply current values are with no output load present. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load. The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed. 3 The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed. 4 tPHL is measured from the 50% level of the falling edge of the VI signal to the 50% level of the falling edge of the VO signal. tPLH is measured from the 50% level of the rising edge of the VI signal to the 50% level of the rising edge of the VO signal. 5 Because the input thresholds of the ADuM1100 are at voltages other than the 50% level of typical input signals, the measured propagation delay and pulse width distortion can be affected by slow input rise/fall times. See the Propagation Delay-Related Parameters section and Figure 14 through Figure 18 for information on the impact of given input rise/fall times on these parameters. 6 Pulse width distortion change vs. temperature is the absolute value of the change in pulse width distortion for a 1C change in operating temperature. 7 tPSK1 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature and output load within the recommended operating conditions. tPSK2 is the magnitude of the worst-case difference in tPHL and/or tPLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. 8 CMH is the maximum common-mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common-mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common-mode voltage slew rates apply to both rising and falling edges. The transient magnitude is the range over which the common-mode is slewed. 9 Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 5 and Figure 6 for information on supply current variation with logic signal frequency. See the Power Consumption section for guidance on calculating the input and output supply currents for a given data rate and output load.
2
Rev. H | Page 8 of 20
ADuM1100
PACKAGE CHARACTERISTICS
Table 4.
Parameter Resistance (Input-to-Output) 1 Capacitance (Input-to-Output)1 Input Capacitance 2 IC Junction-to-Case Thermal Resistance, Side 1 IC Junction-to-Case Thermal Resistance, Side 2 Package Power Dissipation
1 2
Min
Max
240
The device is considered a 2-terminal device; Pin 1, Pin 2, Pin 3, and Pin 4 are shorted together, and Pin 5, Pin 6, Pin 7, and Pin 8 are shorted together. Input capacitance is measured at Pin 2 (VI).
REGULATORY INFORMATION
The ADuM1100 is approved by the following organizations. Table 5.
UL Recognized under 1577 component recognition program 1 Single/basic insulation, 2500 V rms isolation voltage File E214100
1 2
CSA Approved under CSA Component Acceptance Notice #5A Basic insulation per CSA 60950-1-03 and IEC 60950-1, 400 V rms (565 V peak) maximum working voltage File 205078
VDE Certified according to DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 2 Reinforced insulation, 560 V peak File 2471900-4880-0001
In accordance with UL 1577, each ADuM1100 is proof tested by applying an insulation test voltage 3000 V rms for 1 sec (current leakage detection limit = 5 A). In accordance with DIN V VDE V 0884-10, each ADuM1100 is proof tested by applying an insulation test voltage 1050 V peak for 1 sec (partial discharge detection limit = 5 pC). The * marking branded on the component designates DIN V VDE V 0884-10 approval.
CTI VIORM
Rev. H | Page 9 of 20
ADuM1100
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced isolation, only within the safety limit data. Maintenance of the safety data is ensured by means of protective circuits. The * marking on the package denotes DIN V VDE V 0884-10 approval for 560 V peak working voltage. Table 7.
Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage 150 V rms For Rated Mains Voltage 300 V rms For Rated Mains Voltage 400 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input-to-Output Test Voltage, Method B1 Input-to-Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Safety-Limiting Values Case Temperature Side 1 Current Side 2 Current Insulation Resistance at TS
180 160
SAFETY-LIMITING CURRENT (mA)
Conditions
Symbol
Unit
VIORM 1.875 = VPR, 100% production test, tm = 1 sec, partial discharge < 5 pC VIORM 1.6 = VPR, tm = 60 sec, partial discharge < 5 pC VIORM 1.2 = VPR, tm = 60 sec, partial discharge < 5 pC Transient overvoltage, tTR = 10 seconds Maximum value allowed in the event of a failure (see Figure 2)
V peak V peak
VIO = 500 V
TS IS1 IS2 RS
C mA mA
INPUT CURRENT
Parameter Operating Temperature ADuM1100AR/ADuM1100BR ADuM1100UR Supply Voltages 1 Logic High Input Voltage, 5 V Operation1, 2 (See Figure 11 and Figure 12) Logic Low Input Voltage, 5 V Operation1, 2 (See Figure 11 and Figure 12) Logic High Input Voltage, 3.3 V Operation1, 2 (See Figure 11 and Figure 12) Logic Low Input Voltage, 3.3 V Operation1, 2 (See Figure 11 and Figure 12) Input Signal Rise and Fall Times
1 2
Unit C C V V
02462-002
VIL
0.0
0.8
200
Figure 2. Thermal Derating Curve, Dependence of Safety-Limiting Value with Case Temperature per DIN V VDE V 0884-10
VIH
1.5
VDD1
VIL
0.0
0.5
1.0
ms
All voltages are relative to their respective ground. Input switching thresholds have 300 mV of hysteresis. See the Method of Operation, DC Correctness, and Magnetic Field Immunity section, Figure 19, and Figure 20 for information on immunity to external magnetic fields.
Rev. H | Page 10 of 20
Max +150 +125 +6.5 VDD1 + 0.5 VDD2 + 0.5 +25 +7 +20 +100
Unit C C V V V mA mA mA kV/s
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
All voltages are relative to their respective ground. See Figure 2 for information on maximum allowable current for various temperatures. 3 Refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the Absolute Maximum Rating may cause latch-up or permanent damage.
VO Output H L H1 X1
Figure 3 shows the package branding. * is the DIN EN 60747-5-2 mark, R is the package designator (R denotes SOIC_N), YYWW is the date code, and XXXXXX is the lot code.
ADuM1100AR, ADuM1100AR-RL7 8 ADuM1100BR, ADuM1100BR-RL7 8 ADuM1100UR, ADuM1100UR-RL7 8
Rev. H | Page 11 of 20
02462-003
ADuM1100
TOP VIEW (Not to Scale)
7 6 5
MAY BE USED FOR VDD1 . 2 PIN 5 AND PIN 7 ARE INTERNALLY CONNECTED. EITHER OR BOTH MAY BE USED FOR GND2.
Rev. H | Page 12 of 20
18
17
PROPAGATION DELAY (ns)
CURRENT (mA)
16
12 10 8 6 4
02462-005
tPHL
15
tPLH
5V 3.3V
14
13
02462-008
150
12 50
25
25 50 75 TEMPERATURE (C)
100
125
Figure 5. Typical Input Supply Current vs. Logic Signal Frequency for 5 V and 3.3 V Operation
5
14
4
PROPAGATION DELAY (ns)
13
tPLH
12
CURRENT (mA)
3 5V 2
tPHL
11
3.3V
02462-006
10
02462-009
150
9 50
25
75 25 50 TEMPERATURE (C)
100
125
Figure 6. Typical Output Supply Current vs. Logic Signal Frequency for 5 V and 3.3 V Operation
13
17
PROPAGATION DELAY (ns)
12
16
tPHL
15
11
tPHL
10
tPLH
tPLH
14
13
02462-007
02462-010
9 50
25
50 75 25 TEMPERATURE (C)
100
125
12 50
25
25 50 75 TEMPERATURE (C)
100
125
Rev. H | Page 13 of 20
ADuM1100
1.7
1.4 40C +25C
1.6
INPUT THRESHOLD, VITH (V)
1.3
1.4
1.0
0.9
02462-012
1.1 3.0 3.5 4.0 4.5 5.0 INPUT SUPPLY VOLTAGE, VDD1 (V)
5.5
0.8 3.0
5.5
Rev. H | Page 14 of 20
Pulse width distortion is the maximum difference between tPLH and tPHL and provides an indication of how accurately the input signals timing is preserved in the components output signal. Propagation delay skew is the difference between the minimum and maximum propagation delay values among multiple ADuM1100 components operated at the same operating temperature and having the same output load. Depending on the input signal rise/fall time, the measured propagation delay based on the input 50% level can vary from the true propagation delay of the component (as measured from its input switching threshold). This is because the input threshold, as is the case with commonly used optocouplers, is at a different voltage level than the 50% point of typical input signals. This propagation delay difference is given by LH = tPLH tPLH = (tR/0.8 VI)(0.5 V1 VITH (L-H)) HL = tPHL tPHL = (tF/0.8 VI)(0.5 V1 VITH (H-L)) where: tPLH and tPHL are the propagation delays as measured from the input 50% level. tPLH and tPHL are the propagation delays as measured from the input switching thresholds. tR and tF are the input 10% to 90% rise/fall times. VI is the amplitude of the input signal (0 to VI levels assumed). VITH (LH and, VITH (HL) are the input switching thresholds.
02462-014
tPLH
OUTPUT (VO)
tPHL
50%
LH 50%
HL
VITH(HL)
tPLH t'PLH
OUTPUT (VO) 50%
tPHL
t'PHL
02462-015
Rev. H | Page 15 of 20
ADuM1100
4
PULSE-WIDTH DISTORTION ADJUSTMENT, PWD (ns) PROPAGATION DELAY CHANGE, LH (ns)
5V INPUT SIGNAL 2
1
02462-016
10
10
Figure 16. Typical Propagation Delay Change due to Input Rise Time Variation (for VDD1 = 3.3 V and 5 V)
0
PROPAGATION DELAY CHANGE, HL (ns)
Figure 18. Typical Pulse Width Distortion Adjustment due to Input Rise/Fall Time Variation (at VDD1 = 3.3 V and 5 V)
1 5V INPUT SIGNAL
3
02462-017
10
Figure 17. Typical Propagation Delay Change due to Input Fall Time Variation (for VDD1 = 3.3 V and 5 V)
The impact of the slower input edge rates can also affect the measured pulse width distortion as based on the input 50% level. This impact can either increase or decrease the apparent pulse width distortion depending on the relative magnitudes of tPHL, tPLH, and PWD. The case of interest here is the condition that leads to the largest increase in pulse width distortion. The change in this case is given by PWD = PWD PWD = LH HL = (t/0.8 V1)(V VITH (L-H) VITH (H-L)), (for t = tr = tf) where: PWD = |tPLH tPHL| PWD = |tPLH tPHL|. This adjustment in pulse width distortion is plotted as a function of input rise/fall time in Figure 18.
Rev. H | Page 16 of 20
02462-018
ADuM1100
MAXIMUM ALLOWABLE CURRENT (kA)
Given the geometry of the receiving coil in the ADuM1100 and an imposed requirement that the induced voltage be at most 50% of the 0.5 V margin at the decoder, a maximum allowable magnetic field is calculated, as shown in Figure 19.
100
10
0.1
0.01 1k
10k
100k
1M
10M
100M
0.001 1k
10k
100k
1M
10M
100M
For example, at a magnetic field frequency of 1 MHz, the maximum allowable magnetic field of 0.2 kgauss induces a voltage of 0.25 V at the receiving coil. This is about 50% of the sensing threshold and does not cause a faulty output transition. Similarly, if such an event were to occur during a transmitted pulse (and was of the worst-case polarity), it would reduce the received pulse from >1.0 V to 0.75 V, still well above the 0.5 V sensing threshold of the decoder. The preceding magnetic flux density values correspond to specific current magnitudes at given distances away from the ADuM1100 transformers. Figure 20 expresses these allowable current magnitudes as a function of frequency for selected distances. As can be seen, the ADuM1100 is extremely immune and can be affected only by extremely large currents operated at high frequency and very close to the component. For the 1 MHz example noted, one would have to place a current of 0.5 kA 5 mm away from the ADuM1100 to affect the components operation.
Note that at combinations of strong magnetic field and high frequency, any loops formed by printed circuit board traces could induce sufficiently large error voltages to trigger the thresholds of succeeding circuitry. Care should be taken in the layout of such traces to avoid this possibility.
POWER CONSUMPTION
The supply current of the ADuM1100 isolator is a function of the supply voltage, the input data rate, and the output load. The input supply current is given by IDDI = IDDI (Q) IDDI = IDDI (D) (2f fr) + IDDI (Q) The output supply current is given by IDDO = IDDO (Q)
3
IDDO = (IDDO (D) + (0.5 10 ) CLVDDO) (2f fr) + IDDO (Q) f > 0.5fr where: IDDI (D), IDDO (D) are the input and output dynamic supply currents per channel (mA/Mbps). CL is output load capacitance (pF). VDDO is the output supply voltage (V). f is the input logic signal frequency (MHz, half of the input data rate, NRZ signaling). fr is the input stage refresh rate (Mbps). IDDI (Q), IDDO (Q) are the specified input and output quiescent supply currents (mA).
Rev. H | Page 17 of 20
1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) COPLANARITY 0.10 SEATING PLANE
0.50 (0.0196) 0.25 (0.0099) 8 0 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157)
45
COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
Figure 21. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches)
ORDERING GUIDE
Model1 ADuM1100AR ADuM1100AR-RL7 ADuM1100ARZ ADuM1100ARZ-RL7 ADuM1100BR ADuM1100BR-RL7 ADuM1100BRZ ADuM1100BRZ-RL7 ADuM1100UR ADuM1100UR-RL7 ADuM1100URZ ADuM1100URZ-RL7
1
Temperature Range 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +105C 40C to +125C 40C to +125C 40C to +125C 40C to +125C
Maximum Data Rate (Mbps) 25 25 25 25 100 100 100 100 100 100 100 100
012407-A
Package Description 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel 8-Lead SOIC_N 8-Lead SOIC_N, 1,000 Piece Reel
Package Option R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8 R-8
Rev. H | Page 18 of 20
ADuM1100 NOTES
Rev. H | Page 19 of 20
ADuM1100 NOTES
20012011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D02462-0-3/11(H)
Rev. H | Page 20 of 20