Dr.

Abhijit RAsati
EEEDepartment,
BITS,Pilani
Floor-planning and pin Assignment
Floor-planning:
Floor planningisconcernedwith Floor-planningisconcernedwith
Selectinggoodlayout alternativesfor eachblock,
aswell astheentirechip.
The area of each block can be estimated after partitioning. The
estimation isbasedapproximatelyon:
Thenumber andthetypeof componentsinthat block yp p
Interconnect arearequiredwithintheblock
The actual rectangular shape of the block be varied within a pre-
specifiedrange specifiedrange.
Floor-planningis acritical step, as it sets upthegroundwork for a
goodlayout.
Floor-planning Problem:
The problem of assigning location to a fixed block on layout The problem of assigning location to a fixed block on layout
surfaceiscalledtheplacement problem.
If some or all blocks are flexible then the problemis called the
fl l i bl floor-planning problem.
Thus, floor-planning istheplacement of flexibleblocks, i.e.
blockswithfixedarea
but unknowndimensions.
Floor-planning aretypicallyusedinhierarchical physical design.
For small standardcell design: For small standardcell design:
floor-planingproblemissimplytheplacement problem.
For largestandardcell design:
circ it is partitioned into se eral regions hich are floor circuit is partitioned into several regions, which are floor-
planed, beforecellsareplacedinregions.
Problem formulation:
Input: Input:
B
1
,B
2
,B
3
B
n
are blocks to be placed on chip.
a
1
,a
2
,a
3
a
n
are area of each block.
A
l
l b d th t ti A
i
l
lower bound on the aspect ratio
A
i
h
upper bound on the aspect ratio
Output :
Block B
i
has height h
i
&width w
i
such that A
i
l s
[h
i
/w
i
]
s
A
i
h
In addition to finding the shapes of the blocks, the floor-
planningalgorithmhastogenerateavalidplacement suchthat planning algorithm has to generate a valid placement such that
the area of the layout is minimized.
Designstylespecificfloor-planningProblems:
Full customdesign
Standardcell design Standardcell design
Gatearraydesign
d d ll d i d i l d i i i i d Instandardcell designor gatearray designlargedesignis partitioned
intoseveral regions.
Apart from the standard cell design and full custom block layout p g y
style, acombinationof bothisalsocommon.
Chip planning problem:
Planning of interconnect is done in addition to floor-planning Planning of interconnect is done in addition to floor planning
problem.
Floor-planning and placement either ignore the interconnect or
id it d bj ti consider it asasecondaryobjective.
Chip planning problem:
Input:
Sameinput asthat of floor-planningproblem. Same input as that of floor planning problem.
Additional inputs:
S S S S aresignals S
1
,S
2
,S
3
S
m
are signals.
Each of these signal have criticality, width, source and sink.
Output:
Same input as that of floor-planning problem.
Classificationof floor-planningalgorithm:
Constraint basedmethods.
Integer programmingbasedmethods.
Rectangular dualization based methods.
Hierarchical treebasedmethods Hierarchical treebasedmethods.
SimulatedEvolutionalgorithms
TimingDrivenfloor-planningalgorithms
The partitioning process generates a group of subcircuits and their
Rectangular dualization based methods:
The partitioning process generates a group of subcircuits and their
interconnections.
The output froma partitioning algorithmcan be represented as a
hG (V E) h graphG=(V, E) where
Theverticesof thegraphcorrespondtothesubcircuits
The edges represent the interconnections between the
subcircuit.
Graphmodel
Circuit
Graph model
Floorplanapproach:
convert thisgraphintoitsrectangular dual convert thisgraphintoitsrectangular dual
Rectangular dual of graph G =(V, E) consists of non-overlapping
rectangleswhichsatisfythefollowingproperties:
E h t V d t di ti t t l R Each vertex v
i
eV corresponds to a distinct rectangle R
i
,
1<i<|V|
For every edge (v
i
,v
j
) the corresponding rectangles R
i
and R
j j j
andareadjacent inrectangular dual.
Rectangular Dual
Graph model
Rectangular Dual
Planar triangular graph(PTG) or Properly Triangulatedplanar (PTP)
Graph:
It hasfollowingproperties: It hasfollowingproperties:
P1: Everyface(except theexterior) isatriangle.
P2 :All internal verticeshavedegree> 4.
P3: All c clesthat arenot facesha elength> 4 P3: All cyclesthat arenot faceshavelength> 4.
Th h f Fi ( ) i l t ti The graph of Figure (a) violates properties:
P2: since the degree of the internal vertex D is less than four.
P3: Also the cycle A - B - C is not a face and has length less than
four.
The graph (b) is a PTP graph.
For graph to have PTP drawing:
Twochecksperformedare:
Check1: Cv =0alsoCv shouldnot begreater than2 Check1: Cv
ij
=0 also Cv
ij
should not be greater than 2.
Check2: Number of interior faces (f)= number of triangles (t)
1 | ) ( | | ) ( | + = H V H E f
E(H)=Number of edges
V(H)=Number of vertices

e
=
) ( ) , (
3
1
H E j i
ij
cv t
In a graph:
F h d (i j) For each edge (i, j),
determine the number of common vertices of ( i , j), cv
ij
Example 1:
Figure
( ) Ch k1 P Ch k2 f il (f ) (a) Check 1: Pass, Check 2: fail (f = t)
f=6-4+1=3, t=12/3=4
(b) Check 1: Pass, Check 2: Pass (f =t)
f =8 - 5 +1 =4 and t =12/3=4.
Check if graph to have PTP drawing :
1 | ) ( | | ) ( | + = H V H E f

=
) ( ) (
3
1
H E j i
ij
cv t
A graph which passes both checks:
Check1: Pass , Check 2: Pass (f=t)
e ) ( ) , (
3
H E j i
f = 16- 9 + 1 = 8
t =24/3= 8.
Therefore it is PTP graph. g p
Convert it to planar diagraph (PDG ).
Toconstruct aPDG, followingverticesareidentified.
A northwest (NW),
A northeast (NE) A northeast (NE),
A southwest (SW)
A southeast (SE)
Inour exampleNW=1, NE=7, SW=3andSE=9.
NW to NE define the top boundary
(vertices 1,4,6,7)
S S d fi h b b d SW to SE define the bottom boundary
(vertices 3,9)
NW to SW define the left boundary y
(vertices 1,2,3)
NE to SE define the right boundary
(vertices789) (vertices 7,8,9)
vertices 1, 4, 6, 7, 8, 9, 3, and 2 make-up the outer boundary.
Pl di h Planar diagraph
Given a Planar Triangular Graph (PTG), a planar diagraph is
constructedasshowninfigure.
Planar diagraph Planar diagraph
Planar diagraphiscanbe convertedtofloorplanasshowninfigure. Planar diagraphiscanbe convertedtofloorplanasshowninfigure.
Slicing floor-plans:
All the floor-plans that can be generated with min-cut bi- p g
partitioningareslicingfloor-plans.
A tree representing the hierarchy of partitioning is called a
floor-plantree floor-plantree.
Each leaf represents a basic rectangle and each node a
compositerectangle.
Slicing Floorplan
Slicing Tree
Another Slicing Tree
A slicingstructurecanbemodeledbyabinarytreewithN leavesand
N-1nodes.
In this binary tree, each node represents a vertical cut line or
horizontal cut line, andeachleaf abasicrectangle. , g
Non-Slicing floor-plans:
(a) Shows a floor-plan for which there is no valid slicing tree.
Horizontal and Vertical adjacency graphs:
Representation of topological placements.
Sli i d li i fl l b d l db i f di d Slicing and non-slicing floor plans can be modeled by a pair of directed
acyclic graph
Each block is modeled by a vertex. y
Horizontal adjacency graphs: Arcs model vertical channels
Vertical adjacency graphs: Arcs model horizontal channels
Adjacencygraphscanbeusedtodeterminetheminimumrequired Adjacency graphs can be used to determine the minimum required
width, height, and area of the corresponding rectangular floorplan.
Q: For therectangular floorplanof figureassumethecellshavethe
sizesasgivenintable.
Usetheadjacency graphstodeterminetheminimumrequiredwidth
andheight of thefloorplanfor agivenslicingtree.
x
1
>2 y
1
>1 I
1
={2,1}
x
2
>2 y
2
>2 I
2
={2,2}
2
y
2 2
{ , }
x
3
>4 y
3
>3 I
3
={4,3}
x
4
>3 y
4
>1 I
4
={3,1}
x >1 y >3 I {1 3} x
5
>1 y
5
>3 I
5
={1,3}
x
6
>1 y
6
>1 I
6
={1,1}
x
7
>3 y
7
>2 I
7
={3,2}
x
8
>3 y
8
>1 I
8
={3,1}
x
9
>2 y
9
>4 I
9
={2,4}
Pin assignment on blocks:
Thisprocessof identifyingpinlocationsiscalledpinassignment.
Thepurposeof pinassignment istodefinethesignal that eachpinwill
receive receive.
Thepinassignment problem:
Givenaset of terminals T
1
,T
2
, T
3
....T
n
andaset of pinsP
1
,P
2
,P
3
,....P
m
,
where, m>n.
Assign each Ti terminal to appropriate pin Pi, such that objective
functionisminimized(e.g. routingcongestions, channel density)
(a) If the blocks are already designed-
It maybepossibletoexchange: y p g
few'functionally- equivalent' pins.
few 'equipotential' pins.
Such pins are defined for standard cell and for cells in gate array
d i designs.
Equipotential pins:
In standard cell designs, equipotential pins appear as feed- g q p p pp
throughs.
Wiringcost isminimized.
Reducescongestion (number of crossovers) Reducescongestion (number of crossovers)
Functionally- equivalent pins:
Exchangingthesignals does not haveany effect onthecircuit g g g y
functionality.
Wiringcost isminimized.
Reducescongestion (number of crossovers) Reducescongestion (number of crossovers)
Channel Pin Assignment:
Theroutingcanbeimprovedbymovingthepinssuchthat it requires g p y g p q
lesser tracks.
(a) requiresthreetrack.
(b)requiresonetrack ( ) q
Spacenot occupied by theblocks areused for routing arecalled as
routingregions routingregions.
Routing regions definition consist of partitioning the routing area
intoset of non-intersectingrectangular regionscalledchannels.
H i t l h l A h l ll l t th i Horizontal channel: A channel parallel tothe x- axis.
Vertical channel: A channel parallel tothe y- axis.
Typesof channel basedonshape:
'L' typechannel
'T' typechannel T typechannel
'+' typechannel
In most cases, horizontal and vertical channels can touch at T-
intersections.
'L' type channel and 'T' type channel can be completely routed
usingchannel routers. g
The '+' type junctions are more complex and require the use of
switchboxrouters.
Thereforeit is advantageous totransformall '+' typejunctions into Thereforeit is advantageous totransformall +typejunctions into
T-typejunctions.
Inbetweenblockstherearetwotypesof routingregions:
Channels Channels
2D-switchboxes.
In2D-switchboxesroutingisperformedinsideabox.
T i l t b f ti i d d t i l Terminals are preset before routing is doneand terminals can
beplacedonanyof the4sidesof thebox.
In multilayer routing, abovetheplaced blocks, theentire routing
spaceisavailable, whichis partitionedit intosmaller regionscalled p , p g
3Dswitchboxes.
Generallytopmetal layersaredividedinto3Dswitchbox.
In 3D-switchbox terminals can beplaced on any of the6 sides of In 3D-switchbox terminals can beplaced on any of the6 sides of
thebox.
SlicingFloorplan Slicing Floorplan
Slicing Tree
Another Slicing Tree
Weroutethecells inthereverseorder of slices, so that eachroute
isachannel route.