Magnetic Materials and Devices For MRAM Technology

Magnetic Materials and Devices for MRAM Technology
Jon Slaughter
TM
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006. Eintell5503
Outline
MRAM Overview 1st Generation Product

Technology Reliability Applications 90 nm CMOS-node MRAM demonstration Spin Transfer MRAM
Scaling
Future directions Summary
Slide 1
TM
Freescale and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. Freescale Semiconductor, Inc. 2006.
MRAM Advantages
Nonvolatile Fast Unlimited Cycles Flexible & Robust Data Retention 10 years Symmetrical Read/Write
35ns for 4Mb at 0.18m technology node
Endurance (>1015)
Data stored by magnetic polarization
Integrated with Existing CMOS Baseline Compatible with Embedded Designs Highly Reliable
Slide 2
TM
Technology Comparison
SRAM Read Speed Write Speed Cell Density Non-volatility Endurance Cell Leakage Fastest Fastest Low No Unlimited Low/High DRAM Fast Fast High No Unlimited High Flash Fast Slow High Yes Limited Low FeRAM Fast Medium Medium Yes Limited Low PRAM Fast Medium High Yes Limited Low MRAM Fast Fast Med/High Yes Unlimited Low
High performance symmetrical read and write timing Non-volatile with unlimited read-write endurance Low leakage and low voltage operation Easy integration for embedding in system-on-a-chip Scalable for future generations
Slide 3
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1st Commercial MRAM Freescale 4Mb MR2A16A Now in volume production
Slide 4
TM
4Mb MRAM Memory Circuit

MR2A16A: 4 Mb Toggle MRAM
35ns Speed read/write speed Unlimited Endurance Date retention >>10 Years 256Kx16bit organization 3.3V single power supply Fast SRAM pinout (center power
and ground) Commercial Temperature (0-70C) RoHS Compliant TSOP type-II package Uses Freescale toggle-bit technology
Slide 5
TM
MRAM Memory Cell

Bit Line
i
Magnetic Field Flux concentrating cladding layer
Di g
MTJ
it
Li
ne
Inlaid Copper interconnects Isolation Transistor
Slide 6
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MTJ Stack Key Parameter Summary
Top electrode Free M2 Ru Free M1 AlOx Fixed Ru Pinned AF pinning layer Seed Base electrode MMT
Slide 7
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Top Electrode (Ta)

Free SAF: Thickness uniformity <0.5% for Hsat control
AlOx tunnel barrier: (RA-wafer)<5%, (Al)<0.5% Pinned SAF: Thickness uniformity <1%, high fixing field PtMn alloy Composition tolerance 1% Bottom electrode: RMS Roughness: < 5
4Mb Memory Cell

M5-BL TE i
Program path for Writing information M3

M2 Thk Oxide Xtor
N+ N+
V4 M4-DL V3 V2 V1 M1
N+ P-
TJ MVia
TVia i BE
Pass Xtor
Pass Xtor
Group Select
Sense Path for bit cell reading

N+
N+
N+
N+
Layer Name M1-3 Via1-4
M4-DL MVia
BE
TJ
TVia
TE
M5-BL
Slide 8
TM
MRAM 4Mb bit cell

Metal 5 Cu
Cu
Metal 4 Via 3 Metal 3 Via 2 Metal 2

Al Al
MRAM module
MTJ
Metal 5
Front End 0.18 m CMOS
Via 1 Metal 1 Contact

Al
Metal 4
Bit cell
Slide 9
TM
Free Layer Field Response
Conventional Free Layer: switch H=0 0
SAF Free layer: spin flop H=0 0
Slide 10
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Toggle MRAM Switching Sequence

H2 Hard Axis Easy Axis Hard Axis H1 I1 Easy Axis Hard Axis H1 I1 I2 Easy Hard Axis Axis H2 I2 Easy Axis Hard Axis Easy Axis
Write Line 1 Write Line 2
On Off On Off
Write Line 1 Write Line 2 t0 t1 t2 t3 t4
Slide 11
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Toggle-Bit Selection
High bit disturb margin All bits along -selected

current lines have increased energy barrier during programming
Toggle
Slide 12
TM
Measured Switching from 4Mb Toggle-MRAM

4Mb, March 6N Toggle Map No -select disturbs Large operating region Operating region
Conventional MRAM
ibit
Operating region
0% switching region (no disturbs)
idigit
Slide 13
TM
ibit idigit
Tunnel Junction Reliability: Read
1) Dielectric Breakdown (catastrophic)

7000
2) Resistance Drift (gradual)
5000 4000 3000 2000 1000 T=175 C 0 1 10 100 1000 1.0V 0.8V
0.6V
Number of Bits @ R
6000
Resistance []
Low State
Margin before drift
High State
Necessary margin for spec. readout speed
Margin after drift
10000
100000
Time [s]
Bit Resistance
Slide 14
TM
MRAM TDDB
1.102 175
99 95 90 80 70 60 50 40 30 20 10 5 3 2 1
125C, 150C, 175C 1.1V 1.3V
1.151 175 1.201 150 1.201 175 1.246 175
1.251 125
Percent
1.251 150
1.287 175
Slo pe :1 .86
1.298 150
1.301 125
0.0001
0.0010
0.0100
0.1000
1.0000
Hours
~27x/0.1V Ea: 1.21 eV
9 TDDB Reliability far exceeds 10 years at operating voltage.

Slide 15
TM
Resistance drift vs. bias
1.00
R normalized
R generally decreases over time more at high bias/high T R drift will cause bits to fail over time adds to R distribution
0.6V 0.7V 0.8V 0.9V 1.0V 0.1
0.95 0.90 0.85 0.80
Distribution of R drift very tight all bits drift with a very similar rate
T=120C 1 10 100 1000
Time [min]
9 Worst case drift is less <1.5% in 10 years
Slide 16
TM
Resistance drift scaling

1.00
Increasing bias shifts curve along logt axis curves overlap when time axis is rescaled Bias stress is a true accelerator
0.6V 0.7V 0.8V 0.9V 1.0V 0.1
R normalized
0.95 0.90 0.85 0.80
speeds up drift mechanism does not introduce new mechanism

T=120C 1 10 100 1000
Scaling factor t* can be used for extrapolations

1E7
Time [min]
1.00
R normalized
Scaling Factor
0.95 0.90 0.85
25% d.c -1% 0.6V t/t*=2500 0.7V t/t*=400 0.8V t/t*=50 0.9V t/t*=6.5 1.0V t/t*=1 1
100% d.c -2.2%
1000000 100000 10000 1000 100 10 1 0.1
3*10
10 years at 0.25V 1.75 min at 1V
0.80 1E-4 1E-3 0.01 0.1
10 100 1000
0.01 0.00
0.25
0.50
0.75
1.00
1.25
Time [min]
Slide 17
TM
Bias [V]
4Mb MRAM Tested Reliability
1.E+12 1.E+11
TDDB and Drift Lifetimes, 90% LCL
1 FIT Drift,TDDB Life (hrs)
1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 50 60 70
Intrins ic TDD
4Mb A rray D rift
Life
10 Year Reliability
80
90
100
Junction Temperature Usage Temp (C) (C)
Slide 18
TM
Energy Barrier for Nonvolatile Data Retention = Eb/ kbT Thermal energy can cause
bit flip if barrier too low E
kbT
Eb
10-year data retention

> 70 required for 1 FIT quality
> 1 FIT = 1 error in 10,000 parts in 10 yrs
0
Slide 19
TM
Thermal activation in zero applied field Data retention
N = N 0 (1 e
boundary for 1 failure
1.E+07
t 0 e
measured data with NO failures
N = number of flipped bits N0 = Total number of bits in sample t = time at temperature 0 = attempt time = magnetic energy barrier divided by kbT
time at temp (sec)
1.E+06 1.E+05 1.E+04 1.E+03 1.E+02 150
Theoretical curve of time to observe 1 state change in 500 4Mb parts versus measurement temperature with an = 70 @ 85C Measured data for time with NO observed state changes in 500 4Mb parts
170 190 210 230 250
temp (C)
Over 3000 4Mb parts tested in total with no observed thermally induced state changes indicating all bits in sample have >> 70
Slide 20
TM
Markets and Applications Standalone and Embedded
Slide 21
TM
Example: Battery-backed SRAM Replacement

MRAM: single chip solution
Addr/Data Bus
SRAM
MRAM
MCU
CE
Control Chip
Battery
Problems Multiple parts required System design complexity Board space and weight Battery contact failure Limited life Manufacturing complexity Environmental concerns
Slide 22
TM
Benefits Single chip solution Simple system design Small profile No battery Unlimited life Manufacturing simplification Environmentally friendly
Example: RAID Storage
The Application

Redundant Array of Inexpensive Disks (RAID 0-7 & Hybrids) RAID systems are found in Imaging, Video, Audio, Web sites, emerging multimedia programs, transaction processing systems, mission critical backup solutions for Hospitals, Police, Banking and Insurance firms have ever increasing needs for high transfer rates and storage capacity. Address Vectors & System Configuration Disk Error Recovery
RAID Controller Chip
Configuration Data
MRAM Improves Performance

Fast read & write of 35ns No erase before write improves speed Unlimited read & writes practically infinite cycles Byte writeable greater granularity Non volatile memory increase security & integrity of data Fail Safe RAID cache High Data Availability without BBSRAM difficulties
Slide 23
TM
RAID Journal
RAID Controller
Critical Cache Disk Arrays
Embedded MRAM
Uses standard CMOS MRAM can be readily inserted between two existing
levels of metal
Provides smaller die size,performance improvement and

design flexibility
SRAM
DSP SRAM/ Logic NVM
MRAM MRAM Logic
Insertion does not change underlying CMOS parameters
ROM Logic
Logic
Logic
MRAM
Logic
MRAM
Logic MRAM
SRAM
Die Size =1
Slide 24
TM
Die Size =0.8

Converged Memory
Scaling Toggle MRAM 90 nm CMOS Demonstration
Slide 25
TM
MR for MgO/NiFe MTJ Material
MR>90%
MR (%)
100 80 60 40 20 0 1 10 (k R ) cell (k R ) cell 100 1000
Can adjust MgO thickness

to optimize resistance over broad range
Top electrode
NiFe Ru NiFe MgO
Highest reported for NiFe 2X higher than with AlOx
350 C 300 C 265 C

o o
Ru
Pinning
350 C post-anneal needed

for full MR
~270 C for AlOx
Base electrode
Slide 26
TM
MRAM Cell Integration in 90nm BEOL

Full integration of MgO-based MRAM devices with 90nm front end CMOS. MRAM process with clad Cu write lines. 8 kb arrays of memory cells Cell Size 0.29 m2 Linear shrink from 180nm MTJ resistance of 1kohm-m2
0.2 9 Bit m 2 Ce ll
MR AM
90n m
CM O
Toggle write characteristics
Slide 27
TM
90nm MRAM Read/Write Endurance

State 1
Data Out
State 0
Read 0 Write 1
Read 1 Write 0
Read 0 Write 1
Write Control Read Control
Passed >1e12 read/write cycles test

Slide 28
TM
Breakdown of MgO/NiFe MTJ Bits

MgO barrier consistently
BreakdownVoltage Voltage [V] Breakdown (V)
higher Vbd for given RA 0.15V improvement ~ 10100x longer life Vbd distributions are wider than for AlOx material
Gaussian Probability Plot of Vbd Barrier = MgO
2.2 2.0 1.8 1.6 1.4 1 Barrier AlOx MgO 10
99 95 90
Percent [%]
80 70 60 50 40 30 20 10 5 1 1.4
RA (k-m2)
RA (kOhm*um^2)
1.5
1.6
1.7
1.8
1.9
2.0
2.1
2.2
Vbd [V]
Slide 29
TM
=2.3%
Toggle MRAM Scaling

MRAM Technology
0.18m 4Mbit 7.1mm2/Mb 1.26m2 0.28m2 90nm (projected) 32 Mbit < 0.8mm2/Mb 0.29m2 0.044m2
Memory size / density
Cell size Magnetic bit size
Read/Write Endurance
> e^15
> e^15
Access time read/write
25ns / 25ns
15ns / 15ns
Slide 30
TM
Scaling Summary
Demonstrated integration of MgO-based MTJ material

MR>90% with NiFe SAF free layer for toggle MRAM
> Highest MR ever reported with NiFe
Critical MgO material properties evaluated

Bias dependence similar to AlOx Breakdown voltage higher than AlOx (good reliability expected)
Demonstrated 0.29m cell in 90 nm CMOS with MgO

Indicates capability to make and integrate high-MR material for high-speed MRAM at 256Mb densities
Slide 31
TM
Future Directions Spin Transfer Switching
Slide 32
TM
Standard vs. Spin Transfer MRAM

Standard MRAM bit line write current H-field magnetic tunnel junction IDC free magnet tunnel barrier fixed magnet SMT MRAM
H-field Isolation transistor digit line write current Isolation transistor Current IDC flows through MTJ and transistor
Fixed magnet polarizes IDC Spin-transfer torque programs free magnet Conservation of angular momentum
Cross-point architecture
Current along bit line and digit line to switch at intersection
Slide 33
TM
Spin Transfer MRAM Processing

CoFeB free layer MgO barrier
Low RA ~ 5 m2 MR ~ 100% Conventional photolithographic patterning 0.1 m 0.17 m bits 200 mm wafer ~0.5 mA critical currents 5 - 15% within die 1-sigma switching distribution width
(a 0.9 (b 25
0.6
V write relative (%)
20 15 10 5 0 0 5
Low High
Iwrite (mA)
0.3 0 -0.3 -0.6 -0.9 0
Low High
Frequency (arb. units)
2 4 6 8 10 12 Wafer number
(c
High
10 15 20 25 Die number
Low
12 8 4 0
0.1
-1.0
-0.5
0.0
0.5
1.0
Vwrite (V)
Slide 34
TM
Prospects for Spin Transfer MRAM
Advantages:
High density Stable bits with modest switching current ( < 1mA) High speed No neighboring or -select disturbs Switching current decreases with bit area
Challenges:
Write current flows through MTJ itself
> Reliability > Need to reduce critical currents to use minimum sized transistor
Slide 35
TM
MRAM Summary
First commercial MRAM product in industry Only memory technology today with characteristics of non
volatility, fast read/write, and unlimited endurance Reliability has been demonstrated to exceed all other existing nonvolatile memories
No fatigue mechanism observed 4Mb MRAM with 35ns read/write access time Enabled by advancement in MTJ material and Toggle Write
Ease of integration ideal for embedded space

Adds new functionality to SOC applications Integration at backend provides process compatibility and flexibility
Demonstrated scalability
Slide 36
TM

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Magnetic Materials and Devices for MRAM Technology

MRAM Overview 1st Generation Product

Future directions Summary

1st Commercial MRAM Freescale 4Mb MR2A16A Now in volume production

4Mb MRAM Memory Circuit

MRAM Memory Cell

Inlaid Copper interconnects Isolation Transistor

MTJ Stack Key Parameter Summary

Top Electrode (Ta)

4Mb Memory Cell

Program path for Writing information M3

Sense Path for bit cell reading

Layer Name M1-3 Via1-4

MRAM 4Mb bit cell

Metal 4 Via 3 Metal 3 Via 2 Metal 2

Front End 0.18 m CMOS

Via 1 Metal 1 Contact

Free Layer Field Response

Conventional Free Layer: switch H=0 0

SAF Free layer: spin flop H=0 0

Toggle MRAM Switching Sequence

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2

Write Line 1 Write Line 2 t0 t1 t2 t3 t4

High bit disturb margin All bits along -selected

Measured Switching from 4Mb Toggle-MRAM

0% switching region (no disturbs)

Tunnel Junction Reliability: Read

1) Dielectric Breakdown (catastrophic)

2) Resistance Drift (gradual)

Margin before drift

Necessary margin for spec. readout speed

Margin after drift

125C, 150C, 175C 1.1V 1.3V

1.151 175 1.201 150 1.201 175 1.246 175

~27x/0.1V Ea: 1.21 eV

9 TDDB Reliability far exceeds 10 years at operating voltage.

Resistance drift vs. bias

0.95 0.90 0.85 0.80

Resistance drift scaling

0.95 0.90 0.85 0.80

speeds up drift mechanism does not introduce new mechanism

Scaling factor t* can be used for extrapolations

0.95 0.90 0.85

100% d.c -2.2%

1000000 100000 10000 1000 100 10 1 0.1

10 years at 0.25V 1.75 min at 1V

0.80 1E-4 1E-3 0.01 0.1

4Mb MRAM Tested Reliability

TDDB and Drift Lifetimes, 90% LCL

1 FIT Drift,TDDB Life (hrs)

1.E+10 1.E+09 1.E+08 1.E+07 1.E+06 1.E+05 1.E+04 1.E+03 50 60 70

4Mb A rray D rift

Junction Temperature Usage Temp (C) (C)

10-year data retention