Application Report

SLUA653B Revised July 2013

1
5W USB Flyback Design Review/Application Report
Michael OLoughlin Senior Power Applications Engineer

Introduction:
In USB and isolated low power converter designs-quasi resonant and discontinuous conduction mode
flyback converter topologies are a popular choice, due to their low parts count and relatively low cost.
To reduce the cost even further, TI has developed a quasi-resonant/discontinuous current mode flyback
controller with primary-side control. This removes the need for optocoupler and TL431 feedback
circuitry reducing the cost of these low power designs even more. To achieve relatively low no load
input power and regulate the output voltage and output current this device uses a control methodology
known as control law. This control methodology uses a combination of primary peak current amplitude
modulation (AM) and frequency modulation (FM) to regulate the output current and voltage please refer
to the data sheet [1] for details. This application report reviews the design of the 5W adapter,
UCC28700EVM-068, evaluation module [2] using the UCC28700 power supply controller. The design
calculations are based on typical values. In a production design the values need to be modified for
worst case conditions. Also note there is a MathCAD design tool [3] that goes along with this
application note to make the power supply design process easier using this device.
Design Specifications:

Description Minimum Typical Maximum Units
RMS Input Voltage 90 (VINMIN) 115/230 265 (VINMAX) V
No Load Input Power 30 (PINL) mW
Output Voltage 4.75 5 (VOUT) 5.25 V
Output Voltage Ripple 100 (VRIPPLE) mVpp
Output Load Step
(0.1 to 0.6A), (0.6 to 0.1A)
4.1 (VOTRM) 6.0 V
Output Current 1(IOUT) A
Switching Frequency 105 (fMAX) kHz
Full Load Efficiency
(230/115V RMS input)
73() %
Table 1, Design Specifications













SLUA653B
2 5W USB Flyback Design Review/Application Report

Functional Schematic:
V
IN
D
A
D
B
D
C
D
D
2
6
5
3
4
1
UCC28700
CS
VDD DRV
GND
CBC/
NTC
T1
T1
VS
V
OUT
+
V
OUT
-
C
A
C
B
L
A
R
S1
R
S2
R
CBC
R
LC
R
F1
C
DD
D
Z
R
S
C
S
C
OUT
R
CS
R
G2
R
G1
R
Z
R
T
3.01k
D
E
D
F
D
G
10
10k
330nF
22
N
P N
S
N
A
R
L
10
470uH
Q
A
1nF

Figure 1, UCC28700 5W Offline Flyback Functional Schematic

Selecting RCB/NTC Resistor:
In this design cable compensation was not used and resistor R8 was not populated.
Please refer to the data sheet on how to setup cable compensation [1].

Initial Power Budget:
To meet the efficiency () goal an initial power loss budget (P
BUDGET
) needs to be set.

W A V I V P
OUT OUT OUT
5 1 5 = = =

W P
P
P
OUT
OUT
BUDGET
85 . 1
74 . 0
~ |
.
|

\
|
=

Bridge Rectifier Selection (D
A
..D
D
):
For this design a 600V, 0.8A, bridge rectifier from Diodes Incorporated was chosen for the bridge
rectifier diode (D
A
.. D
D
), part number HD06.

V V
FDA
1 = , forward voltage drop of bridge rectifier diode (V
FDA
)


SLUA653B
5W USB Flyback Design Review/Application Report 3
mA
V
W
V
P
I
INMIN
OUT
DA
85
2
2
90
74 . 0
5
2
2
~ =
|
|
|
|
.
|

\
|
=
t t
q
, bridge rectifier average diode current (I
DA
)

mW I V P
DA FDA DA
85 = = , estimate power dissipated in bridge rectifier diode (P
DA
)

Estimate remaining power budget based on bridge rectifier loss.

W P P P
DA BUDGET BUDGET
68 . 1 2 ~ =

Transformer Calculations (T1):

Transformer demagnetizing duty cycle (D
MAG
) is fixed to 42.5% based on the UCC28700 control law
methodology [1].

425 . 0 =
MAG
D

T
R
is the estimated period of the LC resonant frequency at the switch node.

us T
R
2 =

Calculate maximum duty cycle (D
MAX
):

47 . 0
2
2
105 425 . 0 1
2
1 = = =
s
kHz
T
f D D
R
MAX MAG MAX



Calculate transformer primary peak current (I
PPK
) based on a minimum flyback input voltage. This
calculation includes a factor of 0.6 to account for the reduction in flyback input voltage caused by the
ripple voltage across the input capacitors (C
A
and C
B
).

mA
V
W
D V
P
I
MAX INMIN
OUT
PPK
382
47 . 0 6 . 0 2 90 74 . 0
5 2
6 . 0 2
2
~


=


=
q


Selected primary magnetizing inductance (L
PM
) based on minimum flyback input voltage, transformer,
primary peak current, efficiency and maximum switching frequency (f
MAX
).

( )
uH
kHz mA
W
f I
P
L
MAX PPK
OUT
PM
896
105 376
74 . 0
5 2
2
2 2
~

=
q



SLUA653B
4 5W USB Flyback Design Review/Application Report
V V
QAON
2 = , estimated voltage drop across FET during conduction

V V
RCS
75 . 0 = , voltage drop across current sense resistor

V V
DG
6 . 0 = , estimated forward voltage drop across output diode

Calculate transformer turns ratio primary to secondary (a
1
) based on volt-second balance.
Note in the following equation L
SM
is secondary magnetizing inductance.

( )
( )
5 . 14
6 . 0 2
1
~
+

= = =
DG OUT MAG
RCS AON INMIN MAX
SM
PM
S
P
V V D
V V V D
L
L
N
N
a



V V
DDMIN
8 = , UCC28700 minimum VDD voltage before UVLO turnoff.

V V
DE
3 . 0 = , estimated auxiliary diode forward voltage drop

V V
INIT OUT
2
_
= , Minimum voltage on the output when adapter is connected to a device with a depleted
battery.


Calculate transformer auxiliary to secondary turns ratio (a
2
)

2 . 3
_
2
~
+
+
= =
DG INIT OUT
DE DDMIN
S
A
V V
V V
N
N
a


Transformer primary RMS current (I
PRMS
)

mA
D
I I
MAX
PPK PRMS
151
3
= =

Transformer secondary peak current RMS current (I
SPK
)

A
D V
P
I
MAG OUT
OUT
SPK
7 . 4
2
~

=




SLUA653B
5W USB Flyback Design Review/Application Report 5
Transformer secondary RMS current (I
SRMS
)

A
D
I I
MAG
SPK SRMS
8 . 1
3
~ = , transformer secondary RMS current

For this design we estimated the power dissipated by the UCC28700 (P
IC
) would be 50mW maximum.
Note this will vary in the design based on the FET that is being driven and the maximum frequency it is
being driven at.

mW P
IC
50 =


Calculate auxiliary winding peak current (I
APK
)

mA
D a V V
P
I
MAG DE OUT
IC
APK
13
) (
2
2
=
+

=

Calculate auxiliary winding RMS current (I
ARMS
)

mA
D
I I
MAG
APK ARMS
0 . 5
3
~ =

For this transformer we allow for 3% efficiency loss from the transformer (P
T1
)

mW P P
OUT T
150 03 . 0
1
= =

Recalculate remaining power budget

W P P P
T BUDGET BUDGET
53 . 1
1
~ =

A Wurth Electronik transformer was designed for this application, part number 750312723, which has
the following specifications:

a
1
= 15.33

a
2
= 3.83

uH L
PM
925 =

uH L
LK
16 = , primary leakage inductance


SLUA653B
6 5W USB Flyback Design Review/Application Report
Input Capacitor Selection (C
IN
= C
A
+ C
B
):

Calculate input capacitor charge time (t
CH
) based on 40% input capacitor ripple voltage.


ms
Hz
V
V V
t
INMIN
INMIN INMIN
CH
4 . 3
47 4
2
6 . 0 2 2
sin 1
1
=

|
|
.
|

\
|

=



Calculate flyback average primary current (I
PT1
) during input capacitor discharge.

mA
V
P
V
P
I
INMIN
OUT
INMIN
OUT
PT
72
2
6 . 0 2 2
1
=

+

=
q q


Calculate total input capacitance (C
IN
) based on minimum flyback input voltage and 40% ripple voltage
across the input capacitor.

ms
Hz
T
RL
11
47 2
1
~

= , longest period of the rectified line voltage

V V V
INMIN INRIPPLE
9 . 50 4 . 0 2 ~ = , input ripple to the flyback converter

( )
uF
V
t T I
C
INRIPPLE
CH RL PT
IN
10
1
~

=

uF
C
C C
IN
B A
5
2
= = =

Calculate input capacitor (C
A
) RMS current (I
C_ARMS
) based on 40% input capacitor ripple voltage.


mA
t
V C C
I
CH
INMIN B A
CINP
311
4 . 0 2 ) ( 2
~
+
= , peak input capacitor charge current (I
CINP
)


mA
I
T
t T I
T
t I
I
PT
RL
CH RL CINP
RL
CH CINP
RMS CA
82
2 3 2 3 2
2
1
2 2
_
~
|
.
|

\
|

|
|
.
|

\
|

+
|
|
.
|

\
|

=


SLUA653B
5W USB Flyback Design Review/Application Report 7

Estimate of capacitor C
B
s low frequency (1/T
RL
) RMS current (
LFRMS CB
I
_
)

RMS CA LFRMS CB
I I
_ _
=

Estimate of C
B
s high frequency RMS current (I
CB_HFRMS
)

mA
D
I
D
I I
MAX
PPK
MAX
PPK HFRMS CB
122
2 3
2
2
_
~
|
.
|

\
|

|
|
.
|

\
|
=

Estimate of C
B
s total RMS current (I
CB_RMS
)

( ) ( ) mA I I I
HFRMS CB LFRMS CB RMS CB
147
2
_
2
_ _
~ + =

For this design 4.7uF, 400V electrolytic capacitors, from Nichicon part number UVR2G4R7MPD were
chosen for the design.

uF C C
B A
7 . 4 = =

These capacitors had a measured ESR of 6 ohms at 105 kHz

ESR
CA
= ESR
CB
= 6

Recalculate remaining power budget based on power dissipation by the ESRs in the input capacitors.

( ) ( ) W ESR I ESR I P P
CB RMS CB CA RMS CA BUDGET BUDGET
36 . 1
2
_
2
_
~ =

Filter Inductor (L
A
):
Filter inductor (L
A
) is used for EMI filtering. In this design it is just a place holder and the design has
not been optimized for EMI. 470uH inductor from Bourns was chosen, part number RLB0608-471KL.
This inductor has a DCR of 6.5 ohms.

O = 5 . 6 DCR

Recalculate power budget based on DCR losses

( ) W DCR I P P
PRMS BUDGET BUDGET
212 . 1
2
~ =




SLUA653B
8 5W USB Flyback Design Review/Application Report
Fusible Resistor (R
L
):
To limit the inrush current during power and for safety a 10 ohm, 3W fusible resistor from Bourn, part
number PWR4522AS10R0JA was placed at the input of this design.

O =10
L
R

Recalculate power budget based on estimated R
L
losses

( ) W R I P P
L PRMS BUDGET BUDGET
984 . 0
2
~ =

Trickle Charge Resistor (R
T
):
To reduce no load power losses R
T
and to keep no load power to a minimum, three 5.11M are used in
series for R
T


O = O = M M R
T
33 . 15 3 11 . 5

( )
mW
R
V
P
T
INMAX
RT
2 . 9
2
2
~ = , Total trickle charge resistor power dissipation

Recalculate power budget

W P P P
RT BUDGET BUDGET
974 . 0 ~ =

VDD Capacitor Selection (C
DD
):
The C
DD
is selected with the following equation based on the desired startup time (dt
CDDS
) of the
UCC28700 controller and knowing the start current (I
START
), as well as, the UCC28700 device startup
threshold (V
VDD(on)
). For this design a 330nF capacitor was selected.


s dt
CDDS
1 =


uA I
START
5 . 1 =

V V
on VDD
21
) (
=


nF nF
V
dt I
R
V
C
on VDD
CDDS START
T
INMIN
DD
330 324
2
) (
~ =

|
|
.
|

\
|

=

Note after C
DD
has been charged up to the device turn on threshold (V
VDD(on)
), the UCC28700 will
initiate three small gate drive pulses (DRV) and start sensing current and voltage. (Please refer to figure
2) If a fault is detected such as an input under voltage or any other fault, the UCC28700 will terminate
SLUA653B
5W USB Flyback Design Review/Application Report 9
the gate drive pulses and discharge C
DD
to initiate an under voltage lockout. This capacitor will be
discharged with the run current of the UCC28700 (I
RUN
) intil the V
DD
turnoff (V
VDD(off)
) threshold is
reached. Note the C
DD
discharge time (t
CDDD
) from this forced soft start can be calculated knowing the
controller run current (I
RUN
) without out gate driver switching and the controllers VDD turnoff
threshold (V
VDD(off)
) and the following equations. If no fault is detected, the UCC28700 will continue
driving Q
A
and controlling the input and output currents [1] and a soft start will not be initiated.

mA I
RUN
1 . 2 =

V V
off VDD
8
) (
=
ms
I
R
V
V V
C dt
RUN
T
INMAX
off VDD on VDD
DD CDD
71
2
) ( ) (
=
|
|
.
|

\
|

=

V
DD
0V
DRV
V
VDD(on)
=21V
V
VDD(off)
=8V
3 Initial DRV Pulses After V
DD(ON)

Figure 2, VDD and DRV at Startup with Fault

Current Sense Resistor (R
CS
):
For this design 2.05 ohm resistor was selected based on a nominal maximum current sense signal of
0.75V.

ohm
I
V
R
PPK
CS
05 . 2 965 . 1
75 . 0
~ O = =

( ) W R I P
CS PRMS RCS
046 . 0
2
= = , nominal current sense resistor power dissipation

Recalculate power budget

W P P P
RCS BUDGET BUDGET
928 . 0 ~ =




SLUA653B
10 5W USB Flyback Design Review/Application Report
Select Output Diode (D
G
):

Calculate diode reverse voltage (V
RDG
)

V
a
V V V
INMAX OUT RDG
45 . 29
1
2
1
~ + =

Calculate peak output diode (I
DGPK
)

A I I
SPK DGPK
7 . 4 = =

For this design we selected a 3A, 40V schottky rectifier with a forward voltage drop (V
FDG
) of 0.31V.

V V
FDG
31 . 0 =

Estimated diode power loss (P
DG
)

~

=
OUT
FDG OUT
DG
V
V P
P 0.31W

Recalculate power budget

W P P P
DG BUDGET BUDGET
618 . 0 ~ =


Select Output Capacitors (C
OUT
):

Select output ESR based on 90% of the allowable output ripple voltage

O =

= m
A
mV
I
V
ESR
SPK
RIPPLE
COUT
19
7 . 4
9 . 0 100 9 . 0


For this design the output capacitor (C
OUT
) was selected to prevent V
OUT
from dropping below the
minimum output voltage during transients (V
OTRM
).

V V
OTRM
1 . 4 =
mF
V V
V
P
ms
C
OTRM OUT
OUT
OUT
OUT
1 . 1
2
2
=

>



SLUA653B
5W USB Flyback Design Review/Application Report 11
For this design two 560uF capacitors were used in parallel on the output, with an ESR of 13m each.

mF uF C
OUT
12 . 1 560 2 = =

O =
O
= m
m
ESR
COUT
5 . 6
2
13


Estimate total output capacitor RMS current (I
COUT_RMS
)

A
V
P
D I
I
OUT
OUT
MAG SPK
RMS COUT
46 . 1
3
2
2
_
~
|
|
.
|

\
|

(
(

=

Estimate total output capacitor loss (P
COUT
)

( ) mW ESR I P
COUT RMS COUT COUT
14
2
_
= =

Recalculate power budget

W P P P
COUT BUDGET BUDGET
604 . 0 ~ =

Select FET Q
A
:

For this design we had chosen a 600V rated MOSFET with the following characteristics:

ohm R
DSON
5 . 4 = , FET Q
A
on resistance

pF C
OSS
5 . 8 = , average FET drain to source capacitance

SLUA653B
12 5W USB Flyback Design Review/Application Report

Figure 3, Gate Charge vs V
gs


Estimate FET losses (P
QA
)

A I
DRIVE
35 . 0 = , maximum FET gate drive current

nC Q
g
9 = , gate charge just above the miller plateau

ns
I
Q t
DRIVE
g r
52
2
~ = , estimated FET V
ds
rise and fall time

Estimate FET power loss by driving the FETs gate (P
g
)

nC Q
g
12
1
= , Gate charge at 12V drive clamp

V V
g
12 =

mW f Q V P
MAX g g
15 12
1
= =

Calculate the average input voltage to the flyback at the maximum input voltage (V
INMAX
).

V V
V
V V
FDA
INRIPPLE
INMAX FLY
347 2
2
2 ~ =



SLUA653B
5W USB Flyback Design Review/Application Report 13
Estimate FET average switching loss (P
SW
)


( ) mW
f t I
a V V V P
MAX r PPK
VDG OUT FLY SW
269
2
1
~

+ =

Estimated FET Coss power dissipation (P
COSS
)

pF C
OSS
5 . 8 = , average FET drain to source capacitance

( ) mW f V
C
P
MAX FLY
OSS
COSS
54
2
2
~ =

Calculate power loss from Rdson (P
RDSON
)

W R I P
DSON PRMS RDSON
1 . 0 ) (
2
= =

Estimate total FET losses (P
QA
)

mW P P P P P
COSS g SW RDSON QA
441 ~ + + + =

Recalculate the power budget

mW P P P
QA BUDGET BUDGET
163 ~ =

Setup Zener Clamp to Protect FET Q
A
:

V V
Z
82 = , Zener Clamp Voltage (D
Z
)

V V
MAX ds
600
_
= , FET maximum drain to source voltage

V V V V
INMAX MAX ds CLAMP
2 . 165 2 9 . 0
_
~ = , Available Clamp Voltage to Protect FET Q
A


O ~

= 5 . 216
6 . 0
PPK
Z CLAMP
S
I
V V
R

Select a standard resistor for the design.

O = 215
S
R



SLUA653B
14 5W USB Flyback Design Review/Application Report

Estimate Zener Clamp/L
LK
power dissipation (P
LK
)

( )
mW
f I L
P
MAX PPK LPK
LLK
122
2
2
=

=

Recalculate power budget

mW P P P
LLK BUDGET BUDGET
40 ~ =

Select VS voltage divider (R
S1
, R
S2
):

uA I
run VSL
220
) (
= VS Line-sense run current

Note R
S1
so the converter will go into under voltage lockout when the input is below 80% of the
minimum specified input voltage.

O ~

= k
I
V
a
a
R
run VSL
INMIN
S
6 . 115
8 . 0 2
) (
1
2
1


Select a standard resistor for the design

O = k R
S
121
1


( )
O ~
+
= k
R
V a V V
V
R
S
DG OUT
S
7 . 27
4
4
1
2
2

Calculated R
S2
is a starting point and will need to be adjusted in circuit. To have a 5V regulated output
this resistor was adjusted to 30.1k

O = k R
S
1 . 30
2


Calculate VS divider power dissipation (P
VS
)

( ) ( )
( )
mW
R R
a V V D
P
S S
DG OUT MAX
VS
3 . 1
2 1
2
2
~
+
+
=
Select auxiliary diode (D
E
) for this design that had a forward voltage drop (V
DE
) of 0.6V.

V V
DE
6 . 0 =

SLUA653B
5W USB Flyback Design Review/Application Report 15
( ) V V a V V V
DE DG OUT DD
8 . 20
2
~ + = , UCC28700 supply voltage at V
DD

V
a
a
V V V
INMAX DD RDE
115 2
1
2
~ + = , maximum reverse voltage across V
DE


mA I
RUN
1 . 2 = , UCC28700 bias current when gate drive = 0V

mA
V
V I P
I
DD
VDD RUN g
DD
8 . 2 ~
+
= , Estimated UCC28700 VDD current.

Calculate D
E
power dissipation (P
DE
)

mW V I P
DE DD DE
7 . 1 ~ =

Recalculated power budget

mW P P P P
DE VS BUDGET BUDGET
037 ~ =

Preload Resistor Selection (R
Z
):
To keep the output voltage from climbing at no load a pre-load resistor is required. This is generally a
trial an error process. For this designs the preload resistor that kept the output regulated under no load
conditions was 3.01 k.

K R
Z
01 . 3 =

Calculate R
Z
power dissipation (P
RZ
)

( )
mW
R
V
P
Z
OUT
RZ
3 . 8
2
~ =

Recalculated power budget and there is 29 mW of margin left in the power budget to meet the efficiency
requirements of the design. Note in production designs, more margin might be required. Also note
these calculations are estimations and the final design may need to be adjusted to hit efficiency and
regulation requirements.

mW P P P
RZ BUDGET BUDGET
29 ~ =






SLUA653B
16 5W USB Flyback Design Review/Application Report

Internal Blanking
The UCC2870X controller regulates the output voltage by sensing the auxiliary (Aux) winding. This
removes the need for opto isolator feedback scheme reducing the cost of the design. However, this
voltage control feedback scheme is susceptible to leakage spikes at the switch node that occur in most
flyback converters. This signal is coupled through the turns ratio of the transformer (T1) and shows up
on the Aux winding during t
LK_RESET
, please refer to figure 4 for details.

To help insure the leakage spike on the Aux winding does not cause a control issues, the UCC2870X
blanks (t
B
) the Aux signal to the controller for 500 ns to 1.5 us depending on loading. Please see the
data sheet details [1]. Note the ringing on the auxiliary winding needs to be less than 100mV peak
to peak after t
B
. Snubbing circuitry on the secondary and/or auxiliary winding may be required to
reduce ringing.

Aux/
D
E
Cathode
R
CS
DRV
0V
t
B
0V
t
LK_RESET
VS Samples Aux Voltage for Control
QA on
QA off
Aux Ringing after t
B
< 100mV

Figure 4, Auxiliary Winding VS Blanking

To ensure the leakage spike does not cause control issues it needs to be dissipated before the Aux
blanking (t
B
) has terminated. The tank frequency (f
LC
) between the switch node capacitance (C
SWN
) and
the transformer leakage inductance (L
LK
) should be greater than 1MHz.
SWN LK
LC
C L
f

=
t 2
1


MHz
ns
f
LC
1
500 2
1
=

>



SLUA653B
5W USB Flyback Design Review/Application Report 17

Select line compensation resistor R
LC
:
Resistor R
LC
provides offset to the peak current comparator input (CS). R
LC
is adjusted to terminate the
gate drive signal (B) early to prevent primary current (A) from over shooting [1]. Please refer to figures
5 and 6 for details.


Figure 5, Peak Current Limit Comparator Figure 6, CS(A), QA
g
(B), VQA
DS
Signals

25 =
LC
K , Line Compensating Ratio [1]

Calculate R
LC
initial resistor setting based on QA
DS
rise and fall time (t
r
)

O ~

=

k
L
a t R R K
R
PM
r CS S LC
LC
29 . 5
1
1
, Starting Point for R
LC

In circuit adjust R
LC
so the maximum output current is (I
OUT
). For this design RLC was set to 4.64 k.

O = k R
LC
64 . 4

Estimate no load input power (P
NL
):

kHz f
MIN
1 = , Minimum operating frequency

uW f Q V P
MIN g g g
144 = = , gate drive power dissipation at f
MIN


uA I
WAIT
85 = , VDD input current at 1 kHz operating frequency [1]

SLUA653B
18 5W USB Flyback Design Review/Application Report
mW V I P P
DD WAIT g VDD
9 . 1 ~ + = , Estimated UCC28700 power dissipation at f
MIN

Estimate switching losses (P
SWFM
) at high line at f
MIN

( ) uW
f t
I
a V V V P
MIN r
PPK
VDG OUT FLY SWFM
945
2
3
1 ~

=


( ) mW f V
C
P
MIN FLY
OSS
COSS
5 . 0
2
2
~ = , estimated C
OSS
losses at f
MIN



uW
f
I
L
P
MIN
PPK
LPK
LLK
129
2
3
2
~

|
.
|

\
|

= , estimate of leakage power dissipation at no load

The estimated no load input power (P
NL
) is roughly 22 mW. In the actual 5W design the no load input
power was roughly 20 mW at 230V RMS input voltage.

mW P
RZ
3 . 8 =

mW P
RT
2 . 9 =

mW P P P P P P P
LLK RT RZ COSS SWFM VDD NL
22 ~ + + + + + =

5W EVM Schematic:

SLUA653B
5W USB Flyback Design Review/Application Report 19
Figure 7, Schematic



Efficiency:

Efficiency
64%
66%
68%
70%
72%
74%
76%
78%
25% 50% 75% 100%
Output Power
%

E
f
f
i
c
i
e
n
c
y
Efficiency @ 115V RMS
Efficiency @ 230V RMS

Figure 8, Efficiency


Load Transient at 115V RMS
CH1 = I
OUT
, CH4 = V
OUT
with a 5V offset

Figure 9, 0.1 to 0.6A load step Figure 10, 0.6 to 0.1A load step
SLUA653B
20 5W USB Flyback Design Review/Application Report



Load Transient at 230V RMS
a. CH1 = I
OUT
, CH4 = V
OUT
with a 5V offset

Figure 11, 0.1 to 0.6A load step Figure 12, 0.6 to 0.1A load step


REFERENCES
[1] UCC28700/1/2/3 Data Sheet, Constant-Voltage, Constant-Current Controller with Primary Side
Regulation, SLUSB41, July 2012, http://www.ti.com/lit/gpn/ucc28700
[2]Using the UCC28700EVM-068, UCC28700EVM-068 5W USB Adapter, SLUU968, July 2012,
http://www.ti.com/litv/pdf/sluu968
[3] UCC28700 MathCAD design tool, http://www.ti.com/litv/zip/sluc381









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