Ipx Pu

FPGA/PLD IP
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T H E I N T E L L I G E N T A P P R O A C H T O
TM
I N T E L L E C T U A L
P R O P E R T Y
Inventra IPX
LeonardoSpectrum Altera Release (PC / UNIX edition)
User Guide
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12/01 PU-69501.002-FC 2001 Mentor Graphics Corporation All Rights Reserved
INVENTRA IPX USER GUIDE
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Confidential. May be photocopied by licensed customers of Mentor Graphics for internal business purposes only. The product(s) described in this document are trade secret and proprietary products of Mentor Graphics Corporation or its licensors and are subject to license terms. No part of this document may be photocopied, reproduced or translated, disclosed or otherwise provided to third parties, without the prior written consent of Mentor Graphics. The document is for informational and instructional purposes. Mentor Graphics reserves the right to make changes in specifications and other information contained in this publication without prior notice, and the reader should, in all cases, consult Mentor Graphics to determine whether any changes have been made. The terms and conditions governing the sale and licensing of Mentor Graphics products are set forth in the written contracts between Mentor Graphics and its customers. No representation or other affirmation of fact contained in this publication shall be deemed to be a warranty or give rise to any liability of Mentor Graphics whatsoever. MENTOR GRAPHICS MAKES NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. MENTOR GRAPHICS SHALL NOT BE LIABLE FOR ANY INCIDENTAL, INDIRECT, SPECIAL, OR CONSEQUENTIAL DAMAGES WHATSOEVER (INCLUDING BUT NOT LIMITED TO LOST PROFITS) ARISING OUT OF OR RELATED TO THIS PUBLICATION OR THE INFORMATION CONTAINED IN IT, EVEN IF MENTOR GRAPHICS CORPORATION HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. RESTRICTED RIGHTS LEGEND Use, duplication, or disclosure by the Government is subject to restrictions as set forth in the subdivision (c)(1)(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227-7013. A complete list of trademark names appears in a separate Trademark Information document. Mentor Graphics Corporation 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070. This is an unpublished work of Mentor Graphics Corporation.
For Pre-Sales Support on this product (Evaluation License):

Please email ipfpga_support@mentor.com
For Post-Sales Support on this product (Annual Subscription License):

Contact the Customer Support Service through the SupportNet web site at http://www.mentor.com/supportnet (First time visitors need to register.) Email support_net@mentor.com (Requires prior registration via the above SupportNet web site.)
Additional information is provided in Chapter 11.
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TABLE OF CONTENTS
1. 2.
LeonardoSpectrum Altera Release
INTRODUCTION.............................................................................................6 THE LEONARDOSPECTRUM ALTERA RELEASE.........................7 2.1. The Tools Required .................................................................................7 2.2. Deliverables ...............................................................................................7 2.3. Product Flow.............................................................................................7
3.
INSTALLATION AND LICENSING..........................................................8 3.1. Licensing Inventra IPX ...........................................................................8 3.1.1. 3.1.2. Obtaining an Evaluation License ...........................................8 Obtaining an Annual Subscription License ..........................8
3.2. Installing Inventra IPX from a CD .......................................................8 3.3. Installing Inventra IPX from the Web .................................................9 3.4. Installing Licenses...................................................................................10 4. THE INSTALLED FILESET........................................................................11 4.1. Structure ...................................................................................................11 4.2. Design Conventions...............................................................................11 4.2.1. 4.2.2. 4.2.3. Compatibility............................................................................11 Module Names.........................................................................12 Signal Names............................................................................12
4.3. Product Specification.............................................................................12 5. RTL-LEVEL SIMULATION.........................................................................13 5.1. The Files Provided .................................................................................13 5.2. Running the Simulations .......................................................................14 5.2.1. 5.2.2. 5.2.3. 6. Running the Simulation from within ModelSim................14 Running the Simulation from the DOS Command Line.14 Running the Simulation from the UNIX Command Line14
SYNTHESIS ......................................................................................................15 6.1. The Files Provided .................................................................................15 6.2. Setting the Required Device .................................................................15 6.3. Synthesis Constraints .............................................................................16 6.4. Running the Synthesis............................................................................16 6.4.1. 6.4.2. 6.4.3. Running the Synthesis from within LeonardoSpectrum..16 Synthesizing the RTL from the DOS Command Line.....18 Synthesizing the RTL from the UNIX Command Line: .18
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7. PERFORMING PLACE & ROUTE ...........................................................19 7.1. The Files Provided .................................................................................19 7.2. Setting the Required Device .................................................................19 7.3. Carrying out Place & Route..................................................................19 7.3.1. 7.3.2. 7.3.3. 8. Running Place & Route from within Quartus II...............20 Running Place & Route from the DOS Command Line.20 Running Place&Route using Quartus from the UNIX Command Line:.......................................................................20
GATE-LEVEL SIMULATION ....................................................................21 8.1. The Files Provided .................................................................................21 8.2. Back-Annotation of Timing Information ..........................................22 8.3. Running the Simulations .......................................................................22 8.3.1. 8.3.2. 8.3.3. Compiling and Running within ModelSim .........................23 Compiling and Running from the DOS Command Line 23 Compiling and Running from the UNIX Command Line: ....................................................................................................23
8.4. Comparing the Gate-Level Simulation against the RTL-Level Simulation ................................................................................................23 9. IMPLEMENTATION IN A SYSTEM DESIGN.....................................24 9.1. Stage 1: System Specification................................................................24 9.2. Stage 2: Design Capture ........................................................................24 9.3. Stage 3: System Verification..................................................................25 9.4. Stage 4: Synthesis....................................................................................25 9.5. Stage 5: Place & Route...........................................................................25 9.6. Stage 6: Gate-level Verification............................................................25 10. HELP...................................................................................................................26 10.1. Simulation Problems ..............................................................................26 10.2. Synthesis Problems.................................................................................27 10.3. Place & Route Problems .......................................................................28 10.4. Queries about the Cores........................................................................29 11. SUPPORT...........................................................................................................30 11.1. Pre-Sales Support....................................................................................30 11.2. Post-Sales Support..................................................................................30 11.2.1. Get Started Support..............................................................30 11.2.2. Core Question Support........................................................30 11.2.3. Post-Sales Support Contacts .................................................30
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12. REVISION HISTORY....................................................................................31 12.1. Issue 1.......................................................................................................31 12.2. Issue 2.......................................................................................................31
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1. INTRODUCTION
Inventra IPX is a suite of proven Inventra IP cores for a wide variety of application areas such as computing, consumer and communication, packaged for evaluation and for implementation in FPGAs and PLDs. It takes advantage of the integration of some commonly-used FPGA and PLD vendor flows with Mentor Graphics FPGA/PLD design tools to provide a collection of essential building blocks for accelerating the creation of complex FPGA or PLD-based system designs. The set of cores with which this user guide is supplied are packaged for use either on a PC or under UNIX with Mentor Graphics LeonardoSpectrum and programmable logic devices such as those in the Altera APEX II, APEX 20K and FLEX 10K families that are supported by the Altera encrypted IP flow. The cores of the Inventra IPX collection include: M1284H: IEEE 1284 Host Parallel Port M16550A: UART with FIFO M16x50: Enhanced UART with FIFO and IrDA support M8051: 8-Bit Microcontroller M82365SL: PC Host interface M8237A: 4-Channel DMA Controller M8255: Parallel Peripheral Interface M8490: 5380-compatible SCSI Interface MI2C: I2C Bus Interface MPCMCIA1: PC Card interface
(A full list of the cores provided may be found in the Release Note supplied in the docs directory and in the top-level readme of the installed fileset.) The cores are supplied as encrypted RTL. The advantage of offering an encrypted IP flow is that it allows designers to evaluate whether a core meets their requirements and to determine the performance and footprint of a core optimized to their chosen target technology without first having to acquire and learn the core. The Inventra IPX database also includes compiled simulation models and a range of scripts for simulating, synthesizing and carrying out place & route using the tools specified for the particular Inventra IPX package (see below). These scripts provide the user with a push-button route from encrypted RTL through to place & route. The Inventra IPX cores are delivered either on a CD or by download from the web. This user guide describes how to install the IPX cores on your system, simulate them, synthesize them and carry out place & route using the tools for which the cores have been packaged. Information about the cores themselves can be obtained by visiting the Inventra web site at http://www.mentor.com/inventra and from the core specification supplied alongside each core as part of the Inventra IPX database. Please Note: An Evaluation license to Inventra IPX will allow you to generate performance information but an Annual Subscription license to Inventra IPX is required to generate either a gate-level netlist or an appropriate programming file. For information on how to obtain the required license, please either email your sales representative at ipx@hdlsolutions or visit the Inventra IPX web site at http://www.mentor.com/inventra/ipx.
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2. THE LEONARDOSPECTRUM ALTERA RELEASE

Inventra IPX is supplied packaged for use with particular Mentor Graphics FPGA/PLD design tools and particular FPGA/PLD device families. The release of Inventra IPX for which this user guide is supplied, the LeonardoSpectrum Altera Release, leverages the integration of the Altera encrypted IP flow with Mentor Graphics LeonardoSpectrum synthesis tool to provide cores for implementation on programmable logic devices that are supported by the Altera encrypted IP flow. These include devices from the Altera APEX II, APEX 20K and FLEX 10K families.
2.1. THE TOOLS REQUIRED
To use the cores from this Inventra IPX collection in the Altera flow, you need: Mentor Graphics Exemplars LeonardoSpectrum Synthesis tool (Version 2001.1b (any level) or higher) Mentor Graphics Model Technologys ModelSim Simulator from (Version 5.5c or higher) Alteras Quartus II Place & Route software (Version 1.1 or higher) Either a PC or a UNIX workstation on which the above applications are installed.
2.2. DELIVERABLES
Inventra IPX is shipped with the following deliverables: 1. 2. 3. 4. 5. Encrypted RTL for each core ModelSim compiled models (testbenches and core) for each of these cores Simulation, Synthesis and Place & Route scripts for use with the tools specified above DOS scripts and UNIX scripts for running these operations in command line mode Core Specifications and Readme files
2.3. PRODUCT FLOW
The flow used to generate a netlist for any of the cores from the LeonardoSpectrum Altera Release comprises the following steps: 1. 2. 3. 4. 5. Installing the Inventra IPX database and the associated license(s). See Chapter 3. Optionally running the supplied RTL simulation model as described in Chapter 5. Synthesizing the encrypted RTL to the required Altera technology using LeonardoSpectrum in its Quick Setup mode. See Chapter 6. (Note: The EDIF netlist produced will be encrypted.) Compiling the EDIF within Quartus II to perform place and route, and generating either a Verilog (*.vo) or a VHDL (*.vho) gate-level netlist. See Chapter 7. Simulating the gate-level netlist. See Chapter 8. (Note: This part of the process is only possible with a valid Annual Subscription license to Inventra IPX. With an Evaluation license, no netlist is produced.)
GUI and command line scripts are provided for executing most of the above steps. Please note that the command line scripts assume that the ModelSim, LeonardoSpectrum and Quartus II executables are available on the system path. If any of these tools is not available on the path, either add it to the path or edit the supplied .bat/.scr file to reflect the absolute path to the executable. The scripts also assume that the QUARTUS_ROOTDIR environment variable has been set to point to the Quartus II root directory.
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3. INSTALLATION AND LICENSING

The Inventra IPX cores are delivered either on a CD or by download from the web. The process of installing Inventra IPX has two parts to it installing the IPX cores on the computer or workstation on which you intend to use the cores and installing the license files. Instructions are given below. The files of the current release are available for installation either on a PC under Windows or under UNIX. Please note that you will need around 400M of disk space on the drive or partition on which you install this release of Inventra IPX. Separate instructions are given for installing Inventra IPX from a CD and for installing Inventra IPX from the web.
3.1. LICENSING INVENTRA IPX
Use of the Inventra IPX cores requires at least a valid Evaluation license. Such a license will allow you (for a period of one year only) to simulate and synthesize any of the Inventra IPX cores and gather performance and area data on your chosen target device from a test place and route. It will even allow you to optimize the constraints applied to your chosen target device. What this license will not allow is the generation of either a gate-level netlist or a bitstream file for use in programming the chosen target device: for that you need an Annual Subscription license to Inventra IPX. This license (which can be renewed) will allow you to both explore all the cores in the Inventra IPX collection as described above and implement them for devices supported by the Altera encrypted IP flow for a period of one year.
3.1.1. O B TAINING AN EVALUATION LICENSE
Anyone downloading Inventra IPX from the web should be given an Evaluation license key to copy. Purchasers of a copy of LeonardoSpectrum who are offered Inventra IPX as a product plug-in will also be given an Evaluation license key, typically supplied via the web. (Instructions on obtaining the license key will be supplied alongside the Inventra IPX CD.) This license will allow you to explore the cores offered as described above for one year only.
3.1.2. O B TAINING AN ANNUAL SUBSCRIPTION LICENSE
An Evaluation license will allow you to generate performance information but an Annual Subscription license to Inventra IPX is required to generate either a gate-level netlist or a bitstream file for use in programming the chosen target device. For information on how to obtain the required license, please either email your sales representative at ipx@hdlsolutions or visit the Inventra IPX web site at http://www.mentor.com/inventra/ipx. Anyone who purchases an Annual Subscription license should receive their license key in an email message within two working days of the Purchase Order being received.
3.2. INSTALLING INVENTRA IPX FROM A CD
Inventra IPX is supplied on a CD when an Annual Subscription license to Inventra IPX is purchased from Mentor Graphics. It may also be supplied on a CD to customers who, for example, purchase a copy of LeonardoSpectrum. The main deliverable on the CD are application files which may be used to install the cores of the Inventra IPX collection, together with a range of general documents concerning Inventra IPX (including a copy of this User Guide). The .exe file is for installing Inventra IPX under Windows on a PC. The names of the other files (ipx_vx_xxx.ss6 etc.) reflect the platform on which each file is intended to be used.
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To install the Inventra IPX collection under Windows on a PC: 1. 2. 3. Insert the CD in your PCs CD-ROM drive. Run the supplied ipx_vx_xxx.exe application. Work through the screens of the InstallShield Wizard that is loaded. Note: When the License Agreement is displayed, be sure to read and agree to this. When the last screen is displayed, click Finish. 4. 2. 3. 1.
To install the Inventra IPX collection under UNIX: Insert the CD in a CD-ROM drive mounted on your workstation. Create the directory in which you want to install Inventra IPX (the Destination for the install). Run the appropriate ipx_vx_xxx.<system> application from the ones supplied on the CD. Read the License Agreement that is now displayed, click the box next to the I agree... statement, then click Next>. When the dialog appears, enter your Destination directory in the Selection box at the bottom of the display e.g. by navigating to it through the list of directories shown in the upper part of the display. Click OK.
4.
5.
6.
In either case, the executable will then place a set of files with the following outline directory structure on your disk:
ipx_v x_ xxx
m1284h
m16550a
m16x50
. . .
m8490
mi2c
mpcmcia1
docs
verilog
vhdl
docs
Within the top level Inventra IPX directory will be a set of core directories, one for each core in the Inventra IPX collection, plus a docs directory. The docs directory contains general documents concerning Inventra IPX including a copy of this user guide. (Each core has the same directory structure. Details of this structure are given in Chapter 4.) Before you can use any of the supplied cores, you also need to install at least a valid Evaluation license for Inventra IPX as described in Section 3.4 below.
3.3. INSTALLING INVENTRA IPX FROM THE WEB
A copy of Inventra IPX may also be downloaded from the Inventra IPX web site at http://www.mentor.com/inventra/ipx. To install a copy of Inventra IPX from the web: 1. 2. 3. 4. Use your standard Web Browser to go to the Inventra IPX web site at http://www.mentor.com/inventra/ipx. Read the information given at that site, then click on Product Download. Fill in the form that is displayed. Note: Information requested in red must be filled in. Copy the License Key from the next page to a text file on your machine. This license key will be a single line of text starting with the word FEATURE (possibly split over two lines, with the first line terminated with a backslash).
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To install the Inventra IPX collection under UNIX: 6. Take the option to download the appropriate version of Inventra IPX. Read and agree to the License Agreement then, when asked, specify where you want the copy of Inventra IPX to be placed on your system. This places an ipx_vx_xxx.<system> file in the selected directory. Create the directory in which you want to install Inventra IPX (the Destination for the install). Run the ipx_vx_xxx.<system> application. When the License Agreement is displayed, click the box next to the I agree... statement, then click Next>.
To install the Inventra IPX collection under Windows on a PC: 5. Take the option to download the PC version of Inventra IPX. Read and agree to the License Agreement then, when asked, specify where you want the copy of Inventra IPX to be placed on your PC. This places an ipx_vx_xxx.exe file in the selected directory. Run this .exe application file. Work through the screens of the InstallShield Wizard that is loaded. When the License Agreement is displayed, agree to this. When the last screen is displayed, click Finish.
6. 7.
7. 8. 9.
8.
10. When the dialog appears, enter your Destination directory in the Selection box at the bottom of the display e.g. by navigating to it through the list of directories shown in the upper part of the display. 11. Click OK. The executable will then place a set of files on your disk with the outline directory structure shown on the previous page. Within the top level IPX directory will be a set of core directories, one for each core in the Inventra IPX collection, plus a docs directory. The docs directory contains general documents concerning Inventra IPX including a copy of this user guide. (Each core has the same directory structure. Details of this structure are given in Chapter 4.) Before you can use any of the supplied cores, you also need to install at least a valid Evaluation license for Inventra IPX as described in Section 3.4 below.
3.4. INSTALLING LICENSES
Anyone downloading Inventra IPX from the web should have been offered a license key to copy (see Section 3.3). This gives the user an Evaluation license to Inventra IPX. Purchasers of a copy of LeonardoSpectrum who are offered Inventra IPX as a product plug-in should also have been given an Evaluation license key, typically supplied via the web. (Instructions on obtaining the license key will have been supplied alongside the Inventra IPX CD.) Anyone who has purchased an Annual Subscription license should have received their license key in an email message within two working days of the Purchase Order being received. To be accessed by the software, the Inventra IPX license needs to be appended to the license file pointed to by the LM_LICENSE_FILE environment variable. If this environment variable points to more than one license file, then the Inventra IPX license needs to be appended to the same license file as the license for Altera Quartus II. Delete or comment out any earlier entries for the Inventra IPX feature in this license file. The Inventra IPX license should then be found when LeonardoSpectrum and Quartus II are loaded, allowing access to the Inventra IPX cores. Note: If you use a license server or you are unable to identify the correct license file to which to add the Inventra IPX license, consult your system administrator.
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4. THE INSTALLED FILESET
This chapter outlines the fileset supplied in support of each Inventra IPX core. Not all of the files supplied will be relevant to your design flow. You should use this chapter as a reference to determine where the files required for particular actions are to be found.
4.1. STRUCTURE
The files for each IPX core are provided in a directory named after the core, and are principally divided into a Verilog set and a VHDL set as shown in the diagram below.
IPX_core
verilog
vhdl
docs
rtl_encrypted
rtl_sim
synth
gate_sim
template
rtl_encrypted
rtl_sim
synth
gate_sim
template
work
quartus
work
work
quartus
work
The rtl_encrypted directories contain the encrypted source code. The rtl_sim directories each contain a ModelSim compiled library of the testbench and the core, compiled into a work library. The rtl_sim directories also contain scripts and associated files for simulating the IPX core using ModelSim. The gate_sim directories each contain a ModelSim compiled library of the testbench, compiled into a work library. The gate_sim directories also contain scripts and associated files for simulating the gate-level netlist using ModelSim. The synth directories contain scripts for synthesizing the core using LeonardoSpectrum, initially set up with the Altera APEX EP20K400EFC672 as the target device. The synth/quartus directories contain scripts for running place and route using Quartus II (again, initially set up with same APEX device as the target device). The template directories contain template and symbol files for the IPX core. The docs directory contains documentation specific to the core including its Product Specification.
Version-specific information about the core and details of the files supplied are given in the <IPX_core>.readme file in the top-level <IPX_core> directory and in other readmes located at different points in the directory structure.
4.2. DESIGN CONVENTIONS
This section describes some overall features of the Inventra IPX cores.
4.2.1. COMPATIBILITY
The majority of Inventra IPX cores have, as a first priority, been designed to be compatible with the reference devices on which they are modeled. This means that they are binary compatible at the register-bit function level and that, in the case of
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Microcontroller designs, they are where possible clock-for-clock compatible with the original part. In the case of Peripheral Controllers, the exact timings of the CPU I/O channel interface may differ from the reference device, but the difference should not affect system behavior.
4.2.2. MODULE NAMES
The top-level module is named after the design. Thus the top-level module of the Verilog RTL code is provided as the file <IPX_core>.v , while the top-level module of the VHDL RTL code is provided as the file <IPX_core>.vhd. The name for each module within the core is unique and is (generally) of the form: m3snnnaa where nnn is the module number and aa is a unique alpha code for the design. For example, the M16550A has the alpha code an, and so its modules have names of the form m3snnnan. The fact that each module has a unique name means that different Inventra cores can be used together (and together with cores from other sources) without there being any confusion as to which module is being selected. These module names are not intended to convey any meaning, but they can be cross-referenced to a functional description via the hierarchy diagram shown in the cores Product Specification.
4.2.3. SIGNAL NAMES
The signal names used in the cores start with alpha characters and only contain alphanumeric tokens. Signals that are active low are usually prefixed with N.
4.3. PRODUCT SPECIFICATION
The Product Specification supplied for each of the Inventra IPX cores has a standard format that is intended to make it straightforward to find the information you require. It is supplied in Adobe Acrobat format as the file <IPX_core>_ps.pdf in the cores docs directory and it typically contains the following information: Design Features The main features of the soft core are highlighted as bullet points. These points are expanded with a short discussion and illustrated with a block diagram to enable you to quickly establish whether the function is suitable for your requirements. Design Hierarchy The hierarchy of the design is described using a hierarchical tree diagram. The top-level module of the design is shown as the left-most box with the lower level blocks fanning out to the right. Each box in the diagram contains the module name and a brief description of the modules function is given. Signal Description The inputs and outputs to the core are illustrated in a top-level diagram. Inputs to the core are typically shown on the left-hand side with the outputs shown on the right-hand side. Buses are denoted by thicker lines. This is followed by a table describing the function of the signals. This lists the names of the signals, whether they are inputs or outputs, and gives a brief description of their purpose. Detailed Information Detailed information about the function of the device, including a description of any software interface at the register-bit level, is given in the main body of the Product Specification. Special Features The detailed functional description is followed by a section on special features, giving information on enhancements to, or differences from, the reference device. Timing Diagrams Timing diagrams are included in a separate section towards the end of the Product Specification but it is important to note that these diagrams do not give specific timing information since it is not possible to predict the timing of a design in any particular target technology. What the diagrams show are the relationships between signals in terms of where a transition on one signal causes another signal to change.
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5. RTL-LEVEL SIMULATION
Inventra IPX is shipped with ModelSim compiled models of each core and one or more testbenches, compiled into work libraries within the <IPX_core>/<language>/rtl_sim directory. For example, the Verilog version of the MI2C core and its testbench are supplied compiled into a ModelSim library named work within the mi2c/verilog/rtl_sim directory. GUI and command line scripts for running the supplied model under ModelSim are provided alongside the work library. The purpose of supplying this compiled model is to allow users to examine particular aspects of the cores behavior prior to synthesis, especially in comparison with its behavior after place and route. This chapter outlines the steps that may be taken to verify the supplied designs. For specific information on verifying a particular core, please refer to the rtl_sim.readme file provided for the core. Note: This process requires the use of Version 5.5c or higher of the ModelSim simulator. You should also note that the testbenches supplied for a particular core do not test every conceivable mode of operation of the design. It is up to the user to ensure that the mode(s) of operation required by their system configuration are tested.
5.1. THE FILES PROVIDED
The files and libraries supplied for RTL simulation are provided within the <IPX_core>/<language>/rtl_sim directory. The principal files and libraries for each core are: work <IPX_core> xxx_tb.do <IPX_core> xxx_tb.bat <IPX_core> xxx_tb.scr <IPX_core> xxx_tb.ref * <IPX_core> xxx_tb_diff.bat * <IPX_core> xxx_tb_diff.scr * rtl_sim.readme ModelSim simulation library comprising compiled versions of the RTL core and the testbenches. One or more GUI script for running the simulations interactively under ModelSim. One or more DOS command line script for running the simulations under ModelSim in batch mode. One or more UNIX command line script for running the simulations under ModelSim in batch mode. One or more reference listing file. DOS command line script(s) that compare the generated listing against the provided reference file. UNIX command line script(s) that compare the generated listing against the provided reference file. Readme file noting core-specific information about simulating the core and about the files etc. delivered.
(Any other files included in this directory will be used by the testbenches during simulation.) For core-specific details, see the rtl_sim . re adm e file included in the rtl_s im directory.
Note: Reference listing files and associated _diff.bat/.scr files are not included with self-checking testbenches. You should also note that the reference files for some cores have a .lst, .lis or .vec file extension.
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5.2. RUNNING THE SIMULATIONS
Scripts are provided either for running the simulations interactively from within ModelSim or for running these in batch mode either under DOS or under UNIX. The scripts supplied for running the simulations from within ModelSim are provided as files called <IPX_core> xxx _tb.do . The scripts supplied for running the simulations in batch mode are provided as <IPX_core> xxx _tb.bat (for DOS) and <IPX_core> xxx _tb.scr (for UNIX). The <IPX_core> xxx _tb.bat and <IPX_core> xxx _tb.scr scripts both invoke ModelSim to run the corresponding <IPX_core> xxx _tb.do script. In most cases, both a transcript file and a listing file are produced. Where appropriate, command line scripts (<IPX_core> xxx _tb_diff.bat and <IPX_core> xxx _tb_diff.scr ) are also provided that compare the listing file that is generated against the good reference supplied as the file <IPX_core> xxx _tb.ref (or equivalent name: see previous page) There should not be any differences but any that do occur will be recorded in a sim_diff.txt text file. When run interactively from within ModelSim, the script also causes a waveform display to be generated showing the behavior of the cores input and output signals during the test. The steps used to run each simulation are given below. One of the first actions carried out by the scripts is to refresh the supplied work library for the version of ModelSim that you use.
5.2.1. RUNNING THE SIMULATION FROM WITHIN ModelSim
Note: The following just gives an outline of the steps used. For further information, refer to the ModelSim documentation. 1. Invoke ModelSim.
Within ModelSim, perform the following tasks: 2. 3. Navigate to the appropriate <IPX_core>/<language>/rtl_sim directory either by using the File Change Directory menu option or by issuing a cd command. Execute the selected .do macro either by using the Macro Execute Macro menu option or by using a do command such as do mi2c_tb.do
Note: In some cases, the simulation listing file is not fully written until the simulation has been terminated (using quit f ).
5.2.2. RUNNING THE SIMULATION FROM THE DOS COMMAND LINE
1. 2.
Use a cd command to navigate to the appropriate <IPX_core>\<language>\rtl_sim directory. Execute the required <IPX_core> xxx _tb.bat script.
5.2.3. RUNNING THE SIMULATION FROM THE UNIX COMMAND LINE
1. 2.
Use a cd command to navigate to the appropriate <IPX_core>/<language>/rtl_sim directory. Execute the corresponding .scr script.
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6. SYNTHESIS
GUI and command line scripts are provided for synthesizing each of the supplied cores using LeonardoSpectrum. These scripts take the encrypted RTL modules supplied for the core, compile them and process them to produce an EDIF netlist for use with the Altera Place & Route software (as described in Chapter 7). This chapter outlines the steps used to synthesize the IPX cores using the supplied files. For specific information on synthesizing a particular core, please refer to the synth.readme file provided for the core. Note: This process requires the use of Version 2001.1b (any level) or higher of the LeonardoSpectrum Synthesis tool.
The files supplied for synthesizing an IPX core are provided within the appropriate <IPX_core>/<language>/synth directory. The principal files used are: spectrum.tcl setup.tcl do_ip.tcl spectrum.bat spectrum.scr synth.readme Tcl script for synthesizing the core using LeonardoSpectrum. Can be run from within LeonardoSpectrum. Setup file used by spectrum.tcl. Sets the target part and the timing constraints. Synthesis script used by spectrum.tcl. Sets the basic parameters for the synthesis and controls the order in which the modules are compiled. DOS command line script for running the synthesis in batch mode. Calls spectrum.tcl. UNIX command line script for running the synthesis in batch mode. Calls spectrum.tcl. Readme file noting core-specific information about synthesizing the core and about the files delivered.
For core-specific details, see the synth.re adm e file included in the synth directory.
6.2. SETTING THE REQUIRED DEVICE
The files of the Inventra IPX LeonardoSpectrum Altera Release may be used to generate netlists for any programmable logic device that is supported by the Altera encrypted IP flow, such as the devices in the Altera APEX II, APEX 20K and FLEX 10K families. The scripts supplied in the synth directory are set up to synthesize each core for implementation on an APEX EP20K400EFC672 device. For this, they call on LeonardoSpectrums APEX20E technology library. The details of the device used are recorded in the setup.tcl file, alongside timing parameters suitable for implementing the core on the selected device. The use of the APEX20E technology library is recorded both in the setup.tcl and the do_ip.tcl files. One way of synthesizing the core for a different device is therefore by editing the appropriate details in the setup.tcl and do_ip.tcl files. However, a better way to do this when you are in the process of establishing which might be the best device to use is to first run the supplied scripts as described in Section 6.4.1, then use the options available within LeonardoSpectrum to select different devices and different clock speeds, and click the Run IP Flow button offered within LeonardoSpectrum to rerun the synthesis. This provides an efficient way of checking out the core on a number of different devices. The time to transfer these details to the setup.tcl and do_ip.tcl files is when you have decided which device and speed to use.
Note: Other aspects of the synthesis that may be modified either within LeonardoSpectrum or by editing the setup.tcl and
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do_ip.tcl files include the effort setting and the location of the output file. However, you should note that the compilation order that is set in the do_ip.tcl file is important and should not be modified. You should also note that any changes you make to the device settings and the location of the output file will also need to be applied in the quartus.tcl script that is used to run the place & route part of the operation.
6.3. SYNTHESIS CONSTRAINTS
The setup.tcl file contains the basic constraints on the register-to-register, input-to-register, register-to-output, and input-tooutput timings appropriate to running the core at the selected clock speed. Where appropriate, constraints appropriate to the environment in which you are planning to use the core may be applied either by adding these to the setup.tcl file, using the Advanced features of LeonardoSpectrum or setting up a suitable .ctr file. Further information on this may be found in the documentation for LeonardoSpectrum.
6.4. RUNNING THE SYNTHESIS
Scripts are provided for either running the synthesis from within LeonardoSpectrum or for running it in batch mode either under DOS or under UNIX. The script supplied for running the synthesis from within LeonardoSpectrum is provided as the file spectrum.tcl. The scripts supplied for running the synthesis in batch mode are spectrum.bat (for DOS) and spectrum.scr (for UNIX). The spectrum.bat and spectrum.scr scripts both invoke LeonardoSpectrum to run the spectrum.tcl script. The spectrum.tcl script: invokes the setup.tcl script to set the device parameters and the timing constraints to be applied invokes the do_ip.tcl script to set other aspects of the synthesis such as the effort level applied and to compile the encrypted RTL modules in the appropriate order generates an EDIF netlist ( default name <IPX_core>.edf ).
Please note that the EDIF file produced will be encrypted. The steps used to run the synthesis are given below. A range of information about the synthesized core is generated as the core is synthesized. However, this information is largely superceded by that available after place & route. Note: The scripts are supplied set up to synthesize the core for implementation on one particular member of the Altera APEX family. To synthesize the core for implementation on a different device, the user should modify the setup.tcl and do_ip.tcl files as described in Section 6.2 above. Core-specific information may be given in the synth. re adm e file included in the synth directory.
6.4.1. RUNNING THE SYNTHESIS FROM WITHIN LeonardoSpectrum
Note: The following just gives an outline of the steps used. For further information, refer to the LeonardoSpectrum documentation. 1. 2. Invoke LeonardoSpectrum. If necessary, select Quick Setup mode by clicking on the Q button.
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This is displays the GUI shown in Figure 1 below.
Figure 1: Leonardo Spectrum Quick Setup GUI
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Within this GUI: 3. Run the script spectrum.tcl by selecting File Run Script and navigating to the <IPX_core>/<language>/synth directory. This script uses values set in the associated setup.tcl and do_ip.tcl scripts to set the following parameters to appropriate values for synthesizing the core in the selected Altera technology: 1. 2. 3. 4. 5. Device Speed grade Timing constraints Optimization effort Output file: <IPX_core>/<language>/synth/<IPX_core>.edf
then runs the synthesis. Note: The synthesis may also be run by using the facilities of the Quick Setup dialog to select the modules of the design from the appropriate <IPX_core>/<language>/rtl_encrypted directory and to set the required synthesis parameters. You should note however that the order in which the modules are selected is important as it represents the compilation order. Also, when running more than one synthesis in a single session, it is advisable to check that the correct output file is selected before clicking the Run (IP) Flow button.
6.4.2. SYNTHESIZING THE RTL FROM THE DOS COMMAND LINE
1. 2.
Navigate to the directory <IPX_core>\<language>\synth. Execute the supplied spectrum.bat script.
6.4.3. SYNTHESIZING THE RTL FROM THE UNIX COMMAND LINE:
1. 2.
Navigate to the directory <IPX_core>/<language>/synth. Execute the supplied spectrum.scr script.
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7. PERFORMING PLACE & ROUTE
Place & Route uses the EDIF netlist generated using LeonardoSpectrum to generate the netlist required to layout the design on the selected target device. GUI and command line scripts are provided for executing place & route using the Altera Quartus II tool. These are for use following synthesis of the required IPX core using LeonardoSpectrum (as described in the previous chapter). Alternatively, netlists can be processed directly within Quartus II. This chapter outlines the steps used to place & route the IPX cores using the supplied files. For core-specific information, please refer to the quartus.readme file provided for the core. Note: This process requires the use of Version 1.1 or higher of the Quartus II software. You should also note that the netlist generated can be the source for a range of performance and area information about the core in the chosen implementation but it cannot either be simulated (as described in Chapter 8) or be used to program the chosen target device unless a valid Annual Subscription license to Inventra IPX has been installed (as described in Section 3.4).
The files supplied for place & route are provided within the <IPX_core>/<language>/synth/quartus The principal files used are: quartus.tcl quartus.bat quartus.scr quartus.readme Tcl script for place & route. Can be run from within Quartus II. DOS command line script for place & route in batch mode. Calls quartus.tcl. UNIX command line script for place & route in batch mode. Calls quartus.tcl.
directory
Readme file noting core-specific information about place & route and about the files delivered.
For core-specific details, see the q u a rtus. re adm e file included in the quartus directory.
7.2. SETTING THE REQUIRED DEVICE
The files of the Inventra IPX LeonardoSpectrum Altera Release may be used to generate netlists for any programmable logic device from a family such as the APEX II, APEX 20K or FLEX 10K family that is supported by the Altera encrypted IP flow. The scripts supplied in the quartus directory are set up to use Quartus II to produce netlists for implementation on an APEX EP20K400EFC672 device. Place & Route for this device uses cells from the APEX20KE technology library. The details of the device and the technology library used are recorded in the quartus.tcl file, alongside some timing parameters suitable for implementing the core on the selected device. The core may therefore be laid out for a different device by setting the device and library details together with appropriate timing information either directly within the Quartus II tool or in the quartus.tcl file. Note: The target device selected for place & route should also have been selected when the EDIF netlist used by the place & route procedure was synthesized (as described in Section 6.2). If necessary, the synthesis stage should be repeated.
7.3. CARRYING OUT PLACE & ROUTE
Scripts are provided for carrying out place & route from within Quartus II or in batch mode either under DOS or under UNIX. Alternatively, the details for place & route can be set up directly within Quartus II. The script supplied for running the synthesis from within Quartus II is provided as the file quartus.tcl . The scripts supplied for running the synthesis in batch mode are quartus.bat (for DOS) and quartus.scr (for UNIX).
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The quartus.bat and quartus.scr scripts both invoke Quartus II to run the quartus.tcl script. This script: creates a new project named after the core within <IPX_core>/<language>/synth/quartus assigns appropriate values to the various place & route parameters reads in the appropriate technology library reads in the encrypted netlist produced by LeonardoSpectrum sets timing constraints appropriate to the chosen target device processes the netlist
The resulting EDIF netlist is written to a simulation/modelsim subdirectory created within the synth/quartus directory, along with an SDF file. The default name for the netlist is <IPX_core>.vo for the Verilog version or <IPX_core>.vho for the VHDL version. The Verilog version of the SDF file is stored as <IPX_core>_v.sdo , the VHDL version of this file is stored as <IPX_core>_vhd.sdo. The script then terminates Quartus. (To stay within Quartus at the end of place & route, comment out the project close line at the end of the quartus.tcl script.) The steps used to carry out place & route are given below. Note: The scripts are supplied set up to generate netlists for one particular member of the Altera APEX 20K family. To lay out the core for a different device, the user should modify the quartus.tcl file as described in Section 7.2 above. (This change should also have been made in the Synthesis scripts: see Section 6.2 above.) The quartus.tcl script also needs to be edited if the netlist generated by LeonardoSpectrum has been moved from its default location in the synth directory. Core-specific information may be given in the quartus.readm e file included in the synth/ quartus directory.
7.3.1. RUNNING PLACE & ROUTE FROM WITHIN Quartus II
Note: The following just gives an outline of the steps used. For further information, refer to the Quartus II documentation. 1. 2. 3. 4. Invoke Quartus II. Open the Tcl console window by selecting View Auxiliary window Tcl console. Within the Tcl console window, use a cd command to select the directory <IPX_core>/<language>/synth/quartus. Run the supplied quartus.tcl script by using the command: source quartus.tcl
RUNNING PLACE & ROUTE FROM THE DOS COMMAND LINE
7.3.2.
1. 2.
Navigate to the directory <IPX_core>\<language>\synth\quartus. Execute the supplied quartus.bat script.
7.3.3. RUNNING PLACE&ROUTE USING QUARTUS FROM THE UNIX COMMAND LINE:
1. 2.
Navigate to the directory <IPX_core>/<language>/synth/quartus. Execute the supplied quartus.scr script.
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8. GATE-LEVEL SIMULATION
Inventra IPX is shipped with scripts and supporting files for simulating any gate-level netlists that are produced. These files are provided within each cores gate_sim directories. For example, the files for simulating gate-level netlists generated from the Verilog version of the MI2C core may be found within the mi2c/verilog/gate_sim directory. The supporting files include the testbenches for the core compiled into a ModelSim library named work within this directory.
Note: These files are for use in simulating the technology-specific gate-level netlists generated from the supplied encrypted RTL using LeonardoSpectrum and Quartus II (as described in Chapters 6 and 7). The files are of no use if you are using an Evaluation license because the final gate-level netlist can only be produced when you have a valid Annual Subscription license to Inventra IPX installed on your system. The flow for carrying out gate-level simulation is as follows: 1. 2. 3. Compile the gate-level netlist into the same ModelSim library as the compiled testbench. Run the simulation. Compare the listing file that is output against the supplied reference file.
GUI and command line scripts are provided for compiling and running the simulation, with separate command line scripts provided for comparing the generated listing file against the supplied reference file. This chapter outlines the steps that may be taken to verify netlists using the supplied files. For specific information on verifying a particular core, please refer to the gate_sim.readme file provided for the core. Note: The supplied files require the use of Version 5.5c or higher of the ModelSim simulator. They also require access to the technology library used to generate the gate-level netlist. You should also note that the testbenches supplied for a particular core do not test every conceivable mode of operation of the design. It is up to the user to ensure that the mode(s) of operation required by their system configuration are tested.
The files and libraries supplied for gate-level simulation are provided within the appropriate <IPX_core>/<language>/ gate_sim directory. The principal files and libraries for each core are: work <IPX_core> xxx_tb.do <IPX_core> xxx_tb.bat <IPX_core> xxx_tb.scr comp_gate.do comp_altera_lib.do <IPX_core> xxx_tb_diff.bat <IPX_core> xxx_tb_diff.scr gate_sim.readme ModelSim simulation library, supplied comprising compiled versions of the testbenches. One or more GUI script for running the simulations interactively under ModelSim. One or more DOS command line script for running the simulations under ModelSim in batch mode. One or more UNIX command line scripts for running the simulations under ModelSim in batch mode. Script that compiles the netlist generated by Quartus into the work library. (Called by <IPX_core>_tb.do ) Script that compiles the required Altera technology library. (Called by <IPX_core>_tb.do ) One or more DOS command line script that compares the generated listing against a reference file supplied in the rtl_sim directory (if provided). One or more UNIX command line scripts that compare the generated listing against a reference file supplied in the rtl_sim directory (if provided). Readme file noting core-specific information about gate-level simulation and the files delivered.
(Any other files included in this directory will be used by the testbenches during simulation.) For core-specific details, see the gate_sim . re adm e file included in the g ate_sim directory.
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Note: The comp_gate.do script is set up to retrieve the netlist to work on from the <IPX_core>/<language>/ synth/quartus/simulation/modelsim directory. Similarly, the comp_altera_lib.do script is set up to compile the apex20ke simulation libraries which it expects to find in the (QUARTUS_ROOTDIR)/eda/sim_lib directory, the standard location for such files in a Quartus II installation. Any changes that need to be applied to these files should be made before the simulation is run.
8 . 2 . B A C K - A N N O TAT I O N O F T I M I N G I N F O R M A T I O N
Most libraries include an intrinsic delay for each macrocell in the library, for use in the absence of back-annotation. These give the macrocells fixed delays, which assume that the cell outputs have no loads. In order to get a more realistic idea of timing, you need to use back-annotation. Timing back-annotation is supported by reading a Standard Delay Format (SDF) file into the simulation database at compile time. (Most simulators have a switch through which SDF data may be loaded.) SDF files for use with the Inventra IPX cores are generated by the Quartus II Place & Route tool. The file is placed alongside the netlist generated by Quartus II in the directory <IPX_core>/<language>/synth/quartus/simulation/modelsim. The Verilog version of the SDF file is stored as <IPX_core>_v.sdo , the VHDL version of this file is stored as <IPX_core>_vhd.sdo. The scripts provided for simulating the netlist are set up to apply the timing information contained in these files to the design.
8.3. RUNNING THE SIMULATIONS
Scripts are provided for either running the simulations interactively from within ModelSim or for running it in batch mode either under DOS or under UNIX. The scripts supplied for running the simulations from within ModelSim are provided as the files <IPX_core> xxx _tb.do . The scripts supplied for running the simulation in batch mode are provided as the files <IPX_core> xxx _tb.bat (for DOS) and <IPX_core> xxx _tb.scr (for UNIX). The <IPX_core> xxx _tb.bat and <IPX_core> xxx _tb.scr scripts both invoke ModelSim to run the corresponding <IPX_core> xxx _tb.do script. The <IPX_core> xxx _tb.do script: invokes the comp_altera_lib.do script to compile the selected Altera technology library (specified in the comp_altera_lib.do file) invokes the comp_gate.do script to compile the netlist that has been generated by Quartus II into the work library uses the SDF file generated alongside the netlist to back-annotate the design (<IPX_core>_v.sdo for the Verilog version of the design, <IPX_core>_vhd.sdo for the VHDL version of the design) then runs the simulation under ModelSim.
In most cases, both a transcript file and a listing file are produced. Where a listing file is produced, command line scripts are also provided that compare the listing file that is generated against the good reference (see Section 8.3.3). When run interactively from within ModelSim, the script also causes a waveform display to be generated showing the behavior of the cores input and output signals during the test. The steps used to run each simulation are given below. One of the first actions carried out by the scripts is to refresh the supplied work library for the version of ModelSim that you use. Note: You may wish to perform these simulations at a place where you wont overwrite or add new files to the original IPX package. To avoid this, copy the entire IPX data base to a place of your choice and perform simulation there. Core-specific information may be given in the gate_sim . re adm e file included in the g ate_sim directory.
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8.3.1. COMPILING AND RUNNING WITHIN ModelSim
Note: The following just gives an outline of the steps used. For further information, refer to the ModelSim documentation. 1. Invoke ModelSim.
Within ModelSim, perform the following tasks: 2. Navigate to the appropriate <IPX_core>/<language>/gate_sim Directory menu option or by issuing a cd command such as: cd <IPX directory>/mi2c/vhdl/gate_sim 3. Execute the required .do macro by using the Macro Execute Macro menu option or by using a do command such as: do mi2c_tb.do The .do macro both compiles the gate-level netlist previously produced by Quartus II and runs the simulation. Note: In some cases, the simulation listing file is not fully written until the simulation has been terminated (using quit f ).
8.3.2. COMPILING AND RUNNING FROM THE DOS COMMAND LINE
directory either by using the File Change
1. 2.
Use a cd command to navigate to the directory <IPX_core>\<language>\gate_sim. Execute the required <IPX_core> xxx _tb.bat script.
8.3.3. COMPILING AND RUNNING FROM THE UNIX COMMAND LINE:
1. 2.
Use a cd command to navigate to the directory <IPX_core>/<language>/gate_sim. Execute the required <IPX_core> xxx _tb.scr script.
8.4. COMPARING THE GATE-LEVEL SIMULATION AGAINST THE RTL-LEVEL SIMULATION
Except where the testbench is self-checking, each pair of RTL and gate-level simulations produce listing files, typically with names of the form <IPX_core> xxx .lis one in the rtl_sim directory and the other in the gate_sim directory (assuming you have followed these instructions). Comparing these <IPX_core>.lis files will reveal any differences between the behavior of the RTL design and the gate-level netlist. This comparison can be made under DOS by using the FC command or under UNIX by using a diff command. Alternatively the listing file produced by the gate-level simulation may be compared against the reference RTL listing supplied as the <IPX_core> xxx _tb.ref * file in the rtl_sim directory. Command line scripts (<IPX_core> xxx _tb_diff.bat and <IPX_core> xxx _tb_diff.scr files) are provided that compare the listing file that is generated against the supplied reference file. Any differences between these listings will be recorded in a sim_diff.txt text file. Comparisons between the behavior of the RTL and the gate-level versions of the core can also be made by running the RTL simulation within one copy of ModelSim (as described in Section 5.2.1) at the same time as running the gate-level simulation within another copy of ModelSim (as described in Section 8.3.1 above) and comparing the waveform traces generated.
Note: No reference listing files or associated _diff.bat/.scr files are included with self-checking testbenches. You should also note that the reference files for some cores have a .lst, .lis or .vec file extension. For core-specific details, see the gate_sim.readme for the core.
*
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9. IMPLEMENTATION IN A SYSTEM DESIGN

This chapter describes the way in which we suggest you integrate Inventra IPX cores into your design flow. Using an Inventra IPX core in an FPGA/PLD design should not disrupt your design flow. Using the Inventra IPX core in your FPGA/PLD design should be just like using any other separately-designed block. However, it is important to remember that neither the core or the supplied test suites have been designed with any knowledge of the environment in which the core will be used. This chapter goes through the steps involved in a typical FPGA/PLD design flow and discusses how the supplied design material fits in with each part of the process. You will also be pointed to the part of this guide that is relevant to the different points in this flow.
9.1. STAGE 1: SYSTEM SPECIFICATION
Functional Information: Functional information about a cores design and interface requirements can be obtained from the cores Product Specification (supplied in its docs directory). You may also find it helpful to refer to the documentation available about the reference part for the design (typically named in the cores Product Specification). Design Partitioning: The area required for the core within your design will be easy to determine where you have already used the selected core in your chosen target technology. If not, you can obtain an estimate of the area required by reading the EDIF netlist generated by Leonardo Spectrum into Alteras Quartus II. The report generated after compilation contains a Resource Usage Summary which includes a table of cells from which you will be able to deduce the approximate size of the core in your chosen device.
9.2. STAGE 2: DESIGN CAPTURE
Having specified and partitioned the system, the next step is to implement the design. If you have already synthesized the core for your chosen target device, you will probably do this by selecting the netlist generated by LeonardoSpectrum as part of a larger design within the Quartus II Place & Route tool. Alternatively, you might instantiate the core as a component in an RTL source file. Two files that may be helpful in this a Quartus symbol file and an HDL template containing a sample instantiation of the core are provided for each IPX core in the directory <IPX_core>/<language>/template. Instantiating the Core in Quartus: A Quartus symbol file for the core is provided in the template directory as the file <IPX_core>.bsf . This symbol file is supplied for use where you have already synthesized the core. Place the symbol in the Quartus schematic editor, map it to the core EDIF netlist and connect it up to the rest of the system. Instantiating the Core in an RTL source file: The simplest way to instantiate an Inventra IPX core in an RTL source file is to cut and paste the component instantiation provided in the template file ( <IPX_core>.template ) into the RTL source file. This will provide the necessary link to the encrypted RTL files.
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9.3. STAGE 3: SYSTEM VERIFICATION
One of the most common sources of design errors is in the interconnections between blocks. It is therefore very important that you simulate the overall system, and that you run a simulation which tests your FPGA/PLD design in the way in which you intend to use it in its target application. For this, you will need to create your own test suite. It will not be possible to adapt the supplied testbench. Where an Inventra IPX core has been instantiated in an RTL source file, you will be able to run your simulation at RTL level. To model the Inventra IPX core, create a mapping to either the compiled model of the encrypted RTL files in the rtl_sim/work library or the compiled netlist in the gate_sim/work library created when the core was simulated at gate-level. Where the core has been instantiated as a netlist within the Quartus schematic editor, however, you can only carry out a gate-level simulation of the design (as described in Section 9.6 below). Note: The fact that each Inventra IPX core has been verified doesnt mean that your test suite doesnt need to verify the functionality of the core, because there may be a facet of the way in which you are using it in your system that causes problems. This may be as a result of a misunderstanding about exactly what it does, or it may be due to an interface issue.
9.4. STAGE 4: SYNTHESIS
Where the core has been instantiated in an RTL source file, the next step is to synthesize the design into a gate-level netlist for the target technology. As a result of the format in which the cores are supplied, designs incorporating IPX cores from this edition of the Inventra IPX suite need to be synthesized using LeonardoSpectrum for implementation on one of the Altera devices supported by the Altera encrypted IP flow. However, rather than synthesize the whole design, you are recommended to instantiate any IPX cores as black boxes which you synthesize separately and only re-incorporate with the rest of the design at the Place & Route stage. The reason for this is that the range of control you have over the way in which a design is synthesized within the LeonardoSpectrum tool is very much reduced if it includes any encrypted RTL. The steps used for the overall design will be much the same as those used to synthesize the core as a stand-alone item. It may therefore be possible to adapt the synthesis scripts provided with the core to suit the requirements of your system design. Details of these scripts are given in Chapter 6 of this User Guide.
9.5. STAGE 5: PLACE & ROUTE
Again as a result of the format in which the cores are supplied, the complete design will need to be laid out for implementation on one of the supported Altera devices. Also the place & route procedure will need to be carried out using Quartus II. Again, it may be possible to adapt the supplied quartus.tcl script to carry out the place and route for the complete design using Quartus in very much the same way used for individual Inventra IPX cores (described in Chapter 7).
9.6. STAGE 6: GATE-LEVEL VERIFICATION
After synthesis, the gate-level implementation of the system FPGA/PLD will need to be verified using the test suite generated at the system verification stage.
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10.
HELP
This chapter is intended to offer assistance when you come to a point in using the Inventra IPX cores at which you are not sure how to proceed. Four main areas are considered: Simulation problems Synthesis Problems Place & Route Problems Queries about the cores
If you cant find the answer to your problem here or in the section of this User Guide that deals with the action you are trying to take, then please contact Customer Support (see Chapter 11).
10.1. SIMULATION PROBLEMS
This section looks at some problems that might be encountered in simulating an Inventra IPX core using the supplied testbenches and scripts. For help with aspects of using ModelSim that dont relate directly to using Inventra IPX, please consult the ModelSim on-screen help or, if necessary, consult Model Technology Customer Support ( email support@model.com ). IMPORTANT: Users of an OEM version of ModelSim supplied by Altera should contact Alteras Customer Support. The contact information to use is given in Section 10.3.
The supplied scripts dont run

There are two likely explanations. 1. ModelSim is not on the current system path. The scripts provided with the Inventra IPX cores all assume that each of the tools that are used are available on the system path. To correct this, either edit the .bat/.scr scripts to record the full path on your system to the ModelSim executable or add its location to your system path. (The standard path entry for ModelSim Version 5.5c on a PC is C:\Modeltech_5.5c\win32. ) 2. You have not installed your Inventra IPX license correctly. This license should have been appended to the file pointed to by the LM_LICENSE_FILE environment variable. If this variable points to more than one file, then it should have been appended to the license file that contains the license for the Quartus tool. Earlier entries for Inventra IPX should have been commented out. See Section 3.4.
No Listing file (.lis file) appears to have been generated

There are two things to note here. Firstly, some of the testbenches are self-checking: such testbenches do not produce a listing file. The other thing to note is that, in some cases, the listing file is not written until the simulation has been terminated (with a quit f command).
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ModelSim is unable to locate Altera Simulation models (Gate-Level Simulation)

The gate-level simulation scripts are set up to expect the required Altera simulation libraries to be in the directory (QUARTUS_ROOTDIR)/eda/sim_lib. If ModelSim is unable to locate these libraries, the likely explanation is that the QUARTUS_ROOTDIR system variable has not been set up correctly. Alternatively, the libraries have been moved to a non-standard location in which case the full path to these libraries needs to be recorded in the file. comp_altera_lib.do
ModelSim is unable to find the place and routed version of the core (Gate-Level Simulation)
The gate-level simulation scripts are set up to expect to process netlists that have been placed by Quartus II in a directory called <IPX_core>/ <language>/synth/quartus/simulation/modelsim. If the netlist has been moved to a non-standard location, you will need to record the location of the netlist in the comp_gate.do file. Alternatively, you are using Inventra IPX with an Evaluation license. This license allows you to simulate and synthesize the IPX cores and to obtain performance and area information about these cores on different Altera devices. However, it doesnt allow you to produce a final gate-level netlist. To produce this netlist, you need to acquire an Annual Subscription license to Inventra IPX. For information on how to obtain the required license, please either email your sales representative at ipx@hdlsolutions or visit the Inventra IPX web site at http://www.mentor.com/inventra/ipx. If you have already acquired an Annual Subscription license, then the likely explanation is that you have not installed this license correctly see Section 3.4.
10.2. SYNTHESIS PROBLEMS
This section looks at some problems that might be encountered in synthesizing an Inventra IPX core. For help with aspects of using LeonardoSpectrum that dont relate directly to using Inventra IPX, please consult the LeonardoSpectrum on-screen help or, if necessary, consult Mentor Graphics Exemplar Customer Support ( email support@exemplar.com ). IMPORTANT: Users of an OEM version of LeonardoSpectrum supplied by Altera should contact Alteras Customer Support. The contact information to use is given in Section 10.3.

There are two likely explanations. 1. LeonardoSpectrum is not on the current system path. The scripts provided with the Inventra IPX cores all assume that each of the tools that are used are available on the system path. To correct this, either edit the scripts to record the full path on your system to the spectrum executable or add its location to your system path. (The standard path entry for LeonardoSpectrum Version 2001.1b (Level 12) on a PC is C:\EXEMPLAR\LEOSPEC\LS2001_1b_12 )
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INVENTRA
2.
You have not installed your Inventra IPX license correctly. This license should have been appended to the file pointed to by the LM_LICENSE_FILE environment variable. If this variable points to more than one file, then it should have been appended to the license file that contains the license for the Quartus tool. Earlier entries for Inventra IPX should have been commented out. See Section 3.4.
LeonardoSpectrum reports an undeclared module

LeonardoSpectrum has found a reference to a module that hasnt yet been compiled. The most likely explanation for this is that the modules that need to be compiled have been picked out in the wrong order or one has been accidentally omitted from the list. The correct compilation order may be found in (an unedited version of) the do_ip.tcl script.
10.3. PLACE & ROUTE PROBLEMS
This section looks at some problems that might be encountered in using Inventra IPX. For help with aspects of using Quartus II that dont relate directly to using Inventra IPX, please consult the Quartus II on-screen help or, if necessary, consult Altera Customer Support as follows: By phone: By email: Via the web: 800-800-3753 or (+1) 408-544-7000 support@altera.com http://websupport.altera.com

Assuming that you have already successfully used LeonardoSpectrum to synthesize the supplied RTL, the likely explanation is that Quartus II is not on the current system path. The scripts provided with the Inventra IPX cores all assume that each of the tools that are used are available on the system path. To correct this, either edit the scripts to record the full path on your system to the Quartus II executable or add its location to your system path. (The standard path entry for Quartus II Version 1.1 on a PC is %QUARTUS_ROOTDIR%\bin with the system variable QUARTUS_ROOTDIR = C:\quartus .)
Quartus II reports Source File not found

Quartus has failed to find an EDIF file to process. There are two likely explanations: 1. 2. You have omitted to produce this file (generated by running LeonardoSpectrum). The EDIF netlist was saved to somewhere other than the default location. To correct this, edit the quartus.tcl script to record the actual location of the <IPX_core>.edf file.
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10.4. QUERIES ABOUT THE CORES
This section contains some of the more common questions about the IPX cores. Further information about the cores can be found from a set of Core FAQs available through the Inventra IPX web site at http://www.mentor.com/inventra/ipx.
What kind of Support is offered?

Please see Chapter 11.
Do the cores follow any certification or compliance standards? If so, which?

Inventra design team members and management sit on several standards committees including VSIA and are well-aligned with the standards committees in general. Additionally, established reuse methodology guidelines are followed during the design and evaluation of Inventra cores. It is a general ongoing goal of Inventra to adhere to all applicable standards and guidelines, with management taking an active part in ensuring that products meet the standards currently expected by the industry.
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11.
SUPPORT
Mentor Graphics offers multiple methods for contacting us for resolution of pre-sales and post-sales support questions. Our objective is to provide dedicated support to allow our customers using Inventra IPX to work effectively and maximize their productivity. For general Inventra IPX questions, please contact ipx_info@mentor.com
11.1. PRE-SALES SUPPORT
Email your pre-sales questions to ipfpga_support@mentor.com
11.2. POST-SALES SUPPORT
Mentor Graphics offers two levels of support to Annual Subscription licensees:

11.2.1. GET STARTED SUPPORT
Get Started Support is automatically included with an Annual Subscription license to Inventra IPX. This first level of support covers the user for Installation and Licensing questions. You will also be automatically notified if a bug is discovered within an intellectual property (IP) core and will receive any appropriate fix for the affected core.
11.2.2. CORE QUESTION SUPPORT
Core Question Support is an optional support product. This level of support enables the user to contact us with Inventra IPX core-specific questions. Like the Inventra IPX product itself, this support product is offered on an annual renewal basis for an additional fee.
11.2.3. POST-SALES SUPPORT CONTACTS
WEB: http://www.mentor.com/supportnet Note: First time visitors to this site need to register. EMAIL: support_net@mentor.com Note: Requires prior registration via the above SupportNet web site. TELEPHONE: 1 800 547 4304 (US or Canada only) Users in other parts of the world can call any of the customer support offices listed at http://www.mentor.com/supportnet/ support_offices.html DISTRIBUTOR POST-SALES CONTACTS: Customers who have acquired Inventra IPX from their local distributor should contact their distributor for support. For distributor contact information, see http://www.mentor.com/inventra/ipx/contact_us.html.
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12. REVISION HISTORY
12.1. ISSUE 1
31st August 2001. Initial version of the document. PC implementation only.
12.2. ISSUE 2
4th December 2001. Extended to cover UNIX implementations.
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2001 Mentor Graphics Corporation, All Rights Reserved. Mentor Graphics and ModelSim are registered trademarks of Mentor Graphics Corporation. Altera and Quartus are registered trademarks of Altera Corporation. Inventra, Inventra IPX and LeonardoSpectrum are trademarks of Mentor Graphics Corporation. APEX and FLEX are trademarks of Altera Corporation. All other trademarks are the property of their respective owners.
http://www.mentor.com/inventra
Pacific Rim Headquarters Mentor Graphics (Taiwan) Room 1603, 16F, International Trade Building No.333, Section 1, Keelung Road Taipei, Taiwan, ROC Phone: 886-2-87252000 Fax: 886-2-27576027 Japan Headquarters Mentor Graphics Japan Co., Ltd. Gotenyama Hills 7-35, Kita-Shinagawa 4-chome Shinagawa-Ku, Tokyo 140 Japan Phone: 81-3-5488-3033 12/01 Fax: 81-3-5488-3021
Corporate Headquarters Mentor Graphics Corporation 8005 S.W. Boeckman Road Wilsonville, OR 97070 USA Phone: 503-685-7000 North American Support Center Phone: 800-547-4303 Fax: 800-684-1795
Silicon Valley Headquarters Mentor Graphics Corporation 1001 Ridder Park Drive San Jose, California 95131 USA Phone: 408-436-1500 Fax: 408-436-1501
Europe Headquarters Mentor Graphics Corporation Immeuble le Pasteur 13/15, rue Jeanne Braconnier 92360 Meudon La Foret France Phone: 33-1-40-94-74-74 Fax: 33-1-46-01-91-73
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LeonardoSpectrum Altera Release (PC / UNIX edition)

INVENTRA IPX USER GUIDE

For Pre-Sales Support on this product (Evaluation License):

For Post-Sales Support on this product (Annual Subscription License):

Additional information is provided in Chapter 11.

LeonardoSpectrum Altera Release

INVENTRA IPX USER GUIDE

LeonardoSpectrum Altera Release

INVENTRA IPX USER GUIDE

LeonardoSpectrum Altera Release

2. THE LEONARDOSPECTRUM ALTERA RELEASE

2.1. THE TOOLS REQUIRED

2.3. PRODUCT FLOW

INVENTRA IPX USER GUIDE

3. INSTALLATION AND LICENSING

3.1. LICENSING INVENTRA IPX

3.2. INSTALLING INVENTRA IPX FROM A CD

LeonardoSpectrum Altera Release

3.3. INSTALLING INVENTRA IPX FROM THE WEB

INVENTRA IPX USER GUIDE

3.4. INSTALLING LICENSES

LeonardoSpectrum Altera Release

4.2. DESIGN CONVENTIONS

INVENTRA IPX USER GUIDE

4.3. PRODUCT SPECIFICATION

LeonardoSpectrum Altera Release

5.1. THE FILES PROVIDED

INVENTRA IPX USER GUIDE

5.2. RUNNING THE SIMULATIONS

5.2.3. RUNNING THE SIMULATION FROM THE UNIX COMMAND LINE

LeonardoSpectrum Altera Release

6.1. THE FILES PROVIDED

6.2. SETTING THE REQUIRED DEVICE

INVENTRA IPX USER GUIDE

6.3. SYNTHESIS CONSTRAINTS

6.4. RUNNING THE SYNTHESIS

LeonardoSpectrum Altera Release

Figure 1: Leonardo Spectrum Quick Setup GUI

INVENTRA IPX USER GUIDE

Navigate to the directory <IPX_core>\<language>\synth. Execute the supplied spectrum.bat script.

6.4.3. SYNTHESIZING THE RTL FROM THE UNIX COMMAND LINE:

Navigate to the directory <IPX_core>/<language>/synth. Execute the supplied spectrum.scr script.

LeonardoSpectrum Altera Release

7.1. THE FILES PROVIDED

7.2. SETTING THE REQUIRED DEVICE

7.3. CARRYING OUT PLACE & ROUTE

INVENTRA IPX USER GUIDE

Navigate to the directory <IPX_core>\<language>\synth\quartus. Execute the supplied quartus.bat script.

Navigate to the directory <IPX_core>/<language>/synth/quartus. Execute the supplied quartus.scr script.

LeonardoSpectrum Altera Release

8.1. THE FILES PROVIDED

INVENTRA IPX USER GUIDE

8.3. RUNNING THE SIMULATIONS

LeonardoSpectrum Altera Release

directory either by using the File Change

8.3.3. COMPILING AND RUNNING FROM THE UNIX COMMAND LINE:

8.4. COMPARING THE GATE-LEVEL SIMULATION AGAINST THE RTL-LEVEL SIMULATION