Formation of Ni-Silicide Nanowires on Silicon-on-Insulator Substrates by Atomic Force Microscope Lithography and Solid Phase Reaction

Ting-Hsuan Chen, Hsun-Feng Hsu and Hwang-Yuan Wu ECS J. Solid State Sci. Technol. 2012, Volume 1, Issue 2, Pages P90-P93. doi: 10.1149/2.022202jss Email alerting service
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2012 The Electrochemical Society

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ECS Journal of Solid State Science and Technology, 1 (2) P90-P93 (2012)
2162-8769/2012/1(2)/P90/4/$28.00 The Electrochemical Society

Formation of Ni-Silicide Nanowires on Silicon-on-Insulator Substrates by Atomic Force Microscope Lithography and Solid Phase Reaction
Ting-Hsuan Chen, Hsun-Feng Hsu,z and Hwang-Yuan Wu
Department of Materials Science and Engineering, National Chung Hsing University, Taichung, Taiwan Nickel silicide nanowires were fabricated by atomic force microscopy nano-oxidation on silicon-on-insulator substrates, selective wet etching, Ni deposition and a solid phase reaction. Si nanowires with various widths can be fabricated using oxide lines with various widths, which can be controlled by tuning the sample bias during nano-oxidation. When the ratio of the thickness of Ni lms to the height of Si nanowires was 1.8, the Ni-rich silicide phases were obtained and were depended on the width of the Si nanowires. Ni atoms on top of and around the Si nanowires participated in the formation of silicide. NiSi nanowires were fabricated by measuring the width of nanowires accurately and tuning the thickness of Ni lms that were estimated on the basis of 1 of Ni/Si atomic ratio. Resistivity of the NiSi nanowires increased as their width decreased, mainly because of the polycrystalline structure of nanowires and the electron scattering by grain boundaries. 2012 The Electrochemical Society. [DOI: 10.1149/2.022202jss] All rights reserved. Manuscript submitted March 1, 2012; revised manuscript received May 17, 2012. Published July 20, 2012.

Si nanowire has been widely investigated for applications in nanoelectronic devices, such as nanowire MOSFETs1 and sensors.2 Most related studies involved the formation of Si nanowires by vapor-liquidsolid growth.38 The freestanding Si nanowires thus formed are placed on an isolated substrate for use in fabricating a device. However, such a method encounters the difculty of manipulating the nanowires. Another problem is that an oxide layer is invariably formed on the surface of an Si nanowire, increasing the contact resistance between it and the electrode. The feasibility of fabricating Si nanowires in the semiconductor industry by the lithography of an ultra-thin body silicon on insulator (SOI) has received considerable interest recently.9,10 This method involves an easy manipulation of Si nanowire, on which no oxide layer is formed. Atomic force microscope (AFM) nano-oxidation is a simpler lithographic method than others, such as E-beam lithography and X-ray lithography. When combined with selective etching, AFM lithography can pattern the Si wafer11 and fabricate Si-nanowire-based nanoelectronic devices using the ultra thin body SOI substrate.1214 Related studies have explored the feasibility of using Si nanowires with respect to the formation of silicide in Si nanowires.3,4,68 NiSi nanowires have a low resistivity and signicantly high failure current densities when they have ultra-small dimensioins.5 Thus, as is expected, NiSi nanowires are the interconnects in nanoelectronic devices in the future. In this work, Si nanowires are fabricated by AFM nano-oxidation and selective wet etching, and then undergo a solid-phase reaction with Ni-coated lms to form Ni silicide nanowires. Because the thermodynamic stable phase of Ni silicide depends strongly on the atomic ratio of Ni to Si15 this work focuses on the effect of the atomic ratio of Ni to Si on the formation of Ni-silicide nanowires in an Ni-metalcoated Si nanowire system. The effects of the width of nanowires on the structural and electrical properties of nanowires are also discussed. Experimental Figure 1 shows the process for fabricating Ni-silicide nanowires in Si nanowires. SOI wafers fabricated by the Smart-Cut process were used. The 20 nm-thick silicon toplayer was insulated from the bulk silicon substrate by a 150-nm thick buried oxide. The silicon layers were cleaned by a standard RCA process16 and, then, dipped in a dilute HF solution before nano-oxidized by AFM. Nano-oxidation was then performed using a commercial AFM (Solver PRO-M, NTMDT) that was operated in the contact mode using PtIr silicion-coated tips (constant force of 0.2 N/m, resonance frequency of 13 kHz). The Si nanowires were formed by a wet etching process, in which the

Figure 1. Schematic diagrams of sample preparation. (a) Cleaned SOI substrate, (b) AFM oxidation, (c) selected etching by KOH solution, (d) selected etching by HF solution, (e) Ni deposition, and (f) rapid thermal annealing treatment.

nano-oxidized samples were immersed in the 20 wt% KOH solution at 50 C for 30 s. Before loaded into an E-beam deposition chamber, the samples were dipped in a dilute HF solution to remove the oxide layer on the surface of Si nanowires. Pressure of the chamber was below 1 106 torr and the deposition rate was 0.1 /s. Next, the Ni-metalcoated Si nanowires on the insulator substrates were annealed in a rapid thermal annealing apparatus at 500 C for 1min in a forming gas (with an Ar:H2 ratio of 95:5). The unreactive Ni atoms were removed by the HNO3 solution. Width of the nanowires, as measured by the AFM, must be modied because of the shape of its tip.17,18 Figure 2a shows the SEM image of the AFM tip. The curvature of the tip was about 30 nm, and the half cone angle of the tip was 25 . Because the sidewall angle of silicon (54.7 ) was smaller than the angle between sidewall of tip and the surface (65 ), the line prole of translation of the curvature center can be as the black solid line in Fig. 2b. The full width of half maximum (FWHM) of the Si nanowire G H is subtracted from the measured FWHM by the AFM tip, which is D E ; the spread size C D is obtained as well. The green solid line shows the outline of the tip when the tip scans arriving at point F. A is the center of curvature is less than of tip apex, and AF is the radius of curvature. When h 2 30 1 cos 54.70 nm, point D is at the curve AJ. C D = B D BC = B D G I = AF B F G I
h 2 2 2

E-mail: hfhsu@dragon.nchu.edu.tw

Where, AF = 30 B F = 30

h 2

GI =

cot 54.70

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2.8
Oxidation Height (nm)

2.4 2.0 1.6 1.2 0.8 0.4 0.0 4 5 6 7 8 9 10 11 12 Voltage (V)

R~30 nm

100 nm

90
Oxidation Width (nm)

80 70 60 50 40 30 20 4 5 6 7 8 9 10 11 12 Voltage (V)

h 2
54.7

54.7

h 2

Figure 2. (a) SEM image of the used AFM tip with the curve radius of about 30 nm. (b) A diagram of the cross-section of Si nanowire and a line prole of translations of the AFM tip. The black solid line is a line prole of translations of the curvature center at the tip apex, and the shaded area shows the shape of the cross-section of the Si nanowire. Because Si nanowire that is etched by KOH solution has the {111} sidewall planes, the sidewalls are 54.7 to the (100) bottom plane.

Figure 4. Relation between sample voltage and (a) height and (b) width of oxide lines.

Thus, the spread size C D can be obtained as

h 2 0

302 (30 h )2 2

cot 54.7 nm, when h 25.3 nm. The morphologies of nanowires were observed using eld emission scanning microscopy (FESEM) (JOEL JSM-6700F with an accelerated voltage of 3 kV) and AFM operating in the tapping mode with silicon tips (constant force of 42 N/m and resonance frequency of 330 kHz). Electrical measurements were then taken using an Agilent B1500A semiconductor device analyzer (SDA) with a probe station. Finally, the crystal structures of NWs in a JOEL JEM-2100F operating at 200 kV were veried using transmission electron microscopy (TEM) analysis. Results and Discussion Figure 3 shows the oxide lines written on the Si substrate along the Si<110> direction with a contact force of 3 nN at a scan speed of 0.1 m/s and sample voltages of 6, 8 and 10 V with respect to the tip. The relative humidity was 50%. Height of the oxide lines was

proportional to the sample voltage, as shown in Fig. 4a,19,20 and the threshold voltage (Vth ) was 3.95 V. Selective etching was performed by immersing the nano-oxidized sample in a 20 wt% aqueous KOH solution at 50 C for 30 s. Under these conditions, the Si(100) etch rate was 0.15 m/min and the thermally grown SiO2 etching rate was 0.33 nm/min.21 The selectivity S (RSi(100) /RSiO2 ) was about 450. Additionally, etching of the (111) crystallographic plane was much slower than that of other planes. A high anisotropic etching ratio greater than 400:1 ({100}:{111}) can be routinely obtained in the most used KOH/H2 O etchant system.22 Therefore, the ideal etching ratio of Si{100}:Si{111}:SiO2 is 450:1.125:1. Thus, the Si nanowires with {111}-plane sidewalls were obtained here under the oxide lines (Fig. 5). However, when the height of the formed oxide line was insufcient, a discontinuous Si nanowire was obtained (Fig. 5a), because several parts of the oxide line had been etched completely during selective etching. Figure 4a indicates that the average height of the oxide line formed by a 6 V sample bias was about 0.78 nm. Since the ratio of the produced height h to the buried depth d of the oxide was about 2:1,23,24 the total thickness of the oxide lines was about 1.17 nm. For 30 s of etching, the ideal etched thickness of SiO2 was around 0.165 nm. In practice, the etching rate of SPM oxide (SiOx ) is higher than that of thermal oxide because the structural properties of SPM oxide differ from those of thermal

(a)

(b)

(c)

500 nm 0 1.0 2.0 3.0

500 nm 0 1.0 2.0 3.0 4.0 5.0 0

500 nm 1.0 2.0 3.0 4.0 5.0 nm

Figure 3. AFM images depicting the oxide lines by applying sample voltages of (a) 6 V, (b) 8 V, and (c) 10 V.

Figure 5. (a), (b) and (c) are the AFM image of the Si nanowires that were formed by immersing the samples shown in Fig. 3a, 3b and 3c respectively in KOH solution for 30 s. The height of nanowires in (b) and (c) were 22 nm.

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Figure 8. SEM images of Si nanowires with the widths of (a) 50 and (b) 100 nm that reacted with 7.5 nm Ni lms by RTA at 500 C for 1 min.

Figure 6. The cross-sectional TEM images of Ni-silicide nanowires formed by annealing the 10 nm Ni-coated Si nanowires, with FWHM of (a) 28, (b) 39 and (c) 52 nm respectively at 500 C. (d), (e) and (f) are the crosssectional HRTEM images of Ni-silicide nanowires and the areas correspond to the squares in (a), (b) and (c) respectively.

oxide.25 In this work, when the height of the oxide line exceeded 1.24 nm, a continuous Si wire was obtained by 30 s of selective etching. Figure 4b indicates that FWHM of the oxide lines increased with the sample bias. The width of Si nanowires depended on the oxide line mask. Si nanowires of various widths can be fabricated using oxide lines of various widths, which can be controlled by tuning the sample bias during nano-oxidation. Herein, after the oxide line on the Si wires was removed, the heights of silicon wires were 1718 nm. According to the thin-lm reactions of Ni with Si, the consumption ratio of Si to Ni in the formation of NiSi is 1.83.26 Thus, as is expected, annealing the 10 nm Ni-caoted Si nanowires at 500 C formed the NiSi nanowires. Figures 6a, 6b and 6c present the cross-sectional TEM images of Ni-silicide nanowires that were formed by the solid phase reaction of 10 nm Ni-coated Si nanowires, with FWHM values of 28 nm, 39 nm and 52 nm respectively. The phases of the Ni-silicide nanowires shown in Fig. 6a, 6b and 6c were Ni2 Si, Ni3 Si2 and Ni3 Si2 respectively. These results were unexpected, as discussed below. According to a previous study,15 the stable Ni silicide phases depend on formation methods. First, when a thin metal reacts with a thick Si layer, the stable phase is NiSi2 . Second, the thermodynamically stable phase formed when a thin Si lm reacts with a thick Ni layer is Ni-rich. Third, when neither excess Ni nor excess Si is present, the ratio of Ni atoms to Si atoms determines the equilibrium phase. In this work, Ni-silicide was formed from Ni-coated Si nanowires, which can be regarded as the third method. Assume that the only Ni lm on top of the Si nanowire reacts with Si to form a silicide wire. Figure 7a displays a diagram of across section of Ni-coated Si nanowires. Formula 1 yields the atomic ratio of Ni to Si. atomic ratio of Ni/Si = ( F W H M Si + h Si cot 54.7 ) h N i F W H M Si h Si
d Si M Si dN i MN i

values are higher than the ideal Ni/Si atomic ratio of NiSi, resulting in the formation of Ni-rich phases. Moreover, in this work, the Ni/Si atomic ratio increased as the width of nanowire decreased. Because the estimated values of Ni/Si atomic ratio using Formula 1 are lower than the ideal Ni/Si atomic ratios of Ni2 Si and Ni3 Si2 (i.e. the above identied Ni-silicide phases), we can infer that some Ni atoms around the Si nanowires diffused to the Si nanowires, and participated in the formation of silicide. To form NiSi phase, the thickness of Ni lm was estimated by formula 1 with 1 of the Ni/Si atomic ratio by assuming that the diffusion of Ni atoms around Si nanowires was neglected. Thus, when the FWHM of nanowire was 50 nm, Ni lm with a thickness of 7.5 nm was required. Figure 8a shows the experimental result, in which a continuous NiSi is formed in the Si nanowire. According to previous studies, NiSi phase can be obtained by a solid phase reaction at 500 C when the atomic ratio of Ni/Si ranges from 0.8 to 1.3.27,28 Therefore, the diffusion of Ni atoms around Si nanowires can be neglected when the thickness of Ni lms is estimated by formula 1. Meanwhile, in the Si nanowire with an FWHM of about 100 nm, the NiSi was discontinuous [Fig. 8b]. This phenomenon is regarded as being related to the excess Si in the system. Additionally, NiSi was a thermodynamically stable phase when the sample was annealed at 500 C. Because NiSi easily agglomerates, when the thickness of Ni lm was less than 10 nm,2931 a discontinuous NiSi was obtained. Figure 9 shows examples

(a)

(b)
( f) (f)

(102) (010) (102)

(010)

(c) NiSi(102)
(h (h

NiSi(010)

[1] Where hSi is the height of Si nanowires (18 nm); hNi is the thickness of Ni lms (10 nm); dNi is the density of Ni (8.91 g/cm3 ); MNi is the atomic weight of Ni (58.69 g/mole), dSi is the density of Si (2.33 g/cm3 ), and MSi is the atomic weight of Si (28.09 g/mole). According to formula 1, when the FWHMs of Si are 28, 39 and 52 nm, the atomic ratios of Ni/Si are 1.48, 1.35 and 1.27 respectively. These

(d)

(e)

(100) (001)

(f)
NiSi(001) NiSi(100)

Figure 7. The schematic diagram of the cross-section of Ni-coated Si nanowire. The white area is the cross-sectional area of Si nanowire. The gray area is the cross-sectional area of the Ni lm that is on top of Si surface.

Figure 9. The cross-sectional TEM images of nanowires. (a) The 57 nmwidth NiSi nanowire has two grains with different orientations, and (b) is the corresponding diffraction pattern. (c) Atomic-resolution TEM image of the 57 nm-width NiSi nanowire and the area corresponds to the square in (a). (d) The 124 nm-width NiSi nanowire has a single grain, and (e) is the corresponding diffraction pattern. (f) Atomic-resolution TEM image of the 124 nm-width NiSi nanowire and the area corresponds to the square in (d).

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width decreased, mainly owing to the polycrystalline structure of nanowires and electron scattering by grain boundaries. Acknowledgment The research is supported by the Republic of China National Science Council grant no. NSC 99-2221-E-005-102-. References
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Resistivity (cm)

200

150

100

50 20 40 60 80 100 120

FWHM (nm)
Figure 10. Relation between the resistivity and the FWHM of NiSi nanowires. The insert is the SEM image of NiSi nanowire and Pt electrodes.

of NiSi nanowires with various widths fabricated by tuning the thickness of the Ni lms deposited on Si nanowires of various widths. In this work, decreasing the width of the NiSi nanowires from 124 to 36 nm increased the resistivity from 63 to 244 cm (Fig. 10). The resistivity was higher than that in previous works (10 cm).5 Wu fabricated Si nanowires by using the vapor-liquid-solid (VLS) mechanism, in which a silicon oxide lm was simultaneously formed on their surfaces. This oxide layer served as a diffusion barrier against the diffusion of Ni into Si. Additionally, the low rate of dissolution of Ni atoms caused the formation of single crystalline Ni silicide nanowires.32,33 In the Si nanowires without an oxide lm, Ni silicide can form everywhere, resulting in polycrystalline Ni silicide grains.32 Moreover, the cross-sectional TEM image of a 57 nm-wide NiSi nanowire (Fig. 9a) and its corresponding diffraction pattern (Fig. 9b) show two grains with different orientations. We can thus infer that the NiSi nanowires in this work were polycrystalline. In polycrystalline nanowires, the grain size decreased as the width of the nanowires decreased. Hence, thinner nanowires had a higher resistivity owing to a higher probability of scattering of the conduction electrons by the grain boundary.34 Conclusions Nickel silicide nanowires were fabricated by atomic force microscopy oxidation on silicon-on-insulator substrates, selective wet etching, Ni deposition and a solid phase reaction. The phase of the subsequently formed Ni-silicide wire depended on the width of the Si nanowire when the thickness of Ni lm was xed. Ni atoms on top of and around the Si nanowires participated in the formation of silicide. NiSi nanowires were fabricated by measuring the width of nanowires accurately and, then, tuning the thickness of Ni lms that were estimated basisd on 1 of Ni/Si atomic ratio. NiSi nanowires with the widths of 124 to 36 nm had a resistivity ranging from 63 to 244 cm. Moreover, the resistivity of nanowires increased as their