Switched-Capacitor Integrator/Gain Blocks

Idealized

view Fundamental Performance Limitations Practical Performance Limitations Gain Blocks for Low Voltage/Low Power

PRG, Gain blocks, 1

Basic Integrator/Gain Functions

Integrating Gain Block: Vi2 Von = -[Von-1 + (Vi1n-Vi1n-1)]C1/C2 + Vi2n-1(Cs/C2)] Vi1 1 C1 2 C2 1

Reset Gain Block: 1 C1 Vi

1 C2

Von = -C1/C2 (Vin-1) 1

PRG, Gain blocks, 2

Important Deviations from Ideality:

Gain Errors
Capacitor Ratio Errors Capacitive Parasitics in Feedback Path Finite Op Amp Gain

DC. Offset Errors

Op amp offset Charge Injection offsets

Transient Errors
Operational Amplier Settling

PRG, Gain blocks, 3

Key Issue: What is the fastest attainable settling?

Simplest possible op amp: Cf Cs Cl Cs Cl Cp Cf+Cgd=Cft

Cgs

Cl+Cp =CLt
This is a single-time-constant circuit!
+

1 (C + C ) 1 s gs g m

1+

Lt Ft C +C C gs s Ft

C 1 1 + Lt C 2f Ft t

Fixed Vgs-Vt
= C C C 1 1 + s 1 + 1 + Ft Lt C C 2f C +C gs t gs s Ft

Device Width and Drain Current

PRG, Gain blocks, 4

Max Attainable Speed, Contd

Assume Cgs=Cs as a practical design choice
= C C 2 1 + 1 + Ft Lt 2f 2C C t s Ft

0.5ns 0.2ns 0.1ns

C 2 1 + 1 + A Lt 2 v C 2f S t

Where Av = Voltage Gain of circuit

Assumptions: 1. Square law applies 2. No slewing 3. Vgs-Vt = 0.5V 4. Neglects all second order device effects. 5. Av = 1, Cl=Cf

0.8u1.0u

1.5u

3u

PRG, Gain blocks, 5

Two Important Limiting Cases

Cs/Cf>>1, As in Reset Gain Blocks in Pipelines
= C 2 1 + L 2f C t F =

2 (1 + a ) q 2f t

Cs/Cf<<1, As in Switched Cap Integrators

C 2 1 + L 2f 2C t S

Sigma-Delta Integrators are usually in between these extremes

PRG, Gain blocks, 5.1

Max Attaninable Speed, Contd

Shortcomings of 1-T Op Amp
Not enough gain No level shift Single-ended- PSRR=0

Other Important Points:

Slew rate will degrade 2-5x Time constants of external switches will degrade speed Short-channel effects have major effect on channel mobility

Key Question: Can more complex op amps go faster?

PRG, Gain blocks, 6

Max Attainable Speed, Contd

What about multi-stage realizations? av gmro Cs CL

(gmro) CL

av

ft C S 2 C L

Cs Key Points:

Unity current gain at same freq for multistage as single stage If CL>>CS or Av>1, then multistage is useful
PRG, Gain blocks, 7

ft C S 2 2 C L

Improving Gain in Gain Block Ampliers

For 1-T amp, 2V a v
=

g r m o

gs

A V

eff ( V V ) 1 gs T dx d dV ds

2 ( 10V ) 40 0.5V

Approaches to the Gain Problem: 1. Cascoding

Bias Bias

av = [Va / (Vgs-VT)]2 Bias

Not really enough for 8 bit applications, at high speeds where channel lengths are short and Vgs-Vt has to be reasonably high.

Vout

Vin

PRG, Gain blocks, 8

Gain improvements, Contd

2. Series Feedback
Challenge is getting enough swing for low-voltage operation Works well in BICMOS to get Hi-Z PMOS current sources. Sackinger- JSC 2/90 Bult, ISSCC90

out

2 g r ) r m o o

Bias or Vin

PRG, Gain blocks, 9

Circuit Improvements, Contd

Unfolded Cascode Op Amp Bias Bias Vo+ VoBias Vi+ ViBias

Best raw speed at low closed-loop gains Limited Swing- no good for low voltage Level Shift in Input C-M caps Requires CMFB Input Preamp improves speed for Acl>1 or 2

PRG, Gain blocks, 10

Gain Block Approaches for Low Voltage (3V)

Design Issues:
Clock Swing/Transmission Gate Design Amplier Output Swing Degradation of Dynamic Range

Potential Solutions:
Low- VT devices in technology Bootstrapped clocks for xmission gates Two-stage op amps, Optimized Pole Split Compensation Three-Stage op amps, Nested Compensation Current-mode operation

PRG, Gain blocks, 11

Summary of Performance Limitations

Sample/Hold V S N Comparator
=

2 L 2

s i g n a l kT 2 L gd

(V

lnG

t Gain Block ao DAC

(V

2 L gd

1+ A

t di
PRG, Gain blocks, 12

m C +C gs L