ISSN: 2277 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July

y 2012

Design of High Speed Six Transistor Full Adder using a Novel Two Transistor XOR Gates
1

Pakkiraiah Chakali, 2Adilakshmi Siliveru, 3Neelima Koppala

AbstractIn modern era, the number of transistors are reduced in the circuit and ultra low power design have emerged as an active research topic due to its various applications. A full adder is one of the essential component
in digital circuit design, many improvements have been made to reduce the architecture of a full adder.The main aim of this paper is to reduce the power dissipation and area by redusing the number of transistors.By using general logic of pmos

transistor, the two transistor xor gate can be implemented. In this paper proposes the novel design of a 2T XOR gate. The design has been compared with earlier proposed 3T, 4T and 6T XOR gates and a significant improvement in silicon area and power-delay product has been obtained. An 8-T full adder has been designed using the proposed 2-T XOR gate and its performance has been obtained. the design is simulated in Mentor graphics tool . Keywords XOR gate, full adder, speed, area, power dissipation. I. INTRODUCTION Moores[17] law explains the requirement of the transistors for VLSI design it gives the empirical observation that transistor density and performance of integrated circuits, doubles every year, which was then revised to doubling every two years[18]. Unfortunately, such performance improvements have been accompanied by an increase in power[2] and energy dissipation of the systems. Higher power and energy dissipation in high performance systems require more expensive packaging and cooling technologies, increase cost, and decrease system reliability. Nonetheless, the level of on-chip integration and clock frequency will continue to grow with increasing performance demands, and the power and energy dissipation[13] of highperformance systems will be a critical design constraint.
Pakkiraiah Chakali, ECE Department, Sree Vidyanikethan Egineering College (Autonomou), JNTUA, Anantapur.( Pakkiraiah1988@yahoo.co.in). Tirupati, INDIA, Adilakshmi Siliveru, ECE Department, Sree Vidyanikethan Egineering College (Autonomou), JNTUA, Anantapur.(adilakshmi458@gmail.com). Tirupati, INDIA, Neelima Koppala, ECE Department, Sree Vidyanikethan Egineering College (Autonomou), JNTUA, Anantapur.Tirupati, INDIA, Mobile No.09966547895(koppalaneelima@gmail.com).

To reduce the power and area requirements of the computational complexities, the size of transistors are shrunk into the deep sub-micron region and predominantly handled by process engineering. Many design architecture and techniques have been developed to reduce power dissipation complementary logic, Pseudo NMOS[10], Dynamic CMOS[3], Clocked CMOS logic (C2MOS), CMOS Domino logic[1], Cascade voltage switch logic (CVSL), Modified Domino logic, Pass Transistor Logic (PTL)[3] have been proposed. Among the various building blocks in digital designs one of the most complex and power consuming is the Adders. Although several Adder designs[14] have been proposed to reduce power consumption[12], they are not suitable for operation in the sub-threshold region. In addition these designs require a large number of transistors, resulting in a large area, not suitable for small, low-priced systems. The power consumption of a CMOS circuit can be decomposed into two basic classes: static and dynamic. The steady state power dissipation[12] of a circuit is expressed by the following relation P
stat

=I V

stat DD

--------------(1)

The dynamic[3] component of power dissipation is due to its transient switching behavior of the CMOS device P = CV
2 DD

dyn

f ..(2)

This paper is organized as following. Section II reviews previous work and implementation of 2T XOR gate. Section III introduces implementation of full adder. Simulation and results are shown in Section IV, followed by the conclusion in Section V. II. DESIGN OF A TWO - TRANSISTOR XOR GATE The circuit performance improvement in through transistor count minimization.XOR gates form the fundamental building block of full adders. The early designs of XOR gates were based on either four transistors[4] or three transistors[5] that are

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ISSN: 2277 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012

conventionally used in most designs over the last decade.The previous designs of the four transistors and three transistors are shown in figure1.The proposed two transistor XOR gates can be designed using general logic implementation. The design[15] of a two transistor XOR gate is shown in figure 2. The circuite operation is as follows when A=0 and B=0 both the pmos transistors are ON and it will produce the output is low.when either one of the transistor is ON it Produces output as high, when A=1 and B=1 both the pmos transistors are OFF and it will produce the output is low.

Fig.2: Proposed Design of 2T -XOR.

III. DESIGN OF THE SIX-TRANSISTOR FULL ADDER Fig.1(a) Fig.1(b) The new design of full adders[7][11] which forms the basic building blocks of all digital VLSI circuits has been undergoing a considerable improvement, being motivated by three basic design goals, viz. minimizing the transistor count, minimizing the power consumption and increasing the speed. Conventional Static[3] CMOS full adder: The conventional CMOS logic gate full adder[16] is shown as Fig. 2 while the equation of a full adder are present as equation(1) - (4) [7]. Fig.1(c) Fig.1(d) x + y + Cin =2Cout + Sum -------------------(3) Cout =(y(x y)) + (Cin(x y)) -----------(4) Sum = x y Cin -----------------------(5)

Fig.1(e) Fig.1: Previous designs of 4-T and 3-T XOR gates.

The static CMOS Full adder is implemented by using 26 transistors.we can also minimize the number of transistors by using the CMOS Transmission gate and CMOS inverter.With this logic we reduce the number of transistors to 20.By using Pass transistor logic we can minimize the static power dissipation and number of transistors.Full adder is design with 14 transistors[9] by using Pass transistor logic.which leads the moderate power dissipation.The full adder design also implemented by using 10 transistors[6].

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ISSN: 2277 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012

Fig.3: Previous designs of 8T Full adder. Mainly the XOR and XNOR circuits are used in designing of full adder. In previous design the Full adder is designed by using eight transistors.which can dissipates more power compare to this work.In this paper the design of full adder using two transistors xor gates can ge implemented.The Six transistor Full adder is shown in Figure.4.
[8]

Fig.5: Wave forms of 2T-XOR gate.

Fig.6: Wave form of 6T-Full adder The comparison of the different XOR gates and Full adders are shown in table.1 according to their transistor count and power dissipation. Table.1: Comparison of existed full adders with proposed one in terms of transistor count and power dissipation Strucures IV. RESULTS AND DISCUSSION The exclusive-or gate and full adder are operated at 100 MHz signal frequency. In fact, in addition to normal transistors, circuits are tested in corner cases with fast and slow transistors and their combinations too. The difference in these stages is in consumption of power and falling and rising times which are caused due to the difference in NMOS and PMOS transistors power consumption and speed. After the simulation, the layout of circuit is drawn. By the post simulation result along with a few corrections have achieved in sizes that the circuit has an accurate operation. Simulation results are performed by using digital schematic design tool of Mentor graphics tool. The waveforms of proposed design as shown in figure 5 and 6 for XOR gate and full adder. XOR (Fig.1(a)) XOR(Fig.1(b)) XOR(Fig.1(c)) XOR (Fig.1(d)) XOR (Fig.1(e)) XOR (Fig.2) FULLADDER(Fig.3) FULLADDER(Fig.4) No Transistors 4 4 4 4 3 2 8 6 Power (w) 0.499 0.486 0.140 0.434 0.435 0.135 0.361 0.235

Fig.4: Proposed Design of 6T Full adder

V. CONCLUSION In this paper different CMOS logic design families has been reviewed and evaluated based on the performance metrics like area, power, delay and transistor count. But the previous techniques have the disadvantages of transistor count, delay and power dissipation. The current work proposes the design of an 6T full adder, which is by far the full adder with the lowest transistor count. In designing the proposed 6T full adder, a novel 2T XOR gate has also been proposed. The implementation of Full Adder has been presented

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ISSN: 2277 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012

and it can be extended to higher bit adders. The future research activities may include integration of the proposed full Adders in complex digital systems, combining sequential and combinational logic. REFERENCES [1] M. Hosseinzadeh, S.J. Jassbi, and Keivan Navi, A Novel Multiple Valued Logic OHRNS Modulo rn Adder Circuit, International Journal of Electronics, Circuits and Systems, Vol. 1, No. 4, Fall 2007, pp. 245-249. [2] D. Radhakrishnan, Low-voltage low-power CMOS full adder, in Proc.IEEE Circuits Devices Syst., vol. 148, Feb. 2001, pp. 19-24. [3] Y. Leblebici, S.M. Kang, CMOS Digital Integrated Circuits, Singapore: McGraw Hill, 2nd edition, 1999, Ch. 7. [4] J. Wang, S. Fang, and W. Feng, New efficient designs for XOR and XNOR functions on the transistor level, IEEE J.Solid-State Circuits, vol. 29, no. 7, Jul. 1994, pp. 780786. [5] H. T. Bui, A. K. Al-Sheraidah, and Y.Wang, New 4-transistor XOR and XNOR designs, in Proc. 2nd IEEE Asia Pacific Conf. ASICs, 2000, pp. 2528. [6] H.T. Bui, Y. Wang, Y. Jiang , Design and analysis of 10-transistor full adders using novel XORXNOR gates, in Proc. 5th Int. Conf. Signal Process., vol. 1, Aug. 2125, 2000, pp. 619622. [7] A. M. Shams, T. K. Darwish, and M. A. Bayoumi, Performance analysis of low-power 1-bit CMOS full adder cells, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 10, no. 1, Feb. 2002, pp. 0 29. [8] K.-H. Cheng and C.-S. Huang, The novel efficient design of XOR/XNOR function for adder applications, in Proc. IEEE Int. Conf. Elect., Circuits Syst., vol. 1, Sep. 58, 1999, pp. 2932. [9] M. Vesterbacka, A 14-transistor CMOS full adder with full voltage swing nodes, in Proc. IEEE Worksh. Signal Process. Syst., Oct. 2022,1999, pp. 713722. [10] R. Zimmermann and W. Fichtner, Low-power logic styles: CMOS versus pass-transistor logic, IEEE J. Solid-State Circuits, vol. 32, July 1997, pp.107990.

[11] N. Zhuang and H. Wu, A new design of the CMOS full adder, IEEE J.Solid-State Circuits, vol. 27, no. 5, May 1992, pp. 840844. [12] E. Abu-Shama and M. Bayoumi, A new cell for low power adders, in Proc. Int. Midwest Symp. Circuits Syst., 1995, pp. 10141017. [13] J.F. Lin, Y.T.Hwang, M.H. Sheu, C.C. Ho, A novel high speed and energy efficient 10 transistor full adder design, IEEE Trans. Circuits Syst. I, Regular papers, Vol. 54, No.5, May 2007, pp. 1050-1059. [14] Y. Tsividis, Mixed Analog-Digital VLSI Devices and Technology, Singapore: McGraw Hill, 1st edition, 1996. [15] M. Morris Mano, Digital Design, Prentice Hall of India, 2nd Edition, 2000. [16] S. Goel, M.A. Elgamel, M.A. Bayoumi, Y. Hanafy, Design Methodologies for high performance noise tolerant XOR-XNOR circuits, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 53, No. 4, 2006, pp. 867-878. [17] Moore, Gordon E. (1965). "Cramming more components onto integrated circuits" (PDF). Electronics Magazine. p. 4. Retrieved 2006-11-11. [18] G. Moore, BNo exponential is forever: But Fforever_ can be delayed! in Proc. IEEE Int. Solid-State Circuits Conf., 2003, Keynote address.

Mr. Pakkiraiah Chakali completed his B.Tech in Electronics and Communication Engineering from Sreenivasa Institute of Technology and mamagement studies, Chittoor, Andhra Pradesh, India in 2009. he is now pursuing his Master of Technology (M.Tech) in VLSI at Sree Vidyanikethan Engineering College , Tirupati, Andhra Pradesh, India. His interest includes Digital Design, ASIC Design, VLSI Testing. Ms. Adilakshmi Siliveru completed her B.Tech in Electronics and Communication Engineering from Kandula Obula Reddy Memorial College Of Engineering, Kadapa, Andhra Pradesh, India in 2011. She is now pursuing her Master of Technology (M.Tech) in VLSI at Sree Vidyanikethan Engineering College , Tirupati, Andhra Pradesh, India. Her interest includes Digital Design, VLSI Testing.

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ISSN: 2277 9043 International Journal of Advanced Research in Computer Science and Electronics Engineering Volume 1, Issue 5, July 2012

Ms. Neelima Koppala, M.Tech., is currently working as an Assistant Professor in ECE department of Sree Vidyanikethan Engineering College, Tirupati. She has completed M.Tech in VLSI Design, from Satyabhama University. Her research areas are RFIC Design, Digital Design, Low Power VLSI Design and VLSI Signal Processing.

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