C3K80 SP v1.0

C3K80 (PATA) Hard Disk Drive Specification
Hitachi Global Storage Technologies
Hard Disk Drive Specification
Hitachi C3K80
1.8 inch ATA/IDE hard disk drive
Models: HTC368080H8CE00 HTC368060H8CE00 HTC368040H5CE00 HTC368030H5CE00
Revision 1.0 22 Dec 2006
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C3K80 (PATA) Hard Disk Drive Specification 1st Edition: (Revision 1.0) (22 December 2006)
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Table of Contents
GENERAL .............................................................................................................................................. 9 1. INTRODUCTION ............................................................................................................................ 9 1.1. 1.2. 1.3. 1.4. 2. ABBREVIATIONS .............................................................................................................................. 9 REFERENCES................................................................................................................................. 11 GENERAL CAUTION ....................................................................................................................... 11 DRIVE HANDLING PRECAUTIONS ................................................................................................... 11
OUTLINE OF THE DRIVE ........................................................................................................... 12
PART 1 FUNCTIONAL SPECIFICATION .......................................................................................... 13 3. FIXED DISK SUBSYSTEM DESCRIPTION ................................................................................ 14 3.1. 3.2. 4. CONTROL ELECTRONICS ............................................................................................................... 14 HEAD DISK ASSEMBLY DATA.......................................................................................................... 14
FIXED DISK CHARACTERISTICS .............................................................................................. 15 4.1. FORMATTED CAPACITY BY MODEL NUMBER .................................................................................. 15 4.2. DATA SHEET .................................................................................................................................. 15 4.3. CYLINDER ALLOCATION ................................................................................................................ 16 4.4. PERFORMANCE CHARACTERISTICS ................................................................................................ 18 4.4.1. COMMAND OVERHEAD ............................................................................................................... 18 4.4.1.1 AVERAGE SEEK TIME (INCLUDING SETTLING) ........................................................................ 19 4.4.1.2 FULL STROKE SEEK ................................................................................................................ 19 4.4.1.3 SINGLE TRACK SEEK TIME (WITHOUT COMMAND OVERHEAD, INCLUDING SETTLING) ........... 20 4.4.1.4 AVERAGE LATENCY ................................................................................................................ 20 4.4.1.5 DRIVE READY TIME ................................................................................................................ 20 4.4.2. OPERATING MODES.................................................................................................................... 21 4.4.2.1 DESCRIPTION OF OPERATING MODES ..................................................................................... 21 4.4.2.2 OPERATING MODE AT POWER ON ........................................................................................... 21 4.4.2.3 ADAPTIVE POWER SAVE CONTROL .......................................................................................... 21
5.
DATA INTEGRITY ........................................................................................................................ 22 5.1. 5.2. 5.3. 5.4. 5.5. 5.6. 5.7. 5.7.1. 5.7.2. 5.7.3. 5.8. DATA LOSS ON POWER OFF ............................................................................................................ 22 WRITE CACHE ............................................................................................................................... 22 EQUIPMENT STATUS...................................................................................................................... 22 WRITE SAFETY ............................................................................................................................ 22 DATA BUFFER TEST ....................................................................................................................... 22 ERROR RECOVERY ......................................................................................................................... 23 AUTOMATIC REALLOCATION.......................................................................................................... 23 NONRECOVERED WRITE ERRORS ............................................................................................... 23 NONRECOVERABLE READ ERROR ............................................................................................... 23 RECOVERED READ ERRORS ........................................................................................................ 23 ECC .............................................................................................................................................. 24
6.
SPECIFICATION .......................................................................................................................... 25 6.1. ENVIRONMENT .............................................................................................................................. 25 6.1.1. TEMPERATURE AND HUMIDITY .................................................................................................. 25 6.1.2. CORROSION TEST ....................................................................................................................... 26 6.1.3. RADIATION NOISE ...................................................................................................................... 26 6.1.4. CONDUCTIVE NOISE .................................................................................................................. 26 6.1.5. MAGNETIC FIELDS ..................................................................................................................... 26 6.2. DC POWER REQUIREMENTS .......................................................................................................... 27 6.2.1. POWER CONSUMPTION EFFICIENCY ........................................................................................... 28 6.3. RELIABILITY.................................................................................................................................. 29 3/129
C3K80 (PATA) Hard Disk Drive Specification 6.3.1. DATA RELIABILITY ..................................................................................................................... 29 6.3.2. FAILURE PREDICTION (S.M.A.R.T.) .......................................................................................... 29 6.3.3. CABLE NOISE INTERFERENCE .................................................................................................... 29 6.3.4. SERVICE LIFE AND USAGE CONDITION ....................................................................................... 29 6.3.5. PREVENTIVE MAINTENANCE...................................................................................................... 29 6.3.6. LOAD/UNLOAD ........................................................................................................................... 29 6.3.7. EMERGENCY UNLOAD ................................................................................................................ 30 6.3.8. REQUIRED POWER-OFF SEQUENCE .......................................................................................... 30 6.3.9. POWER SWITCH DESIGN CONSIDERATIONS ................................................................................ 30 6.3.10. TEST CONSIDERATIONS .......................................................................................................... 30 6.4. MECHANICAL SPECIFICATIONS ..................................................................................................... 32 6.4.1. PHYSICAL DIMENSIONS AND WEIGHT ........................................................................................ 32 6.4.2. MECHANICAL DIMENSIONS........................................................................................................ 32 6.4.3. CONNECTOR AND JUMPER DESCRIPTION ................................................................................... 33 6.4.4. MOUNTING ORIENTATION.......................................................................................................... 33 6.4.5. LOAD/UNLOAD MECHANISM....................................................................................................... 33 6.5. VIBRATION AND SHOCK ................................................................................................................. 34 6.5.1. OPERATING VIBRATION ............................................................................................................. 34 6.5.2. RANDOM VIBRATION .................................................................................................................. 34 6.5.3. SWEPT SINE VIBRATION ............................................................................................................. 34 6.5.4. NONOPERATING VIBRATION ...................................................................................................... 35 6.5.5. RANDOM VIBRATION .................................................................................................................. 35 6.5.6. SWEPT SINE VIBRATION ............................................................................................................. 35 6.5.7. OPERATING SHOCK .................................................................................................................... 35 6.5.8. NONOPERATING SHOCK ............................................................................................................. 36 6.6. ACOUSTICS .................................................................................................................................... 37 6.6.1. SOUND POWER LEVEL ................................................................................................................ 37 6.6.2. DISCRETE TONE PENALTY ......................................................................................................... 38 6.7. IDENTIFICATION LABELS ............................................................................................................... 39 6.8. ELECTROMAGNETIC COMPATIBILITY ............................................................................................. 39 6.8.1. CE MARK .................................................................................................................................. 39 6.8.2. C-TICK MARK ............................................................................................................................ 39 6.8.3. BSMI MARK .............................................................................................................................. 39 6.8.4. MIC MARK ................................................................................................................................ 39 6.9. SAFETY.......................................................................................................................................... 40 6.9.1. UL AND CSA APPROVAL ........................................................................................................... 40 6.9.2. IEC COMPLIANCE ...................................................................................................................... 40 6.9.3. GERMAN SAFETY MARK ............................................................................................................ 40 6.9.4. FLAMMABILITY .......................................................................................................................... 40 6.9.5. SECONDARY CIRCUIT PROTECTION ............................................................................................ 40 6.10. PACKAGING ............................................................................................................................... 40 6.11. SUBSTANCE RESTRICTION REQUIREMENTS ............................................................................... 40 7. ELECTRICAL INTERFACE SPECIFICATIONS ......................................................................... 41 7.1. 7.2. 7.3. 7.4. 7.5. 7.6. 7.7. 7.8. 7.9. 7.9.1. 7.9.2. 7.9.3. 7.9.4. 7.9.5. 7.9.6. CABLING ....................................................................................................................................... 41 INTERFACE CONNECTOR ............................................................................................................... 41 SIGNAL DEFINITIONS .................................................................................................................... 42 SIGNAL DESCRIPTIONS .................................................................................................................. 43 INTERFACE LOGIC SIGNAL LEVELS ................................................................................................ 45 RESET TIMINGS ............................................................................................................................. 45 PIO TIMINGS ................................................................................................................................. 46 MULTIWORD DMA TIMINGS ......................................................................................................... 47 ULTRA DMA TIMINGS ................................................................................................................... 48 INITIATING READ DMA............................................................................................................. 48 HOST PAUSING READ DMA ...................................................................................................... 49 HOST TERMINATING READ DMA .............................................................................................. 50 DEVICE TERMINATING READ DMA ........................................................................................... 51 INITIATING WRITE DMA ........................................................................................................... 52 DEVICE PAUSING WRITE DMA ................................................................................................. 53 4/129
C3K80 (PATA) Hard Disk Drive Specification 7.9.7. 7.9.8. 7.10. 7.10.1. 7.11. DEVICE TERMINATING WRITE DMA ......................................................................................... 54 HOST TERMINATING WRITE DMA ............................................................................................ 55 DRIVE ADDRESS SETTING .......................................................................................................... 56 DRIVE DEFAULT ADDRESS SETTING ....................................................................................... 56 ADDRESSING OF HDD REGISTERS ............................................................................................. 57
PART 2 INTERFACE SPECIFICATION ............................................................................................. 58 8. PARALLEL ATA COMMAND PROTOCOL .................................................................................. 59 8.1. 8.2. 8.3. 8.4. 9. PIO DATA IN COMMANDS ............................................................................................................. 59 PIO DATA OUT COMMANDS.......................................................................................................... 61 NON-DATA COMMANDS................................................................................................................. 62 DMA DATA TRANSFER COMMANDS .............................................................................................. 63
ATA REGISTERS .......................................................................................................................... 64 9.1. ATA REGISTERS ADDRESS............................................................................................................ 64 9.1.1. ALTERNATE STATUS REGISTER ................................................................................................. 64 9.1.2. COMMAND REGISTER ................................................................................................................ 64 9.1.3. DATA REGISTER ........................................................................................................................ 64 9.1.4. DEVICE CONTROL REGISTER ..................................................................................................... 65 9.1.5. DEVICE REGISTER ..................................................................................................................... 65 9.1.6. ERROR REGISTER ...................................................................................................................... 66 9.1.7. LBA HIGH REGISTER ................................................................................................................ 66 9.1.8. LBA MID REGISTER .................................................................................................................. 66 9.1.9. LBA LOW REGISTER ................................................................................................................. 66 9.1.10. STATUS REGISTER ................................................................................................................. 67
10.
GENERAL OPERATIONAL DESCRIPTIONS.......................................................................... 68 RESET RESPONSE ...................................................................................................................... 68 REGISTER INITIALIZATION ..................................................................................................... 69 POWER OFF CONSIDERATIONS................................................................................................... 70 REQUIRED POWER OFF SEQUENCE ........................................................................................ 70 EMERGENCY UNLOAD............................................................................................................ 70 SECTOR ADDRESSING MODE ..................................................................................................... 71 LOGICAL CHS ADDRESSING MODE ....................................................................................... 71 LBA ADDRESSING MODE (28 BIT ADDRESS).......................................................................... 71 LBA ADDRESSING MODE (48 BIT ADDRESS).......................................................................... 71 POWER MANAGEMENT FEATURE .............................................................................................. 72 POWER MODE ........................................................................................................................ 72 POWER MANAGEMENT COMMANDS ....................................................................................... 72 STANDBY COMMAND COMPLETION TIMING ........................................................................... 72 STANDBY TIMER .................................................................................................................... 72 STATUS .................................................................................................................................. 72 INTERFACE CAPABILITY FOR POWER MODES ........................................................................ 73 INITIAL POWER MODE AT POWER ON .................................................................................... 73 ADVANCED POWER MANAGEMENT FEATURE ............................................................................ 73 PERFORMANCE IDLE MODE ................................................................................................... 73 ACTIVE IDLE MODE ............................................................................................................... 73 LOW POWER IDLE MODE ....................................................................................................... 73 TRANSITION TIME .................................................................................................................. 74 SMART FUNCTION ................................................................................................................... 75 ATTRIBUTE VALUES ............................................................................................................... 75 ATTRIBUTE THRESHOLDS ...................................................................................................... 75 THRESHOLD EXCEEDED CONDITION ..................................................................................... 75 SMART COMMANDS ............................................................................................................. 75 SMART OPERATION WITH POWER MANAGEMENT................................................................ 75 WRITE CACHE FUNCTION.......................................................................................................... 76 REASSIGN FUNCTION ................................................................................................................ 77 AUTO REASSIGN FUNCTION ................................................................................................... 77 5/129
10.1. 10.1.1. 10.2. 10.2.1. 10.2.2. 10.3. 10.3.1. 10.3.2. 10.3.3. 10.4. 10.4.1. 10.4.2. 10.4.3. 10.4.4. 10.4.5. 10.4.6. 10.4.7. 10.5. 10.5.1. 10.5.2. 10.5.3. 10.5.4. 10.6. 10.6.1. 10.6.2. 10.6.3. 10.6.4. 10.6.5. 10.7. 10.8. 10.8.1.
C3K80 (PATA) Hard Disk Drive Specification 11. COMMAND DESCRIPTIONS ................................................................................................... 78 CHECK POWER MODE(E5H/98H)............................................................................................... 78 EXECUTE DEVICE DIAGNOSTIC (90H) ....................................................................................... 79 FLUSH CACHE (E7H) ................................................................................................................. 80 FLUSH CACHE EXT (EAH)........................................................................................................ 81 IDENTIFY DEVICE (ECH) ........................................................................................................... 82 IDLE (E3H/97H)......................................................................................................................... 90 IDLE IMMEDIATE (E1H/95H) ..................................................................................................... 91 IDLE IMMEDIATE WITH UNLOAD (E1H) ..................................................................................... 92 INITIALIZE DEVICE PARAMETERS (91H) .................................................................................... 93 READ BUFFER (E4H) ................................................................................................................. 94 READ DMA (C8H) ..................................................................................................................... 95 READ DMA EXT (25H) ............................................................................................................. 96 READ LONG (22H) ..................................................................................................................... 97 READ MULTIPLE (C4H) ............................................................................................................. 98 READ MULTIPLE EXT (29H) ..................................................................................................... 99 READ SECTORS (20H) .............................................................................................................. 100 READ SECTORS EXT (24H)...................................................................................................... 101 READ VERIFY SECTORS (40H) ................................................................................................. 102 READ VERIFY SECTORS EXT (42H)......................................................................................... 103 RECALIBRATE (1XH)................................................................................................................ 104 SEEK (7XH) ............................................................................................................................. 105 SENSE CONDITION (F0H:VENDOR UNIQUE)............................................................................ 106 SENSE DRIVE TEMPERATURE (FAH:VENDOR UNIQUE) .......................................................... 107 SET FEATURES (EFH).............................................................................................................. 108 SET MULTIPLE MODE (C6H) ................................................................................................... 110 SLEEP (E6H/99H) .................................................................................................................... 111 SMART FUNCTION SET (B0H)................................................................................................ 112 STANDBY (E2H/96H) ............................................................................................................... 116 STANDBY IMMEDIATE (E0H/94H) ............................................................................................ 117 WRITE BUFFER (E8H) ............................................................................................................. 118 WRITE DMA (CAH)................................................................................................................. 119 WRITE DMA EXT (35H) ......................................................................................................... 120 WRITE LONG (32H).................................................................................................................. 121 WRITE MULTIPLE (C5H).......................................................................................................... 122 WRITE MULTIPLE EXT (39H).................................................................................................. 123 WRITE SECTORS (30H) ............................................................................................................ 124 WRITE SECTORS EXT (34H).................................................................................................... 125 WRITE VERIFY (3CH, VENDOR UNIQUE)................................................................................. 126 ERROR POSTING ...................................................................................................................... 127 11.1. 11.2. 11.3. 11.4. 11.5. 11.6. 11.7. 11.8. 11.9. 11.10. 11.11. 11.12. 11.13. 11.14. 11.15. 11.16. 11.17. 11.18. 11.19. 11.20. 11.21. 11.22. 11.23. 11.24. 11.25. 11.26. 11.27. 11.28. 11.29. 11.30. 11.31. 11.32. 11.33. 11.34. 11.35. 11.36. 11.37. 11.38. 11.39. 12.
TIMINGS...................................................................................................................................128
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List of Figures
Figure 1: Limits of temperature and humidity .................................................................................................... 26 Figure 2: Mounting Area locations ..................................................................................................................... 32 Figure 3: Interface connector location ................................................................................................................ 41
List of Tables
Table 1: Formatted capacity by model number Table 2: Data sheet Table 3: Cylinder allocation (40GB/p format) Table 4: Cylinder allocation (30GB/p format) Table 5: Performance characteristics Table 6: Mechanical positioning performance Table 7: Full stroke seek time Table 8: Single track seek time Table 9: Latency time Table 10: Drive ready time Table 11: Environmental condition Table 12: Magnetic flux density limits Table 13: DC Power requirements Table 14: Power consumption efficiency Table 15: Physical dimensions and weight Table 16: Random vibration PSD profile breakpoints (operating) Table 17: Swept sine vibration Table 18: Random Vibration PSD Profile Breakpoints (nonoperating) Table 19: Operating shock Table 20: Nonoperating shock Table 21: Weighted sound power Table 22: Connector pin assignment Table 23: Special signal definitions for Ultra DMA Table 24: Signal List Table 25: System reset timings Table 26: PIO cycle timings Table 27:Multiword DMA cycle timings Table 28: Ultra DMA cycle timings (Initiating Read) Table 29: Ultra DMA cycle timings (Host Pausing Read) Table 30: Ultra DMA cycle timings (Host Terminating Read) Table 31: Ultra DMA cycle timings (Device Terminating Read) Table 32: Ultra DMA cycle timings (Initiating Write) Table 33: Ultra DMA cycle timings (Device Pausing Write) Table 34: Ultra DMA cycle timings (Device Terminating Write) Table 35: Ultra DMA cycle timings (Host Terminating Write) Table 36: I/O address map Table 37 ATA Registers Address Table 38 Alternate Status Register Table 39 Device Control Register Table 40 Device Register Table 41 Error Register Table 42 Status Register Table 43 Reset Types Table 44 Reset Response Table 45 Default Register Values Table 46 Diagnostic Codes Table 10-47 Power Conditions Table 48 Check Power Mode Command Table 49 Execute Device Diagnostic command Table 50 Flush Cache Command Table 51 Flush Cache EXT Command 7/129 15 15 16 17 18 19 19 20 20 20 25 26 27 28 32 34 34 35 35 36 37 42 42 43 45 46 47 48 49 50 51 52 53 54 55 57 64 64 65 65 66 67 68 68 69 69 73 78 79 80 81
C3K80 (PATA) Hard Disk Drive Specification Table 52 Identify Device Command Table 53 Identify Device Data Structure Table 54 Identify Device Data Structure Table 55 Idle Command Table 56 Idle Immediate Command Table 57 Idle Immediate Command with Unload Table 58 Initialize Device Parameters Command Table 59 Read Buffer Command Table 60 Read DMA Command Table 61 Read DMA EXT Command Table 62 Read Long Command Table 63 Read Multiple Command Table 64 Read Multiple EXT Command Table 65 Read Sectors Command Table 66 Read Sectors EXT Command Table 67 Read Verify Sectors Command Table 68 Read Verify Sectors EXT Command Table 69 Recalibrate Command Table 70 Seek Command Table 71 Sense Condition Command Table 72 Sense Drive Temperature Command Table 73 Set Features Command Table 74 Supported Features Table 75 Set Multiple Mode Command Table 76 Sleep Command Table 77 SMART Function Set Command Table 78 SMART Subcommands Table 79 SMART Device Attribute Data Structure Table 80 SMART Individual Attribute Data Structure Table 81 SMART Attribute ID Table 82 Standby Command Table 83 Standby Immediate Command Table 84 Write Buffer Command Table 85 Write DMA Command Table 86 Write DMA EXT Command Table 87 Write Long Command Table 88 Write Multiple Command Table 89 Write Multiple EXT Command Table 90 Write Sectors Command Table 91 Write Sectors EXT Command Table 92 Error Reporting Table 93 Timeout Values
82 83 84 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 108 110 111 112 113 114 115 115 116 117 118 119 120 121 122 123 124 125 127 128
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General 1. Introduction
This document describes the specifications of the Hitachi C3K80, a 1.8-inch hard disk drive with ATA/IDE interface: Drive name Model Number Capacity (GB) Height (mm) Rotation speed (rpm) C3K80-80 HTC368080H8CE00 80 8.0 3600 C3K80-60 C3K80-40 C3K80-30 HTC368060H8CE00 HTC368040H5CE00 HTC368030H5CE00 60 40 30 8.0 5.0 5.0 3600 3600 3600
Part 1 of this document beginning on page 13 defines the hardware functional specification. Part 2 of this document is the Interface specification.
1.1.
Abbreviation 32 KB 64 KB " A AC AT ATA Bels BIOS C CSA C-UL Cyl DC DMA ECC EEC EMC ERP ESD FCC G Gb GB GND h HDD Hz I I/O ISO KB Kbit/mm Kbit/sq-mm KHz
Abbreviations
Meaning 32 x 1024 bytes 64 x 1024 bytes inch amp alternating current Advanced Technology Advanced Technology Attachment unit of sound power Basic Input/Output System degrees Celsius Canadian Standards Association Canadian-Underwriters Laboratory cylinder direct current Direct Memory Access error correction code European Economic Community electromagnetic compatibility Error Recovery Procedure electrostatic discharge Federal Communications Commission gravity, a unit of force 1 000 000 000 bits 1 000 000 000 bytes ground hexadecimal hard disk drive hertz Input Input/Output International Standards Organization 1,000 bytes 1,000 bits per mm 1000 bits per square mm kilohertz 9/129
LBA Lw m max. or Max. MB Mbps Mb/sec MB/sec MHz mm ms ns us, s Nm No. or # oct/min O OD PIO POH P/N p-p PSD RH % RH RMS RPM RST R/W sec Sect/Trk SELV S.M.A.R.T Trk. TTL UL V W
C3K80 (PATA) Hard Disk Drive Specification logical block addressing unit of A-weighted sound power meter maximum 1,000,000 bytes 1,000,000 Bit per second 1,000,000 Bit per second 1,000,000 bytes per second megahertz millimeter millisecond nanosecond microsecond Newton meter number oscillations per minute Output Open Drain Programmed Input/Output
Programmed Input/Output
power on hours part number peak-to-peak power spectral density relative humidity per cent relative humidity root mean square revolutions per minute reset read/write second sectors per track A safety extra low voltage Self-monitoring, analysis, and reporting technology track transistor-transistor logic Underwriters Laboratory volt watt
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1.2. 1.3.
References
ATA/ATAPI-7 (Revision 4b)
General caution
Do not apply force to the top cover (See figure below). Do not touch the interface connector pins or the surface of the printed circuit board. The drive can be damaged by shock or ESD (Electric Static Discharge). Any damages incurred to the drive after removing it from the shipping package and the ESD protective bag are the responsibility of the user
1.4.
Drive handling precautions
Do not press on the drive cover during handling.
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2. Outline of the drive

1.8-inch, 8.0mm height (2-disk model) and 5.0mm height (1-disk model) Perpendicular Recording Formatted capacity : 80 and 60GB for 2-disk model, 40 and 30GB for 1-disk model 512 bytes/sector AT Interface (Enhanced IDE) conforming to ATA-7 Data Transfer Rate (Host-Device) -16.6 MB/sec: PIO mode-4/Multiword DMA mode-2 - 33.3 MB/sec: Ultra DMA mode-2 (Device-Buffer) - 288 Mbps(80 and 40GB)
Integrated controller including channel No-ID recording format MEEPRML 60/62 code with 1 bit parity Multi zone recording Enhanced ECC On-The-Fly 128kB Segmented Buffer with write cache Average seek time 14 ms for read Embedded Sector Servo Rotary Actuator Load/Unload Mechanism Auto Read Reassign/Auto Write Reassign FDB(Fluid Dynamics Bearing) Motor Low Power Consumption: 0.23W at Idle mode, 0.08W at Standby mode
Advanced Power Management (APM)
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Part 1 Functional Specification
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3. Fixed disk subsystem description

3.1.

Control Electronics
AT Interface Protocol Embedded Sector Servo No-ID (TM) formatting Multizone recording Code: 60/62 with 1 bit parity System ECC Enhanced Adaptive Battery Life Extender
The control electronics works with the following functions:
3.2.

Head disk assembly data

Femto Slider Perpendicular recording disk and write head GMR read head Load/unload mechanism Mechanical latch
The following technologies are used in the drive:
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4. Fixed disk characteristics

4.1. Formatted capacity by model number
HTC368080H8CE00 512 436-873 4 2 16 63 16,383 156,301,488 80,026,361,856 HTC368060H8CE00 512 336-672 4 2 16 63 16,383 117,210,240 60,011,642,880
Table 1: Formatted capacity by model number

Description Physical Layout Bytes per Sector Sectors per Track Number of Heads Number of Disks Logical Layout Number of Heads Number of Sectors/ Track Number of Cylinders Number of Sectors Total Logical Data Bytes
Description Physical Layout Bytes per Sector Sectors per Track Number of Heads Number of Disks Logical Layout Number of Heads Number of Sectors/ Track Number of Cylinders Number of Sectors Total Logical Data Bytes
HTC368040H5CE00 512 436-873 2 1 16 63 16,383 78,140,160 40,007,761,920
HTC368030H5CE00 512 336-672 2 1 16 63 16,383 58,605,120 30,005,821,440
4.2.
Data sheet
80GB 3600 288 33 38.3 973 5.24 133 201 130 24 60GB 3600 219 33 31.3 795 5.08 129 159 103 24 40GB 3600 288 33 38.3 973 5.24 133 201 130 24 30GB 3600 219 33 31.3 795 5.08 129 159 103 24
Table 2: Data sheet
Rotational Speed (RPM) Data transfer rates (Max) (buffer to/from media) (Mbps) Data transfer rates (Mbyte/sec) ULTRA DMA 33 Recording density (Kbit/mm) (Max) (KBPI) (Max) Track density (Ktrack/mm) (KTPI) Areal density (Mbit/sq-mm.- Max) (Gbit/sq-inch - Max) Number of zones
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4.3.
Cylinder allocation
Adaptive formats are adopted. Typical format is described below.
Table 3: Cylinder allocation (40GB/p format)

40GB/p format Cylinder 0 593 594 1385 1386 2177 2178 7622 7623 - 10592 10593 - 12572 12573 - 15047 15048 - 16928 16929 - 21383 21384 - 25541 25542 - 27521 27522 - 29699 29700 - 34352 34353 - 35243 35244 - 36728 36729 - 39302 39303 - 40391 40392 - 43064 43065 - 44153 44154 - 46034 46035 - 47321 47322 - 53063 53064 - 55241 55242 - 59399
Zone 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
No. of Sectors/Trk 873 868 868 840 806 798 784 772 739 728 714 705 672 651 638 616 604 576 571 560 546 504 470 436
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Table 4: Cylinder allocation (30GB/p format)

30GB/p format Cylinder 0 1631 1632 3263 3264 5183 5184 6911 6912 - 12671 12672 - 14591 14592 - 16991 16992 - 18431 18432 - 19679 19680 - 21023 21024 - 24671 24672 - 28799 28800 - 30335 30336 - 31487 31488 - 32927 32928 - 40031 40032 - 42143 42144 - 43391 43392 - 44639 44640 - 45695 45696 - 48959 48960 - 53375 53376 - 54815 54816 - 57599
Zone 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
No. of Sectors/Trk 672 672 651 651 616 616 616 616 604 604 576 560 546 546 532 504 470 456 448 436 408 378 364 336
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4.4.
Performance characteristics
Drive performance is characterized by the following parameters: Command Overhead Mechanical Positioning Seek Time Latency Data Transfer Speed Buffering Operation (Look ahead/Write Cache) Note: All the above parameters contribute to drive performance. There are other parameters which contribute to the performance of the actual system. This specification defines the essential characteristics of the drive. This specification does not include the system throughput as this is dependent upon the system and the application. The following table gives a typical value for each parameter. The detailed descriptions are found in section 5.0.
Table 5: Performance characteristics

Function Average Random Seek Time - Read (ms) Average Random Seek Time - Write (ms) Rotational Speed (RPM) Power-on-to-ready (sec) Command overhead (ms) Disk-buffer data transfer (Mb/s) Buffer-host data transfer (MB/s)
14 15 3600 3.0 1.0 288 max 33
4.4.1.
Command overhead
Command overhead time is defined as the interval from the time that a drive receives a command to the time that the actuator starts its motion.
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4.4.1.1 Average seek time (including settling)

Table 6: Mechanical positioning performance
Command Type Read Write Typical (ms) 14 15 Max. (ms) 16 17
Typical and Max. are defined throughout the performance specification as follows: Average of the drive population tested at nominal environmental and voltage conditions. Maximum value measured on any one drive over the full range of the environmental and voltage conditions. (See section 6.1, "Environment" on page 25 and section 6.2, "DC power requirements" on page 27) The seek time is measured from the start of motion of the actuator to the start of a reliable read or write operation. A reliable read or write operation implies that error correction/recovery is not employed to correct arrival problems. The Average Seek Time is measured as the weighted average of all possible seek combinations.
max. n=1
Typical Max.
(max. + 1 n)(Tnin + Tnout) Weighted Average = (max. + 1)(max) Where: max. = maximum seek length n = seek length (1-to-max.) Tnin = inward measured seek time for an n-track seek Tnout = outward measured seek time for an n-track seek
4.4.1.2 Full stroke seek

Table 7: Full stroke seek time
Command Type Read Write Typical (ms) 24.0 25.0 Max. (ms) 28.0 29.0
Full stroke seek time in milliseconds is the average time of 1000 full stroke seeks.
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4.4.1.3 Single track seek time (without command overhead, including settling)
Table 8: Single track seek time
Command Type Read Write Typical (ms) 1.0 1.1 Maximum (ms) 3.0 3.0
Single track seek is measured as the average of one (1) single track seek from every track in both directions (inward and outward).
4.4.1.4 Average latency

Table 9: Latency time
Rotational Speed (RPM) 3600 Time for one revolution (ms) 16.7 Average Latency (ms) 8.3
4.4.1.5 Drive ready time

Table 10: Drive ready time
Condition Power On To Ready Typical (sec) 3.0 Max. (sec) 10.0
The condition in which the drive is able to perform a media access command (for exampleread, write) immediately. Power On To Ready This includes the time required for the internal self diagnostics.
Ready
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4.4.2.
Operating modes
4.4.2.1 Description of operating modes

Operating mode Spin-Up Active Read Performance idle Active idle Description Start up time period from spindle stop or power down. Drive is active in seek, read or write operation. Read operation mode The device is capable of responding immediately to media access requests. All electronic components remain powered and the full frequency servo remains operational. The device is capable of responding immediately to media access requests. Some circuitryincluding servo system and R/W electronicsis in power saving mode. The head is parked near the mid-diameter the disk without servoing. A device in Active idle mode may take longer to complete the execution of a command because it must activate that circuitry. The head is unloaded onto the ramp position. The spindle motor is rotating at full speed. The device interface is capable of accepting commands. The spindle motor is stopped. All circuitry but the host interface is in power saving mode. The execution of commands is delayed until the spindle becomes ready. The device interface is capable of accepting commands. The spindle motor is stopped. All circuitry but the host interface is in power saving mode. The execution of commands is delayed until the spindle becomes ready.
Low power idle Standby Sleep
4.4.2.2 Operating mode at power on

The device enters the Active mode at power on as an initial state, then moves to the Low power idel mode or the Standby mode depending on the power management setting if a host command is not received.
4.4.2.3 Adaptive power save control

The transient timing from Performance Idle mode to Active Idle mode and Active Idle mode to Low Power Idle mode is controlled adaptively according to the access pattern of the host system. The transient timing from Low Power Idle mode to Standby mode is also controlled adaptively, if it is allowed by Set Features Enable Advanced Power Management subcommand.
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5. Data integrity
5.1. Data loss on power off
Power off during any operations except for write operation will not cause any data loss. Power off during a write operation causes the loss of data received by the drive but not yet written onto the disk media. There is a possibility that power off during a write operation might make a maximum of 1 sector of data unreadable. This state can be recovered by a rewrite operation.
5.2.
Write Cache
When write cache is enabled, there is a possibility that the write command completes before the actual disk write operation finishes. This means that there is a possibility that a power off event may occur even after a full write command finishes. This means that it is possible that even after a write command completion, a power off might cause the loss of the data in which the drive has received but not yet written onto the disk. In order to prevent data loss, confirm the completion of the actual write operation prior to the power off by issuing the Standby Immediate or Sleep command and confirming its completion. The default state of the write cache at power-on is "ON."
5.3.
Equipment status
The equipment status is available to the host system any time the drive is not ready to read, write, or seek. This status normally exists at the power-on time and will be maintained until the following conditions are satisfied: The access recalibration/tuning is complete. The spindle speed meets the requirements for reliable operation. The self-check of the drive is complete.
The appropriate error status is made available to the host system if any of the following conditions occur after the drive has become ready: The spindle speed lies outside the requirements for reliable operation. The occurrence of a Write Fault condition.
5.4.
WRITE safety
The drive ensures that the data is written into the disk media properly. The following conditions are monitored during a write operation. When one of these conditions exceeds the criteria, the write operation is terminated and the automatic retry sequence is invoked. Head off track External shock Low supply voltage Spindle speed out of tolerance Head open/short
5.5.
Data buffer test

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The data buffer is tested at Power-on-reset. The test consists of a write/read "00"x and "ff"x pattern on each buffer position.
5.6.
Error recovery
Errors occurring on the drive are handled by the error recovery procedure. Errors that are uncorrectable after application of the error recovery procedures are reported to the host system as nonrecoverable errors.
5.7.
Automatic reallocation
The sectors that show some errors may be reallocated automatically when specific conditions are met. The drive does not report any auto reallocation to the host system. The conditions for auto reallocation are described below.
5.7.1.
Nonrecovered write errors
When a write operation cannot be completed after the Error Recovery Procedure (ERP) is fully carried out, the sectors are reallocated to the spare location. An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed.
5.7.2.
Nonrecoverable read error
When a read operation fails after ERP is fully carried out, a hard error is reported to the host system. This location is registered internally as a candidate for the reallocation. When a registered location is specified as a target of a write operation, a sequence of media verification is performed automatically. When the result of this verification meets the required criteria, this sector is reallocated.
5.7.3.
Recovered read errors
When a read operation for a sector fails and is recovered at the specific ERP step, the sector is reallocated automatically. A media verification sequence may be run prior to the reallocation according to the predefined conditions.
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5.8.
ECC
The 10 bit 40 symbol non interleaved ECC processor provides user data verification and correction capability. The first 6 symbol of ECC are 4 check symbols for user data and the 2-symbol system ECC. The other 34 symbols are Read Solomon ECC. Hardware logic corrects up to 16 symbols (20 bytes) errors on the fly. 2 symbol System ECC is generated when HDC receives user data from HOST, and can correct up to 1 symbol(10bit) errors on-the-fly when one transfers to HOST.
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6. Specification
6.1.
6.1.1.
Environment
Temperature and humidity
Table 11: Environmental condition

Operating conditions 5 to 60C (See note below) Temperature 5 to 90% noncondensing Relative humidity 29.4C noncondensing Maximum wet bulb temperature 20C/hour Maximum temperature gradient 300 to 3048 m (10,000 ft) Altitude Nonoperating conditions 40 to 70C Temperature 5 to 95% noncondensing Relative humidity 40C noncondensing Maximum wet bulb temperature 20C/hour Maximum temperature gradient 300 to 12,192 m (40,000 ft) Altitude The system is responsible for providing sufficient air movement to maintain surface temperatures below 65C at the defined measurement point of top cover. Measurement point
The maximum storage period in the shipping package is one year.
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Specification ( Environment )
100
41'C/95%
90
31'C/90%
Relative Humidity ( % )
80 70 60 50 40 30 20 10 0 -50 -40 -30 -20 -10 0 10 20 30 40

60'C/10%
WetBulb 40'C
Non Operating
WetBulb 29.4'C
Operating
70'C/17%
50
60
70
80
Temperature ( degC )
Figure 1: Limits of temperature and humidity
6.1.2. Corrosion test

The hard disk drive must be functional and show no signs of corrosion after being exposed to a temperature humidity stress of 50C/90%RH (relative humidity) for one week followed by a temperature and humidity drop to 25'C/40%RH in 2 hours.
6.1.3.
Radiation noise
The disk drive shall work without degradation of the soft error rate under the following magnetic flux density limits at the enclosure surface.
Table 12: Magnetic flux density limits

Frequency (KHz) 0 60 61 100 101 200 201 400 Limits (uT RMS) 500 250 100 50
6.1.4.
Conductive noise
The drive works without degradation of the soft error rate with an AC current of up to 45mA(p-p) in the frequency rage from DC to 20 MHz via a 50 Ohm resister.
6.1.5.
Magnetic fields
The disk drive will withstand radiation and conductive noise within the limits.
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6.2.
DC power requirements
Connection to the product should be made in a safety extra low voltage (SELV) circuits. The voltage specifications are applied at the power connector of the drive.
Table 13: DC Power requirements

Item Nominal supply Supply voltage Power supply ripple (0 20 1 MHz) 2 Tolerance Supply rise time Operational Mode Performance Idle average Active Idle average Low Power Idle average 4 Read average Write average 5 Seek average Standby Sleep 6 Startup (maximum) Average from standby to ready Footnotes: 1. 2. 3. 4. 5. 6. 7.
3
Requirements +3.3 Volt dc +3.3 Volt -15%/+5% 100 mV p-p max. 5% 100us 200 ms Watts (RMS Typical) 0.70 0.35 0.23 0.80 0.80 1.1 0.08 0.08 1.3 0.75
7
The maximum fixed disk ripple is measured at the 3.3 volt input of the drive. The disk drive shall not incur damage for an over voltage condition of +25% (maximum duration of 20 ms) on the 3.3 volt nominal supply. The idle current is specified at an inner track. The read/write current is specified based on three operations of 63 sector read/write per 100 ms. The seek average current is specified based on three operations per 100 ms. Maximum of 10ms averaged peak current in any operation mode. Typical mean average of the drive population tested at nominal environmental and voltage conditions.
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6.2.1.
Capacity
Power consumption efficiency

80GB 0.003 60GB 0.004 40GB 0.006 30GB 0.008
Table 14: Power consumption efficiency
Power Consumption Efficiency (Watts/GB)
Note: Power consumption efficiency is calculated as Power Consumption of Low Power Idle Watt/ Capacity (GB).
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6.3.
6.3.1.

Reliability
Data reliability
Probability of not recovering data is 1 in 10 bits read ECC implementation
13
On-the-fly correction performed as a part of read channel function recovers up to 16 symbols of error in 1 sector (1 symbol is 10 bits).
6.3.2. 6.3.3.
Failure prediction (S.M.A.R.T.) Cable noise interference
The drive supports Self-monitoring, analysis and reporting technology (S.M.A.R.T.) function.
The common mode noise or voltage level difference between the system frame and power cable ground or AT interface cable ground should be in the allowable level specified in the power requirement section.
6.3.4.
Service life and usage condition
The drive is designed to be used under the following conditions: The drive should be operated within specifications of shock, vibration, temperature, humidity, altitude, and magnetic field. The drive should be protected from ESD. Force should not be applied to the cover of the drive. The specified power requirements of the drive should be satisfied. The drive frame should be grounded electrically to the system. The interface requirements of the drive should satisfy ATA-7. The power-off sequence of the drive should comply with the sequence.35 6.4.6.2,"Required power-off
Service life of the drive is approximately 5 years or 1200 power on hours, whichever comes first, under the following assumptions: Less than 333 power on hours per month. Seeking/Writing/Reading operation is less than 20% of power on hours. This does not represent any warranty or warranty period. covered by the purchase agreement. Applicable warranty and warranty period are
6.3.5.
None.
Preventive maintenance
6.3.6.
Load/unload
The product supports a minimum of 300,000 normal load/unloads. Load/unload is a functional mechanism of the hard disk drive. It is controlled by the drive micro code. Specifically, unloading of the heads is invoked by the following commands: Hard reset 29/129
C3K80 (PATA) Hard Disk Drive Specification Standby Standby immediate Sleep
Load/unload is also invoked as one of the idle modes of the drive. The specified start/stop life of the product assumes that load/unload is operated normally, not in emergency mode.
6.3.7.
Emergency unload
When hard disk drive power is interrupted while the heads are still loaded the micro code cannot operate and the normal 3.3-volt power is unavailable to unload the heads. In this case, normal unload is not possible. The heads are unloaded by routing the back EMF of the spinning motor to the voice coil. The actuator velocity is greater than the normal case and the unload process is inherently less controllable without a normal seek current profile. Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload. The drive supports a minimum of 20,000 emergency unloads.
6.3.8.
Required Power-Off Sequence
The required sequence for removing power from the drive is as follows: Step 1: Issue one of the following commands. Standby Standby immediate Sleep
Note: Do not use the Flush Cache command for the power off sequence because this command does not invoke Unload. Step 2: Wait until the Command Complete status is returned. In a typical case 350 ms are required for the command to finish completion; however, the host system time out value needs to be 30 seconds considering error recovery time. Step 3: Terminate power to HDD. This power-down sequence should be followed for entry into any system power-down state, system suspend state, or system hibernation state. In a robustly designed system, emergency unload is limited to rare scenarios, such as battery removal during operation.
6.3.9.
Power switch design considerations
In systems that use the C3K80 consideration should be given to the design of the system power switch. HITACHI recommends that the switch operate under control of the host system, as opposed to being hardwired. The same recommendation is made for cover-close switches. When a hardwired switch is turned off, emergency unload occurs, as well as the problems cited in section 5.1, "Data loss by power off" on page 22 and section 5.2, Write Cache on page 22.
6.3.10. Test considerations

Start/stop testing is classically performed to verify head/disk durability. The heads do not land on the disk, so this type of test should be viewed as a test of the load/unload function. Start/Stop testing should be done by commands through the interface, not by power cycling the drive. Simple power cycling of the drive invokes the emergency unload mechanism and subjects the HDD to nontypical mechanical stress. Power cycling testing may be required to test the boot-up function of the system. In this case HITACHI recommends that the power-off portion of the cycle contain the sequence specified in section 6.4.6.2, 30/129
C3K80 (PATA) Hard Disk Drive Specification "Required Power-Off Sequence on page 30. If this is not done, the emergency unload function is invoked and nontypical stress results.
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6.4.
6.4.1.
Mechanical specifications
Physical dimensions and weight
The following figure lists the dimensions for the drive.
Table 15: Physical dimensions and weight

Model 80 GB, 60 GB models 40 GB, 30 GB models Height (mm) 8.00.2 5.00.2 Width (mm) 540.25 540.25 Length (mm) 71+0/-0.5 71+0/-0.5 Weight (gram) 59(max.) 48(max.)
6.4.2.
Mechanical dimensions
The size and mounting area locations of the drive are shown below.
:Mounting Area (Unit : mm)
Figure 2: Mounting Area locations
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6.4.3.
Connector and jumper description
A jumper is none. Connector specifications are included in section 7.2, "Interface connector" on page 41.
6.4.4.
Mounting orientation
The drive will operate in all axes (360). Performance and error rate will stay within specification limits if the drive is operated in the other permissible orientations from which it was formatted. Thus a drive formatted in a horizontal orientation is able to run vertically and vice versa. Vibration test and shock test are to be conducted by mounting the drive to the test table using a special fixture
6.4.5.
Load/unload mechanism
The head load/unload mechanism is provided to protect the disk during shipping, movement, or storage. Upon power down, a head unload mechanism secures the heads at the unload position. See Section, Nonoperating shock for additional details.
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6.5.
Vibration and shock
All vibration and shock measurements in this section are for the drive without the mounting attachments for the systems. The input level is applied to the normal drive mounting points. Operating vibration The drive will operate without a hard error while being subjected to the following vibration levels.
6.5.1. 6.5.2.
Operating vibration Random vibration
The drive will operate without a hard error while being subjected to the following vibration levels.
The test consists of 30 minutes of random vibration using the power spectral density (PSD) levels below. 2 The vibration test level is 6.57 m/sec RMS (Root Mean Square) (0.67 G RMS).
Table 16: Random vibration PSD profile breakpoints (operating)

Random vibration PSD profile Breakpoint 2 4 Hz m x 10n (m /sec )/Hz 5 1.9 x E 3 17 1.1 x E 1 45 1.1 x E 1 48 7.7 x E 1 62 7.7 x E 1 65 9.6 x E 1 150 9.6 x E 1 200 4.8 x E 2 500 4.8 x E 2
6.5.3.
Swept sine vibration

Sweep rate (oct/min) 1.0
Table 17: Swept sine vibration

Swept sine vibration (zero to peak 5 to 500 to 5 Hz sine wave) 2 19.6 m/ sec (2 G) (5-500 Hz)
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6.5.4. 6.5.5.
Nonoperating vibration Random vibration
The disk drive withstands the following vibration levels without any loss or permanent damage.
The test consists of a random vibration applied in each of three mutually perpendicular axes for a duration of 15 minutes per axis. The PSD levels for the test simulating the shipping and relocation environment is shown below.
Table 18: Random Vibration PSD Profile Breakpoints (nonoperating)

Hz 2.5 5 40 500 Note: Overall RMS level of vibration is 29.50 m/sec2 (3.01 G). (m/sec )/Hz 0.096 2.88 1.73 1.73
2
6.5.6.

Swept sine vibration

49 m/ sec (5 G) (zero-to-peak), 5 to 500 to 5 Hz sine wave 0.5 oct/min sweep rate 25.4 mm (peak-to-peak) displacement, 5 to 10 to 5 Hz
2
6.5.7.
Operating shock
The hard disk drive meets the criteria in the table below while operating under these conditions: The shock test consists of 10 shock inputs in each axis and direction for a total of 60. There must be a minimum delay of 3 seconds between shock pulses. The disk drive will operate without a hard error while subjected to the following half-sine shock pulse.
Table 19: Operating shock

Duration of 2 ms 5880 m/sec (600 G) The input level shall be applied to the normal disk drive subsystem mounting points used to secure the drive in a normal system.
2
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6.5.8.
Nonoperating shock
The drive withstands the following half-sine shock pulse without any data loss or permanent damage.
Table 20: Nonoperating shock

Duration of 1 ms 14700 m/sec (1500 G) The shocks are applied for each direction of the drive for three mutually perpendicular axes, one axis at a time. Input levels are measured on a base plate where the drive is attached with fixture.
2
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6.6.
6.6.1.
Acoustics
Sound power level
The criteria of A-weighted sound power level are described below. Measurements are to be taken in accordance with ISO 7779. The mean of the sample of 40 drives is to be less than the typical value. Each drive is to be less than the maximum value. The drives are to meet this requirement in both top cover down orientations.
Table 21: Weighted sound power

A-weighted Sound Power 80GB, 60GB models Idle Operating 40GB, 30GB models Idle Operating 1.4 2.0 1.7 2.3 1.6 2.2 1.9 2.5 Typical (Bels) Maximum (Bels)
The background power levels of the acoustic test chamber for each octave band are to be recorded. Sound power tests are to be conducted with the drive supported by spacers so that the lower surface of the drive be located 1253 mm above from the chamber floor. No sound absorbing material shall be used. The acoustical characteristics of the disk drive are measured under the following conditions: Mode definitions Idle mode: Power on, disks spinning, track following, unit ready to receive and respond to control line commands. Operating mode: Continuous random cylinder selection and seek operation of the actuator
with a dwell time at each cylinder. The seek rate for the drive can be calculated as shown below. Ns = 0.4/(Tt + T1) where: Ns = average seek rate in seeks/s Tt = published seek time from one random track to another without including rotational latency T1= equivalent time in seconds for the drive to rotate by half a revolution
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6.6.2.
Discrete tone penalty
Discrete tone penalties are added to the A-weighted sound power (Lw) with the following formula only when determining compliance. Lwt(spec) = Lw = 0.1Pt + 0.3 < 4.0 (Bels) where Lw = A-weighted sound power level Pt = Value of desecrate tone penalty = dLt 6.0(dBA) dLt = Tone-to-noise ratio taken in accordance with ISO 7779 at each octave band.
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6.7.

Identification labels
The HITACHI logo Model name The capacity and rotational speed Part number The statement "Made by HGST" Country of origin The marks of Agencies approval Bar code of the serial numbers
The labels are affixed to every drive. The top side of the label contains
The bottom side of the label contains
Additional requirements by customer are allowed.
6.8.
Electromagnetic compatibility
When installed in a suitable enclosure and exercised with a random accessing routine at maximum data rate, the drive meets the following worldwide electromagnetic compatibility (EMC) requirements:
6.8.1. CE Mark
The product is certified for compliance with EC directive 89/336/EEC. The EC marking for the certification appears on the drive.
6.8.2.
C-Tick Mark
The product complies with the Australian EMC standard "Limits and methods of measurement of radio disturbance characteristics of information technology equipment, AS/NZS 3548: 1995."
6.8.3.
BSMI Mark
The product complies with the Taiwan EMC standard Limits and methods of measurement of radio disturbance characteristics of information technology equipment, CNS 13438 .35
6.8.4.
MIC Mark
The product complies with the Korea EMC standard. The regulation for certification of information and communication equipment is based on Telecommunications Basic Act and Radio Waves Act Korea EMC requirement are based technically on CISPR22:1993-12 measurement standards and limits. MIC standards are likewise based on IEC standards.
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6.9.
6.9.1.
Safety
UL and CSA approval
The product is qualified per UL (Underwriters Laboratory) 60950-1 1st Edition and CAN/CSA C22.2 No.60950-1, for the use in Information Technology Equipment, including Electric Business Equipment. The UL Recognition or the CSA certification is maintained for the product life. The UL and C-UL recognition mark or the CSA monogram for CSA certification appears on the drive.
6.9.2. 6.9.3. 6.9.4.
IEC compliance German Safety Mark Flammability
All models comply with IEC 60950-1:2001.
All models are approved by TUV on Test Requirement: EN 60950-1: 2001 +A11.
The printed circuit boards used in this product are made of material with a UL recognized flammability rating of V-1 or better. The flammability rating is marked or etched on the board. All other parts not considered electrical components are made of material with a UL recognized flammability rating of V-1 or better except minor mechanical parts.
6.9.5.
Secondary circuit protection
This product utilizes printed circuit wiring that must be protected against the possibility of sustained combustion due to circuit or component failures as defined in C-B 2-4700-034 (Protection Against Combustion). Adequate secondary over current protection is the responsibility of the using system. The user must protect the drive from its electrical short circuit problem. A 10 amp limit is required for safety purpose.
6.10.
Packaging
Drives are packed in ESD protective bags and shipped in appropriate containers.
6.11. Substance restriction requirements

The product complies with the Directive 2002/95/EC of the European Parliament on the restrictions of the use of the certain hazardous substances in electrical and electronic equipment (RoHS).
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7. Electrical interface specifications

7.1. 7.2. Cabling Interface connector
The maximum cable length from the host system to the hard disk drive plus circuit pattern length in the host system shall not exceed 90 mm.
The signal connector for AT attachment is designed to mate with DDK / type FF19W-40B-R11B (Gold plate contact) or equivalent. The figure shows the connector location and physical pin location.
Figure 3: Interface connector location

Gold plate on FPC contact is required to avoid Sn whisker completely. 20.5 +/- 0.07mm width, 0.2 +/- 0.03mm thickness FPC with reinforcement is recommended. 2-layer FPC(one layer is GND plane) is recommended for better signal integrity. Durability is 20 times with the same connector and FPC. FPC holding force is min. 6.0N. Please secure appropriate margin in the FPC length not to apply excessive force on shock. Do not lock without FPC.
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7.3.
Signal definitions
pin 21 22 23 24 25 26 27 28 29 30 signal name GROUND DMARQ GROUND DIOW- (*) DIOR- (*) GROUND IORDY (*) GROUND DMACKINTRQ pin 31 32 33 34 35 36 37 38 39 40 signal name DA1 PDIAGDA0 DA2 CS0CS1DASP3.3V 3.3V Reserved
The pin assignments of interface signals are listed as follows: Table 22: Connector pin assignment pin signal name pin signal name 1 factory use 11 DD4 2 factory use 12 DD11 3 RESET13 DD3 4 GROUND 14 DD12 5 DD7 15 DD2 6 DD8 16 DD13 7 DD6 17 DD1 8 DD9 18 DD14 9 DD5 19 DD0 10 DD10 20 DD15
O I I/O OD power reserved
designates an output from the drive designates an input to the drive designates an input/output common designates an Open-Drain output designates a power supply to the drive designates reserved pins which must be left unconnected
The signal lines marked with (*) are redefined during the Ultra DMA protocol to provide special functions. These lines change from the conventional to special definitions at the moment the host decides to allow a DMA burst, if the Ultra DMA transfer mode was previously chosen via SetFeatures. The drive becomes aware of this change upon assertion of the DMACK- line. These lines revert back to their original definitions upon the deassertion of DMACK at the termination of the DMA burst.
Table 23: Special signal definitions for Ultra DMA Special Definition (for Ultra DMA) Write Operation DDMARDYHSTROBE STOP HDMARDYDSTROBE STOP
Conventional Definition
Read Operation
IORDY DIORDIOWDIORIORDY DIOW-
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7.4.
Signal descriptions
The interface is an ATA(IDE) interface. Reserved pins should be left unconnected. The signal names and the pin numbers are shown in Figure 3 and Table 23 shows signal definitions. "I" of I/O type represents an input signal from the device and "O" represents an output signal from the device.
Table 24: Signal List

Signal name RESETDD0-DD15 DIOWSTOP *1 DIORPin 3 5-20 24 I/O type I I/O I Description This is a reset signal output from the host system and to be used for interface logic circuit. This is a 16-bit bi-directional data bus. The lower 8 bits are used for register access other than data register. The rising edge of this Write Strobe signal clocks data from the host data bus into a register on the device. Assertion of this signal by the host during an Ultra DMA burst signals the termination of the Ultra DMA burst. Activating this Read Strobe signal enables data from a register on the device to be clocked onto the host data bus. The rising edge of this signal latches data at the host. This signal is a flow control signal for Ultra DMA Read. Host asserts this signal, and indicates that the host is ready to receive Ultra DMA Read data . This signal is Write data strobe signal from the host for an Ultra DMA Write. Both the rising and falling edge latch the data from DD(15:0) into the device. This signal is used to temporarily stop the host register access (read or write) when the device is not ready to respond to a data transfer request. This signal is a flow control signal for Ultra DMA Write. Device asserts this signal, and indicates that the device is ready to receive Ultra DMA Write data . This signal is the data in strobe signal from the device for an Ultra DMA Read. Both the rising and falling edge latch the data from DD(15:0) into the host. This is an interrupt signal for the host system. This signal is asserted by a selected device when the nIEN bit in the Device Control Register is "0". In other cases, this signal should be a high impedance state. This is a register address signal from the host system. The host shall wait until the power on or hardware reset sequence is complete for all devices on the cable; This device chip selection signal is used to select the Command Block Registers from the host system. This device chip selection signal is used to select the Control Block Registers from the host system. This signal indicates that a device is active when the power is turned on. Upon receipt of a command from the host, the device asserts this signal. At command completion, the device de-asserts this signal. The device shall assert this signal, used for DMA data transfers between host and device, when it is ready to transfer data. The host in response to DMARQ to either acknowledge that data has been accepted, or that data is available shall use this signal.
25
HDMARDY*1 HSTROBE *1 IORDY DDMARDY*1 DSTROBE *1 INTRQ 30 O 27 O
DA0-2 PDIAG-:CBLI D-*2 CS0CS1DASP-
31,33,34 32 35 36 37
I I/O I I I/O
DMARQ DMACK-
22 29
O I
*1: Signal name in Ultra DMA mode *2: PDIAG-:CBLID- (Passed diagnostics: Cable assembly type identifier
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C3K80 (PATA) Hard Disk Drive Specification The I/O signal levels are as follows. (1) Input signal High level 2.0V to Vcc0.5V Low level 0.5V to 0.8V (2) Output signal High level 2.4V to 3.46V or an open circuit Low level 0.4V or less (IOL=2mA), 0.5V or less (IOL=12mA) Note The I/F cable should be no longer than 90mm including the circuit pattern length in the host system. If the cable length is not within this specification, it may cause functional degradations or some errors.
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7.5.
Inputs Outputs:
Interface logic signal levels

Voltage Input High (ViH) Voltage Input Low (ViL) Voltage output high at IoH min (VoH) Voltage output low at IoL min (VoL) Driver Sink Current (IoL) Driver Source Current (IoH) 2.0 V min./3.8 V max. 0.5 V min./0.8 V max. 2.4 V min. 0.5 V max.
The interface logic signals have the following electrical specifications:
Current
16 mA min. 400 A min.
7.6.
Reset timings
RESET t10
BUSY t1
Table 25: System reset timings

PARAMETER DESCRIPTION Min. (s) 25 Max. (s) 9.5
t1 t10
RESET high to Not BUSY RESET low width
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7.7.
PIO timings
The PIO cycle timings meet Mode 4 of the ATA/ATAPI-7 description.
CS(1:0)DA(2:0) t9 t1 DIOR-, DIOWt2 Write data DD(15:0) t3 Read data DD(15:0) t5 t6

t6z
t0
t2i
t4
tRD IORDY tA tB
Table 26: PIO cycle timings

PARAMETER DESCRIPTION Cycle time Address valid to DIOR-/DIOW- setup DIOR-/DIOW- pulse width DIOR-/DIOW- recovery time DIOW- data setup DIOW- data hold DIOR- data setup DIOR- data hold DIOR- data tristate DIOR-/DIOW- to address valid hold Read data valid to IORDY active IORDY setup width IORDY pulse width MIN (ns) 120 25 70 25 20 10 20 5 10 0 MAX. (ns) 30 35 1,250
t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 tRD tA tB
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7.8.
Multiword DMA timings
The Multiword DMA timings meet Mode 2 of the ATA/ATAPI-7 description.
DMARQ tLR/tLW DMACKtI DIOR-/DIOWtG READ DD(15:0) tG WRITE DD(15:0) tH tF tZ tD t0 tKR/tKW tJ
Table 27:Multiword DMA cycle timings

PARAMETER DESCRIPTION Cycle time DIOR-/DIOW- asserted pulse width DIOR- data access DIOR- data hold DIOR-/DIOW- data setup DIOW- data hold DMACK- to DIOR-/DIOW- setup DIOR-/DIOW- to DMACK- hold DIOR negated pulse width / DIOW- negated pulse width DIOR- to DMARQ delay / DIOW- to DMARQ delay DMACK- to read data released MIN (ns) 120 70 5 20 10 0 5 25 MAX (ns) 50 35 25
t0 tD tE tF tG tH tI tJ tKR/tKW tLR/tLW tZ
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7.9.
7.9.1.
DMARQ
Ultra DMA timings

Initiating Read DMA
The Ultra DMA timings meet Mode 0, 1 and 2 of the Ultra DMA Protocol.
tUI DMACKtACK STOP tACK HDMARDYtZIORDY DSTROBE DD(15:0) tAZ tAZD xxxxxxxxxxxxxxxxxxxxxxxxx Host drives DD tFS tCYC tENV t2CYC tCYC tENV
tDS tDH
xxx RD Data xxx RD Data xxx RD Data Device drives DD
Table 28: Ultra DMA cycle timings (Initiating Read)

PARAMETER DESCRIPTION tUI tACK tENV tZIORD tFS tCYC t2CYC tAZ Unlimited interlock time Setup time for DMACK- assertion Envelope time Minimum time before driving IORDY First DSTROBE time Cycle time Two cycle time Maximum time allowed for output drivers to release Drivers to assert Data setup time at host Data hold time at host MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
0 20 20 0 0 112 230
70 230 10
0 20 20 0 0 73 154
70 200 10
0 20 20 0 0 54 115
70 170 10
tAZD tDS tDH
0 15 5
0 10 5
0 7 5
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7.9.2.
DMARQ
Host Pausing Read DMA
DMACK-
STOP tSR HDMARDYtRFS DSTROBE
Table 29: Ultra DMA cycle timings (Host Pausing Read)

PARAMETER DESCRIPTION tSR tRFS DSTROBE to HDMARDY- time HDMARDY- to final DSTROBE time MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
50 75
30 70
20 60
Note: When a host does not satisfy the tSR timing, the host should be ready to receive two more data words after HDMARDY- is negated.
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7.9.3.
DMARQ
Host Terminating Read DMA
tLI DMACKtRP STOP
tMLI
tACK
tACK HDMARDYtRFS
tLI
tIORDYZ tDH tAZ tDS xxx CRC xxxxxxxxxx
DSTROBE xxx RD Data xxxxxxxxxxxxxxxxxx tZAH Device drives DD
DD(15:0)
Host drives DD
Table 30: Ultra DMA cycle timings (Host Terminating Read)

PARAMETER DESCRIPTION tRFS tRP tLI tAZ HDMARDY- to final DSTROBE time Minimum time to assert STOP Limited interlock time Maximum time allowed for output drivers to release Minimum delay time required for output Interlock time with minimum CRC word setup time at device CRC word hold time at device Hold time DMACKnegation Maximum time before releasing IORDY MODE 0
MIN (ns) MAX (ns)
MODE 1
MIN (ns) MAX (ns)
MODE 2
MIN (ns) MAX (ns)
160 0
75 150 10 20
125 0
70 150 10 20
100 0
60 150 10 20
tZAH tMLI tDS tDH tACK tIORDYZ
20 20 15 5 20
20 20 10 5 20
20 20 7 5 20
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7.9.4.
DMARQ
Device Terminating Read DMA
tSS DMACKtLI STOP tLI HDMARDYtLI DSTROBE tAZ DD(15:0) xxxxx tZAH Device drives DD
tMLI
tACK
tACK
tIORDYZ
tDH tDS xxxxxxxxxxxxxxxxxx CRC
xxxxxxxxxx
Host drives DD
Table 31: Ultra DMA cycle timings (Device Terminating Read)

PARAMETER DESCRIPTION tSS Time from DSTROBE edge to negation of DMARQ Limited interlock time Maximum time allowed for output drivers to release Maximum delay time required for output Interlock time with minimum CRC word setup time at device CRC word hold time at device Hold time for DMACKnegation Maximum time before releasing IORDY MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
50
50
50
tLI tAZ
150 10 20
150 10 20
150 10 20
tZAH tMLI tDS tDH tACK tIORDYZ
20 20 15 5 20
20 20 10 5 20
20 20 7 5 20
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7.9.5.
DMARQ
Initiating Write DMA
tUI DMACKtACK STOP tZIORDY DDMARDYtACK HSTROBE tDS DD(15:0) xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx tDH tUI tCYC tLI t2CYC tCYC tENV
WT Data xxx WT Data xxx WT Data
Host drives DD
Table 32: Ultra DMA cycle timings (Initiating Write)

PARAMETER DESCRIPTION tUI tACK tENV tZIORDY tLI tCYC T2CYC tDS tDH Unlimited interlock time Setup time for DMACK- assertion Envelope time Minimum time before driving HSTROBE Limited interlock time Cycle time Two cycle time Data setup time at device Data Hold time at device MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
0 20 20 0 0 112 230 15 5
70 150
0 20 20 0 0 73 154 10 5
70 150
0 20 20 0 0 54 115 7 5
70 150
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7.9.6.
DMARQ DMACK-
Device Pausing Write DMA
STOP tSR DDMARDYtRFS HSTROBE
Table 33: Ultra DMA cycle timings (Device Pausing Write)

PARAMETER DESCRIPTION tSR HSTROBE to DDMARDYtime DDMARDY- to final HSTROBE time MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
50
30
20
tRFS
75
70
60
Note: When a device does not satisfy the tSR timing, the device is ready to receive two more data words after DDMARDY- is negated.
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7.9.7.
DMARQ
Device Terminating Write DMA
tRP DMACK-
tLI
tMLI
tACK STOP tIORDYZ DDMARDYtRFS HSTROBE tDH tDS DD(15:0) xxx WT Data xxxxxxxxxxxxxxxxxxxxxxxxxx CRC xxxxxxxxxx tLI tACK
Host drives DD
Table 34: Ultra DMA cycle timings (Device Terminating Write)

PARAMETER DESCRIPTION tRFS tRP tLI tMLI tDS tDH tACK tIORDY Z DDMARDY- to final HSTROBE time Minimum time to negate DMARQ Limited interlock time Interlocking time CRC word setup time at device CRC word hold time at device Hold time for DMACK- negation Maximum time before releasing IORDY MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
160 0 20 15 5 20
75 150 20
125 0 20 10 5 20
70 150 20
100 0 20 7 5 20
60 150 20
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7.9.8.
DMARQ
Host Terminating Write DMA
tLI DMACKtSS STOP tLI DDMARDYtLI HSTROBE
tMLI
tACK
tIORDYZ
tACK tDH tDS CRC
DD(15:0)
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx Host drives DD
xxxxxxxxxx
Table 35: Ultra DMA cycle timings (Host Terminating Write)

PARAMETER DESCRIPTION tSS Time from HSTROBE edge to assertion of STOP Limited interlock time Interlock time CRC word setup time at device CRC word hold time at device Hold time for DMACK- negation Maximum time before releasing IORDY MODE0
MIN (ns) MAX (ns)
MODE1
MIN (ns) MAX (ns)
MODE2
MIN (ns) MAX (ns)
50
50
50
tLI tMLI tDS tDH tACK tIORDYZ
0 20 15 5 20
150 20
0 20 10 5 20
150 20
0 20 7 5 20
150 20
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7.10.
None
Drive address setting
7.10.1. Drive default address setting

None
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7.11.
Addressing of HDD registers
The host addresses the drive through a set of registers called a Task File. These registers are mapped into the host's I/O space. Two chip select lines (CS0- and CS1-) and three address lines (DA00 02) are used to select one of these registers, while a DIOR- or DIOW- is provided at the specified time. The chip select line CS0- is used to address the Command Block registers while the CS1- is used to address Control Block registers. The following table shows the I/ O address map.
Table 36: I/O address map

CS00 0 0 0 0 0 0 0 1 1 CS11 1 1 1 1 1 1 1 0 0 DA02 0 0 0 0 1 1 1 1 1 1 DA01 0 0 1 1 0 0 1 1 1 1 DA00 0 1 0 1 0 1 0 1 0 1 DIOR- = 0 (Read) DIOW- = 0 (Write) Command Block Registers Data Reg. Data Reg. Error Reg. Features Reg. Sector count Reg. Sector count Reg. LBA low Reg. LBA low Reg. LBA mid Reg. LBA mid Reg. LBA high Reg. LBA high Reg. Device Reg. Device Reg. Status Reg. Command Reg. Control Block Registers Alt. Status Reg. Device control Reg. Drive address Reg.
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Part 2 Interface Specification
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8. Parallel ATA Command Protocol

The commands are grouped into different classes according to the protocols followed for command execution. The command classes with their associated protocols are defined below. For all commands, the host must first check if BSY=1, and should proceed no further unless and until BSY=0. For all commands, the host must also wait for DRDY=1 before proceeding. A device must maintain either BSY=1 or DRQ=1 at all times until the command is completed. The INTRQ signal is used by the device to signal most, but not all, times when the BSY bit is changed from 1 to 0 during command execution. A command shall only be interrupted with a hardware or software reset. The result of writing to the Command register while BSY=1 or DRQ=1 is unpredictable and may result in data corruption. A command should only be interrupted by a reset at times when the host thinks there may be a problem, such as a device that is no longer responding. Interrupts are cleared when the host reads the Status Register, issues a reset, or writes to the Command register.
8.1.
PIO Data In Commands
These commands are; Identify Device Read Buffer Read Long Read Multiple Read Multiple EXT Read Sectors Read Sectors EXT SMART Function Set (Features code: D0h, D1h) Note: When a description is applicable for both 48 bit command and non 48 bit command, a notation like 'Read Multiple (EXT) command' is used throught out the specifications. Execution includes the transfer of one or more 512byte (>512 bytes on Read Long) sectors of data from the device to the host. 1. The host writes any required parameters to the Features, Sector Count, LBA Low, LBA Mid, LBA High and Device registers. 2. The host writes the command code to the Command register. 3. For each sector (or block) of data to be transferred: a. The device sets BSY=1 and prepares for data transfer. b. When a sector (or block) of data is available for transfer to the host, the device sets BSY=0, sets DRQ=1, and interrupts the host. c. In response to the interrupt, the host reads the Status register. d. The device clears the interrupt in response to the Status register being read. e. The host reads one sector (or block) of data via the Data register. f. The device sets DRQ=0 after the sector (or block) has been transferred to the host. 4. For the Read Long command: a. The device sets BSY=1 and prepares for data transfer. b. When the sector of data is available for transfer to the host, the device sets BSY=0, sets DRQ=1, and interrupts the host. c. In response to the interrupt, the host reads the Status register. d. The device clears the interrupt in response to the Status register being read. e. The host reads the sector of data including ECC bytes via the Data register. f. The device sets DRQ=0 after the sector has been transferred to the host. 59/129
C3K80 (PATA) Hard Disk Drive Specification The Read Multiple (EXT) commands transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt. Note that the status data for a sector of data is available in the Status register before the sector is transferred to the host. If the device detects an invalid parameter, then it will abort the command by setting BSY=0, ERR=1, ABT=1, and interrupting the host. If an error occurs, the device will set BSY=0, ERR=1, and DRQ=1. The device will then store the error status in the Error register, and interrupt the host. The registers will contain the location of the sector in error. The error location will be reported with CHS mode or LBA mode, the mode is decided by the L bit (bit 6) of the Device register on issuing the command. If an Uncorrectable Data Error (UNC=1) occurs, the defective data will be transferred from the media to the sector buffer, and will be available to be transferred to the host, at the host's option. In case of Read Multiple (EXT) command, the host should complete transfer the block which includes the error from the sector buffer and terminate whatever kind of type of error occurred. All data transfers to the host through the Data register are 16 bits, except for the ECC bytes, which are 8 bits.
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8.2.

PIO Data Out Commands

Write Write Write Write Write Write Write Buffer Long Multiple Multiple EXT Sectors Sectors EXT Verify
These commands are;
Execution includes the transfer of one or more 512 bytes (>512 bytes on Write Long) sectors of data from the host to the device. 1. The host writes any required parameters to the Features, Sector Count, LBA Low, LBA Mid, LBA High and Device registers. 2. The host writes the command code to the Command register. 3. The device sets BSY=1. 4. For each sector (or block) of data to be transferred: a. The device sets BSY=0 and DRQ=1 when it is ready to receive a sector (or block). b. The host writes one sector (or block) of data via the Data register. c. The device sets BSY=1 after it has received the sector (or block). d. When the device has finished processing the sector (or block), it sets BSY=0, and interrupts the host. e. In response to the interrupt, the host reads the Status register. f. The device clears the interrupt in response to the Status register being read. 5. For the Write Long command: a. The device sets BSY=0 and DRQ=1 when it is ready to receive a sector. b. The host writes one sector of data including ECC bytes via the Data register. c. The device sets BSY=1 after it has received the sector. d. After processing the sector of data the device sets BSY=0 and interrupts the host. e. In response to the interrupt, the host reads the Status register. f. The device clears the interrupt in response to the Status register being read. The Write Multiple (EXT) command transfers one block of data for each interrupt. The other commands transfer one sector of data for each interrupt. If the device detects an invalid parameter, then it will abort the command by setting BSY=0, ERR=1, ABT=1, and interrupting the host. If an uncorrectable error occurs, the device will set BSY=0 and ERR=1, store the error status in the Error register, and interrupt the host. The registers will contain the location of the sector in error. The error location will be reported with CHS mode or LBA mode. The mode is decided by the L bit (bit 6) of the Device register on issuing the command. All data transfers to the device through the Data register are 16 bits, except for the ECC bytes, which are 8 bits.
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8.3.
Non-Data Commands
These commands are; Check Power Mode Execute Device Diagnostic Flush Cache Flush Cache EXT Idle Idle Immediate Idle Immediate with Unload Initialize Device Parameters Read Verify Sectors Read Verify Sectors EXT Recalibrate Seek Sense Condition Sense Drive Temperature Set Features Set Multiple Mode Sleep SMART Function Set (Features codes: D2h, D4h, D8h, D9h, DAh) Standby Standby Immediate Execution of these commands involves no data transfer. 1. The host writes any required parameters to the Features, Sector Count, LBA Low, LBA Mid, LBA High and Device registers 2. The host writes the command code to the Command register. 3. The device sets BSY=1. 4. When the device has finished processing the command, it sets BSY=0, and interrupts the host. 5. In response to the interrupt, the host reads the Status Register 6 The device clears the interrupt in response to the Status register being read.
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8.4.
DMA Data Transfer Commands
These commands are; Read DMA Read DMA EXT Write DMA Write DMA EXT Data transfer using DMA commands differ in two ways from PIO transfers: Data transfers are performed using the slave-DMA channel. No intermediate sector interrupts are used. The DMA protocol allows high performance multi-tasking operating system to eliminate processor overhead associated with PIO transfer. 1. The host initializes the slave-DMA channel. 2. The host writes any required parameters to the Features, Sector Count, LBA Low, LBA Mid, LBA High and Device registers 3. The host writes the command code to the Command register. 4. The device sets DMARQ when it is ready to transfer any part of the data. 5. Host transfers the data using the DMA transfer protocol currently in effect. 6. When all of the data has been transferred, the device generates an interrupt to the host. 6 Host resets the slave-DMA channel 7 Host reads the Status register and, and optionally the Error register
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9. ATA Registers
9.1. ATA Registers Address
The Command Block registers are used for sending commands to the device or posting status from the device. The Control Block registers are used for device control and to post alternate status.
Table 37 ATA Registers Address

-CS1 -CS0 DA2 DA1 DA0 -DIOR=0 -DIOW=0
1 1 1 1 1 1 1 1 0
0 0 0 0 0 0 0 0 1
0 0 0 0 1 1 1 1 1
0 0 1 1 0 0 1 1 1
0 1 0 1 0 1 0 1 0
RD Data Error Sector Count LBA Low LBA Mid LBA High Device Status Alternate Status
WR Data Features Sector Count LBA Low LBA Mid LBA High Device Command Device Control
9.1.1. Alternate Status Register

Table 38 Alternate Status Register
Alternate Status Register 7 BSY 6 DRDY 5 DF 4 DSC 3 DRQ 2 obs 1 obs 0 ERR
This register contains the same information as the Status register. The only difference is that reading this register does not clear a pending interrupt.
9.1.2. Command Register

This register contains the command code being sent to the device. Command execution begins immediately after this register is written. All other registers required for the command must be set up before writing the Command Register.
9.1.3. Data Register

This register is used to transfer data blocks between the device data buffer and the host for data-in, data-out and DMA commands.
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9.1.4. Device Control Register

Table 39 Device Control Register
Device Control Register 7 HOB 6 rsvd 5 rsvd 4 rsvd 3 rsvd 2 SRST 1 nIEN 0 0
This register is used to control 48 bit addressing and to issue an ATA soft reset to the card. This register can be written even if the device is BUSY. Bit Definitions HOB SRST nIEN
HOB (high order bit) is used to read the previous content of Features, Sector Count, LBA High/Mid/Low registers. A write to Command register clears HOB bit to zero. Soft Reset. The host must set SRST=1 and wait for at least 5 microseconds before resetting SRST=0 to ensure that the device recognizes the Soft Reset. Not Interrupt Enable. When nIEN=0 and the device is selected, device interrupts to the host are enabled. When nIEN=1 or the device is not selected, device interrupts to the host are disabled.
9.1.5. Device Register

Table 40 Device Register
Device Register 7 obs 6 L 5 obs 4 DEV 3 HS3 2 HS2 1 HS1 0 HS0
This register selects the CHS or LBA addressing mode, and has the head number or part of LBA bits. It also selects Device 0 (master) or Device 1 (slave). Bit Definitions L DEV HS3 - HS0 Address mode select. When L=0, addressing is by CHS mode. When L=1, addressing is by LBA mode. Device selection. When DEV=0, device 0 (master) is selected. When DEV=1, device 1 (slave) is selected. Head Select. HS0 is the least significant bit. In CHS mode, HS3 HS0 is selected head number. At command completion, these bits are updated to reflect the currently selected head. The head number may be from zero to the number of heads minus one. In LBA mode (28 bit address), HS3 - HS0 contain bits 24-27 of the LBA. At command completion, these bits are updated to reflect the current LBA bits 24-27.
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9.1.6. Error Register

Table 41 Error Register
Error Register 7 ICRC 6 UNC 5 0 4 IDNF 3 0 2 ABRT 1 TK0NF 0 AMNF
This register contains status from the last command executed by the device, or a diagnostic code. At the completion of any command except Execute Device Diagnostic, the contents of this register are valid even if ERR=0 in the Status register. Following a power on, a reset, or completion of an Execute Device Diagnostic command, this register contains a diagnostic code. Refer to the section of Register Initialization.
9.1.7. LBA High Register

In the LBA mode (28 bit address), this register contains LBA Bits 16-23. At the end of the command, this register is updated to reflect the current LBA Bits 16-23. In the CHS mode, this register contains the high order bits of the starting cylinder address. At the end of the command, this register is updated to reflect the current cylinder number. The cylinder number may be from zero to the number of cylinders minus one.
9.1.8. LBA Mid Register

In the LBA mode (28 bit address), this register contains LBA Bits 8-15. At the end of the command, this register is updated to reflect the current LBA Bits 8-15. In the CHS mode, this register contains the low order 8 bits of the starting cylinder address. At the end of the command, this register is updated to reflect the current cylinder number. The cylinder number may be from zero to the number of cylinders minus one.
9.1.9. LBA Low Register

In the LBA mode (28 bit address), this register contains LBA Bits 0-7. At the end of the command, this register is updated to reflect the current LBA Bits 0-7. In the CHS mode, this register contains the starting sector number. At the end of the command, this register is updated to reflect the current sector number. The sector number may be from 1 to the maximum number of sectors per track.
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9.1.10. Status Register

Table 42 Status Register
Status Register 7 BSY 6 DRDY 5 DF 4 DSC 3 DRQ 2 obs 1 obs 0 ERR
This register contains the current device status. The contents are updated at the completion of each command. If BSY=1, no other bits in this register are valid. When BSY is cleared, the other bits in this register is valid within 400 ns. If the host reads this register when an interrupt is pending, the pending interrupt is cleared.
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10.
10.1.
General Operational Descriptions

Reset Response
Type POR Hard Reset Soft Reset Description A reset carried out at power up sequence of the device A reset initiated by a raising edge of RESET signal A reset initiated by changing SRST bit of Device Control register (setting 0, 1 then 0).
There are three types of resets in a device: a Power On Reset (POR), a Hard Reset, and a Soft Reset.
Table 43 Reset Types
The table below shows detailed effects on the device of each type of resets.
Table 44 Reset Response

Description Aborting Host interface Aborting Device operation Initialization of hardware Internal diagnostics Initialization of task file registers (2) Initialization of registers at attribute memory DASPhandshake PDIAGhandshake Reverting programmed parameters to power-on default Logical geometry (number of cylinders/heads/sectors) Multiple mode Write cache Read look-ahead ECC bytes for Read Long and Write Long Delayed Write On-demand prefetch Byte transfer mode PIO transfer mode DMA transfer mode ABLE mode Reset Standby Timer POR N/A N/A Executed Executed Executed Executed Executed Executed Executed Hard Reset Executed Executed (1) Executed Executed Executed Executed Executed Executed Executed Soft Reset Executed Executed (1) Not Executed Not Executed Executed Not Executed Executed Executed (3)
Executed
Executed
Not Executed
Notes: (1) If the device receives a reset during cached writing, the reset completes after cached writing completes. (2) Initialized value of task file registers are shown in the section of Register Initialization. (3) If the device has received Set Features with feature code CCh prior to a reset, setting is reverted to the power on default.
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10.1.1. Register Initialization

After POR, Hard Reset or Soft Reset, the register values are initialized as shown in the following table.
Table 45 Default Register Values

Register Error Sector Count LBA Low LBA Mid LBA High Device Status Alternate Status Default Value Diagnostic Code 01h 01h 00h 00h 00h 50h 50h
The meaning of the Error register diagnostic codes resulting from POR, Hard Reset or the Execute Device Diagnostic command are shown in the following table.
Table 46 Diagnostic Codes

Code 01h 02h 03h 04h 05h 8xh Description No error detected Formatter device error Sector buffer error ECC circuitry error Controller microprocessor error Device 1 failed
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10.2.
Power off Considerations
10.2.1. Required Power off Sequence

Problems can occur on most HDDs when power is removed at an arbitrary time. Examples; 1. Data loss from the write cache which is not written to the media. 2. If the drive is writing a sector, the sector is partially written with an incorrect ECC. It is recommended to use the following sequence to avoid these problems to occur. 1. Issue Standby Immediate command (or Standby or Sleep command). 2. Wait until command complete status is returned. (It takes typically 500 ms.) 3. Terminate the power to HDD This power down sequence should be followed in any system power down, system suspend or system hibernation sequence. In a robustly designed system, emergency unload is limited to rare scenarios such as battery removal during operation.
10.2.2. Emergency Unload

When HDD power is interrupted while the heads are still loaded, the drive firmware can not operate and the normal 3.3V power is unavailable to unload the heads. In this case, normal controlled unload is not possible, the heads are unloaded by the current charge in capacitors on the drive. The actuator velocity is greater than the normal case, and the unload process is inherently less controllable without a normal seek current profile. Emergency unload is intended to be invoked in rare situations. Because this operation is inherently uncontrolled, it is more mechanically stressful than a normal unload.
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10.3.
Sector Addressing Mode
10.3.1. Logical CHS Addressing Mode

The logical CHS addressing is made up of three fields: the cylinder number, the head number and the sector number. Sectors are numbered from 1 to the maximum value allowed by the current CHS translation mode but can not exceed 255 (FFh). Heads are numbered from 0 to the maximum value allowed by the current CHS translation mode but can not exceed 15 (Fh). Cylinders are number from 0 to the maximum value allowed by the current CHS translation mode but can not exceed 65535 (FFFFh). When the host selects a CHS translation mode using the Initialize Drive Parameters command, the host requests the number of sector per logical track and the number of head per logical cylinder. The device then computes the number of logical cylinders available in requested mode. The current CHS translation mode, as well as the default CHS translation mode, is returned by the Identify Device Information.
10.3.2. LBA Addressing Mode (28 bit address)

Logical sectors on the device is linearly mapped with the first LBA addressed sector (sector 0) being the same as the first logical CHS addressed sector (cylinder 0, head 0, sector 1). On LBA addressing mode (28 bit address), the LBA value is set to the following registers: Register Device LBA High LBA Mid LBA Low
LBA bits LBA bits LBA bits LBA bits
27-24 23-16 15- 8 7- 0
10.3.3. LBA Addressing Mode (48 bit address)

The 48-bit Addressing Feature set is supported to allow capacities up to 281,474,976,710,655 sectors (144,115,188,075,855,360 bytes). The Features, Sector Count, LBA Low/Mid/High register are each a two byte deep FIFO. Each time one of these registers is written, the new content written is placed into the most recently written location and the previous content of the register is moved to previous content location. The host may read the previous content of the Sector Count, LBA Low, LBA Mid, and LBA High registers by first setting the HOB bit of the Device Control register to one and then reading the desired register. If the HOB bit in the Device Control register is cleared to zero the host reads the most recently written content when the register is read. A write to any Command Block register causes the device to clear the HOB bit to zero in the Device Control register. The most recently written content always gets written by a register write regardless of the state of the HOB bit. Register Previous Current LBA bits 47-40 LBA bits 23-16 LBA High LBA bits 39-32 LBA bits 15- 8 LBA Mid LBA bits 31-24 LBA bits 7- 0 LBA Low Sector bits 15-8 Sector bits 7-0 Sector Count Support of the 48-bit Address feature set is indicated in the Identify Device command response bit 10 word 83. In addition, the maximum user LBA address accessible by 48-bit addressable commands is contained in Identify Device response words 100 through 103.
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10.4.
Power Management Feature
The power management feature set is supported to modify the behavior in a manner which reduces the power required to operate. The drive implements the following set of functions. 1. Standby Timer 2. Idle Command 3. Idle Immediate Command 4. Standby Command 5. Standby Immediate Command
10.4.1. Power Mode

Standby Mode Idle Mode The device interface is capable of accepting commands, but as the media may not immediately accessible, there is a delay while waiting for the spindle to reach operating speed. Refer to the section of Advanced Power Management Feature.
Active Mode The device is in execution of a command or accessing the disk media with read look-ahead function or write cache function.
10.4.2. Power Management Commands

The Check Power Mode command allows a host to determine if a device is currently in the Standby mode. The Idle and Idle Immediate commands move a device to the idle mode immediately from the active or Standby modes. The Idle command also sets the Standby Timer count and starts the Standby Timer. The Standby and Standby Immediate commands moves a device to Standby mode immediately from the active or idle modes. The Standby command sets and starts the Standby Timer.
10.4.3. Standby Command Completion Timing

1. Confirm the completion of writing cached data in the buffer to media 2. Unload heads on the ramp 3. Set DRDY bit and DSC bit in the Status register 4. Set INTRQ (completion of the command) 5. Activate the spindle break to stop the spindle motor 6. Wait until spindle motor is stopped 7. Perform post process
10.4.4. Standby Timer

The Standby Timer provides a method for the device to automatically enter Standby mode from either active or idle mode following a host programmed period of inactivity. If the device is in the active or idle mode, the device waits for the specified time period and if no command is received, the device automatically enters the Standby mode. If the value of Sector Count register on Idle or Standby command is set to 00h, the device sets the Standby Timer to 109 minutes. If the advanced power management level is less than 0x80, which is power on default, the transition timing to enter the Standby mode is determined by either the Standby Timer or Adaptive Battery Life Extender algorithm, whichever meets the condition first.
10.4.5. Status
In the active, idle and Standby modes, the device sets DRDY bit of the Status register. If BSY bit is not set, the device is ready to accept any command.
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10.4.6. Interface Capability for Power Modes

Each power mode affects the physical interface as defined in the following table: Mode Active Idle Standby Sleep BSY x 0 0 0 DRDY x 1 1 1 Interface active Yes Yes Yes Yes Media Active Active Inactive Inactive
Table 10-47 Power Conditions

The device may post DRDY bit in the Status register even if the media is not be accessible at the time.
10.4.7. Initial Power Mode at Power On

The device powers up in the Idle mode.
10.5.
Advanced Power Management Feature
The Advanced Power Management Feature set is supported to save power without performance degradation. The Adaptive Battery Life Extender 3 (ABLE-3) technology intelligently manages transition among power modes within the device by monitoring access patterns of the host. This technology has three idle modes; Performance Idle, Active Idle and Low Power Idle. This feature allows the host to select an advanced power management level. The advanced power management level is a scale from the lowest power consumption setting of 01h to the maximum performance level of FEh. Device performance may increase with increasing advanced power management levels. Device power consumption may increase with increasing advanced power management levels. The advanced power management levels contain discrete bands, described in the section of Set Features command in detail. This feature set uses the following functions: A Set Features subcommand to enable Advanced Power Management A Set Features subcommand to disable Advanced Power Management The Advanced Power Management feature is independent of the Standby Timer setting. If both Advanced Power Management level and the Standby Timer are set, the device will go to the Standby state when the timer times out or the device's Advanced Power Management algorithm indicates that it is time to enter the Standby state. The Identify Device response word 83, bit 3 indicates that Advanced Power Management feature is supported. Word 86, bit 3 indicates that Advanced Power Management is enabled if set. Word 96, bits 7-0 contain the current Advanced Power Management level if Advanced Power Management is enabled.
10.5.1. Performance Idle Mode

This mode is usually entered immediately after Active mode command processing is complete, instead of conventional idle mode. In Performance Idle mode, all electronic components remain powered and full frequency servo remains operational. This provides instantaneous response to the next command.
10.5.2. Active Idle Mode

In this mode, power consumption is less than that of Performance Idle mode. Additional electronics are powered off, and the head is parked near the mid-diameter without servo control. Recovery time to Active mode is about 10 ms.
10.5.3. Low Power Idle Mode

Power consumption is less than that of Active Idle mode. The heads are unloaded on the ramp, however the spindle is still rotated at the full speed. Recovery time to Active mode is about 300 ms.
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10.5.4. Transition Time

The transition time is dynamically managed by recent access pattern of the user, instead of fixed times. The ABLE-3 algorithm monitors the interval between commands. The algorithm supposes that next command will come with the same command interval distribution as the previous access pattern. The algorithm calculates the expected average saving energy and response delay for next command in several transition time case based on this assumption. And it selects the most effective transition time with the condition that the calculated response delay is shorter than the value calculated from the specified level by Set Feature command. The optimal time to enter Active Idle mode is variable depending on the users recent behavior. It is not possible to achieve the same level of Power savings with a fixed entry time into Performance Idle because every users' data and access pattern is different. The optimum entry time changes over time. The same algorithm works for entering into Low Power Idle mode and Standby mode, which consumes less power but need more recovery time switching from this mode to Active mode.
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10.6.
SMART Function
The intent of Self-Monitoring, Analysis and Reporting Technology (SMART) is to protect user data and prevent unscheduled system downtime that may be caused by predicable degradation and/or fault of the drive. By monitoring and storing critical performance and calibration parameters, the drive employs sophisticated data analysis algorithms to predict the likelihood of near-term degradation or fault condition, the host system can warn the user of impending risk of data loss and advise the use of appropriate action. Since SMART utilizes the internal resource of the drive, there may be some small overhead associated with its operation. However, special care has been taken in the design of SMART algorithm to minimize the impact to host system performance. To further ensure minimal impact to the user, the drives are shipped from the manufacturer s factory with the SMART feature disabled.
10.6.1. Attribute Values

Attribute values are used to represent the relative reliability of individual performance or calibration attributes. Higher attribute values indicate that the analysis algorithms being used by the drive are predicting a lower probability of a degrading or fault condition existing. Accordingly, lower attribute values indicate that the analysis algorithms being used by the drive are predicting higher probabilities of a degrading or fault condition existing. There is no implied linear reliability relationship corresponding to the numerical relationship between different attribute values for any particular attribute.
10.6.2. Attribute Thresholds

Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition. The numerical value of the attribute thresholds are determined by the device manufacturer through design and reliability testing and analysis. Attribute thresholds are set at the device manufacturer s factory and can not be modified in the field. The valid range for attribute threshold is from 1 through 253 decimal.
10.6.3. Threshold Exceeded Condition

If one or more attribute value are less than or equal to their corresponding attribute thresholds, then the device reliability status is negative, indicating an impending degrading or faulty condition.
10.6.4. SMART Commands

The SMART commands provide access to attribute values, attribute thresholds and other logging and reporting information.
10.6.5. SMART Operation with Power Management

The drive saves attribute values automatically on head unload timing except the emergency unload, even if the attribute auto save feature is not enabled. The head unload is done not only by Standby, Standby Immediate, or Sleep command or Hard Reset, but also by the automatic power saving functions like ABLE-3 or Standby Timer.
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10.7.
Write Cache Function
Write cache is a performance enhancement whereby the device reports completion of a write command to the host as soon as the device has received all of the data into its buffer. The device assumes responsibility to write the data subsequently onto the disk. While writing data after completed acknowledgment of a write command, Soft Reset or Hard Reset does not affect its operation. But power off terminates writing operation immediately and unwritten data are to be lost. Flush Cache (EXT), Standby, Standby Immediate, Sleep commands and Soft Reset are executed after the completion of writing to disk media on enabling write cache function. So the host system can confirm the completion of write cache operation by issuing these commands.
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10.8.
Reassign Function
The Reassign Function is used with read and write commands. The sectors of data for reassignment are prepared as the spare data sector. The number of entries of spare sectors is 3687. One entry can register up to 255 consecutive sectors. This reassignment information is registered internally, and the information is available right after completing the reassign function. Also the information is used on the next power on reset or hard reset. If the number of the spare sector reaches 0, the reassign function will be disabled automatically. The spare tracks for reassignment are located at regular interval. As the result of reassignment, the physical location of logically sequenced sectors will be dispersed.
10.8.1. Auto Reassign Function

The sectors that show some errors may be reallocated automatically when specific conditions are met. The conditions for auto reallocation are described below. Uncorrectable write errors When a write operation can not be completed after the Error Recovery Procedure (ERP) is fully carried out, the sector(s) are reallocated to the spare location. An error is reported to the host system only when the write cache is disabled and the auto reallocation fails. If the number of available spare sectors reaches 16 sectors, the write cache function will be disabled automatically. Uncorrectable read errors When a read operation fails after the ERP is fully carried out, a hard error is reported to the host system. The error location is registered internally as a candidate for the reallocation. When the registered location is specified as a target of a write operation, a sequence of media verification is performed automatically. When the result of this verification meets the criteria, this sector is reallocated. Recovered read errors When a read operation for a sector recovered at the specific ERP step, this sector of data is reallocated automatically. A media verification sequence is performed to the relocation.
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11.
Command Descriptions
11.1. Check Power Mode(E5h/98h)

Table 48 Check Power Mode Command
Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 1 1 6 1 5 1 1 4 D 0 3 0 2 1 1 0 0 1 Command Block Input Registers Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
See Below V V V V V V V V -
See Below
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN 0 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY 0 5 DF 0
Status Register
4 DSC 3 DRQ 2 obs 0 1 obs 0 0 ERR V
The Check Power Mode command allows the host to determine the current power mode of the device. Input Parameters From The Device Sector Count The power mode code. The command returns FFh in the Sector Count register if the spindle motor is at speed and the device is not in Standby or Sleep mode. Otherwise, the Sector Count register will be set to 0.
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11.2.
Execute Device Diagnostic (90h)

Command Block Input Registers 1 0 0 0 Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
Table 49 Execute Device Diagnostic command

Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 1 1 6 0 5 1 0 4 1 3 0 2 0
See Below -
See Below Status Register
Error Register
7 ICRC 0 6 UNC V 5 0 V 4 IDN V 3 0 V 2 ABT V 1 T0N V 0 AMN V 7 BSY 0 6 DRDY 0 5 DF 0
4 DSC -
3 DRQ -
2 obs 0
1 obs 0
0 ERR 0
The Execute Device Diagnostic command performs the internal diagnostic tests implemented by the device. The result of the test is stored in the Error register. The Error register contains a diagnostic code. Refer to the section of Register Initialization.
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11.3.
Flush Cache (E7h)

Table 50 Flush Cache Command

Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 1 1 6 1 5 1 1 4 D 0 3 0 2 1
See Below -
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN 0 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
This command causes the device to complete writing data from its write cache. The device returns a status, DRDY=1 and DSC=1 (50h), after the data in the write cache is written to the media.
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11.4.
Flush Cache EXT (EAh)

Table 51 Flush Cache EXT Command

See Below -
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
This command causes the device to complete writing data from its write cache. The device returns a status, DRDY=1 and DSC=1 (50h), after the data in the write cache is written to the media.
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11.5.
Identify Device (ECh)

Table 52 Identify Device Command

See Below -
Error Register
4 DSC -
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Identify Device command requests the device to transfer configuration information to the host. The device will transfer a sector to the host containing the information in the following tables.
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Table 53 Identify Device Data Structure
Word Address 0 1 2 3 6 7-9 10-19 20 21 22 23-26 27-46 47 49 50 51 52 53 54 55 56 57-58
Default Value 045Ah xxxx 0000h 0010h 003Fh 0000h xxxx 0003h 0155h 00xxh xxxx xxxx 8020h 0F00h 4000h 0200h 0000h 0007h xxxx xxxx xxxx xxxx
Total Bytes 2 2 2 2 2 6 20 4 2 2 8 40 2 2 2 2 2 2 2 2 2 4
Data Field Type Information Drive Classification Obsolete (default number of cylinders) Reserved Obsolete (default number of heads) Obsolete (default number of sectors per track) Reserved Serial number in ASCII (Right justified) Obsolete Obsolete Obsolete (# of ECC bytes as currently selected via the Set Features command) Vendor specific Firmware revision in ASCII Model number in ASCII (Left Justified) Maximum number of sectors on Read/Write Multiple command Capabilities Capabilities Obsolete Obsolete Translation parameters are valid Obsolete (current numbers of cylinders) Obsolete (current numbers of heads) Obsolete (current sectors per track) Obsolete (current capacity in sectors)
Note: Obsolete , Retired , Should be used in tables of this page and the following pages are status of these fields/bits in ATA-7. These fileds/bits may have values as in the older ATA specifications.
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Table 54 Identify Device Data Structure
59 60-61 62 63 64 65 66 67 68 69-79 80 81 82 83 84 85 86 87 88 89-90 91 92-255
01xxh xxxx 0000h 0x07h 0003h 0078h 0078h 0078h 0078h 0000h 00FCh 0000h 7069h 7408h 6002h 7068h 3408h 6002h 0x07h 0000h 40xxh xxxx
2 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 4 2
Multiple sector setting Total number of sectors addressable in LBA mode Obsolete Multiword DMA transfer capability Flow Control PIO transfer modes supported Minimum Multiword DMA transfer cycle time (ns) Manufacturer's recommended Multiword DMA transfer cycle time Minimum PIO transfer cycle time without flow control Minimum PIO transfer cycle time with IORDY flow control Reserved Major Version Number Minor Version Number Command Set supported Command Set supported Command Set/Feature supported Extent ion Command Set/Feature Enabled Command Set/Feature Enabled Command Set/Feature Enabled Ultra DMA Transfer Capability Reserved Current Advanced Power Management Level Not used
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C3K80 (PATA) Hard Disk Drive Specification Word 0: General Configuration Bit 15 0 1 = ATAPI device, 0 = ATA device 14 0 Retired 13 0 Retired 12 0 Retired 11 0 Retired 10 1 Retired 9 0 Retired 8 0 Retired 7 0 1 = removable cartridge device 6 1 Obsolete 5 0 Retired 4 1 Retired 3 1 Retired 2 0 1 = Identify data incomplete 1 1 Retired 0 0 reserved Word 9 - 10: Device Serial Number This field contains the serial number of the device. The contents of this field are right justified and padded with ASCII spaces (20h). Word 23 - 26: Firmware Revision This field contains the revision of the firmware in ASCII. Word 27 - 46: Model Number This field contains the model number of the device. The contents of this field are left justified and padded with ASCII spaces (20h). Type Model Name C3K80-80 Hitachi HTC368080H8CE00 C3K80-60 Hitachi HTC368060H8CE00 C3K80-40 Hitachi HTC368040H5CE00 C3K80-30 Hitachi HTC368030H5CE00 Word 49: Capabilities Bit 15-14 0 Reserved 13 0 0 = Standby Timer value is vendor specific 12 0 Reserved 11 1 1 = IORDY supported 10 1 1 = IORDY can be disabled 9 1 1 = LBA mode supported 8 1 1 = DMA transfer supported 7-0 0 Reserved Word 50: Capabilities Bit 15 0 0 = Contents of word 50 are valid 14 1 1 = Contents of word 50 are valid 13-1 0 Reserved 0 0 1 = the device has minimum Standby Timer value that is device specific
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C3K80 (PATA) Hard Disk Drive Specification Word 53:Translation parameters are valid Bit 15-3 0 Reserved 2 1 1 = the fields reported in Word 88 are valid 1 1 1 = the fields reported in Words 64-70 are valid 0 1 Obsolete Word 59: Multiple Sector Setting Bit 15-9 0 Reserved 8 1 1 = Multiple sector setting is valid 7-0 XX XXh =Current setting for number of sectors transferred per interrupt on R/W multiple command Word 63: Multiword DMA Transfer Capability Bit 15-11 0 Reserved 10 X 1 = Multiword DMA mode 2 is selected 9 X 1 = Multiword DMA mode 1 is selected 8 X 1 = Multiword DMA mode 0 is selected 7-3 0 Reserved 2 1 1 = Multiword DMA mode 2 is supported 1 1 1 = Multiword DMA mode 1 is supported 0 1 1 = Multiword DMA mode 0 is supported Word 64: Flow Control PIO Transfer Modes Supported Bit 15-2 0 Reserved 1 1 1 = the device supports PIO mode 4 0 1 1 = the device supports PIO mode 3 Word 80: Major Version Number Bit 15-8 0 Reserved 7 1 1 = the device supports ATA/ATAPI-7 6 1 1 = the device supports ATA/ATAPI-6 5 1 1 = the device supports ATA/ATAPI-5 4 1 1 = the device supports ATA/ATAPI-4 3 1 Obsolete 2 1 Obsolete 1 0 Obsolete 0 0 Reserved Word 81: Minor Version Number Bit 15-0 0000h 0000h or FFFFh = device does not report version
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C3K80 (PATA) Hard Disk Drive Specification Word 82: Command Sets Supported Bit 15 0 Reserved 14 1 1 = NOP command supported 13 1 1 = Read Buffer command supported 12 1 1 = Write Buffer command supported 11 0 Reserved 10 0 1 = Host Protected Area feature Set supported 9 0 1 = Device Reset command supported 8 0 1 = Service interrupt supported 7 0 1 = release interrupt supported 6 1 1 = look-ahead supported 5 1 1 = write cache supported 4 0 1 = PACKET command feature set supported 3 1 1 = Power Management feature set supported 2 0 1 = Removable Media feature set supported 1 0 1 = Security Mode feature set supported 0 1 1 = SMART feature set supported Word 83: Command Sets supported Bit 15 0 0 = should be 0 14 1 1 = should be 1 13 1 1 = Flush Cache EXT command supported 12 1 1 = Flush Cache command supported 11 0 1 = Device Configuration Overlay feature set supported 10 1 1 = 48 bit Address feature set supported 9 0 1 = Automatic Acoustic Management feature set supported 8 0 1 = Set Max security extension supported 7 0 reserved 6 0 1 = Set Feature subcommand required to spinup after power up 5 0 1 = Power up in Standby feature set supported 4 0 1 =Removable Media status Notification feature set supported 3 1 1 = Advanced Power Management feature set supported 2 0 1 = CFA feature set supported 1 0 1 = Read/Write DMA Queued supported 0 0 1 = Download Microcode command supported
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C3K80 (PATA) Hard Disk Drive Specification Word 84: Command Sets Supported Extension Bit 15 0 0 = should be 0 14 1 1 = should be 1 13 1 1 = Idle Immediate with Unload feature supported 12 0 Reserved 11 0 Reserved 10 0 1 = URG bit supported for Write Stream (DMA) EXT 9 0 1 = URG bit supported for Read Stream (DMA) EXT 8 0 1 = 64 bit World wide name supported 7 0 1 = Write DMA Queued FUA EXT command supported 6 0 1 = Write DMA FUA EXT and Write Multiple FUA EXT supported 5 0 1 = General Purpose Logging feature set supported 4 0 1 = Streaming feature set supported 3 0 1 = Media Card Pass Through command feature set supported 2 0 1 = Media serial number supported 1 1 1 = SMART self-test supported 0 0 1 = SMART error logging supported Word 85: Command Set/Feature Enabled Bit 15 0 Obsolete 14 1 1 = NOP command enabled 13 1 1 = Read Buffer Command enabled 12 1 1 = Write Buffer Command enabled 11 0 Obsolete 10 0 1 = Host Protected Area Feature set supported 9 0 1 = Device Reset command supported 8 0 1 = Service interrupt enabled 7 0 1 = release interrupt enabled 6 X 1 = Look-Ahead enabled 5 X 1 = Write Cache enabled 4 0 1 = PACKET command feature set supported 3 1 1 = Power Management feature set enabled 2 0 1 = Removable Media feature set enabled 1 0 1 = Security Mode feature set enabled 0 X 1 = SMART feature set enabled
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C3K80 (PATA) Hard Disk Drive Specification Word 86: Command Set/Feature Enabled Bit 15-14 0 Reserved 13 1 1 = Flush Cache EXT command supported 12 1 1 = Flush Cache command supported 11 0 1 = Device Configuration Overlay supported 10 1 1 = 48 bit Address feature set supported 9 0 1 = Automatic Acoustic Management feature set enabled 8 0 1 = Set Max security extension enabled by Set Max Set Password 7 0 reserved 6 0 1 = Set Feature subcommand required to spinup after power up 5 0 1 = Power up in Standby feature set enabled 4 0 1 =Removable Media status Notification feature set enabled 3 X 1 = Advanced Power Management feature set enabled 2 0 1 = CFA feature set enabled 1 0 1 = Read/Write DMA Queued supported 0 0 1 = Download Microcode command supported Word 87: Command Set/Feature default Bit 15 0 0 = should be 0 14 1 1 = should be 1 13 1 1 = Idle Immediate with Unload feature supported 12 0 Reserved 11 0 Reserved 10 0 1 = URG bit supported for Write Stream (DMA) EXT 9 0 1 = URG bit supported for Read Stream (DMA) EXT 8 0 1 = 64 bit World wide name supported 7 0 1 = Write DMA Queued FUA EXT command supported 6 0 1 = Write DMA FUA EXT and Write Multiple FUA EXT supported 5 0 1 = General Purpose Logging feature set supported 4 0 1 = Valid Configure Stream command has been executed 3 0 1 = Media Card Pass Through command feature set enabled 2 0 1 = Media serial number is valid 1 1 1 = SMART self-test supported 0 0 1 = SMART error logging supported Word 88: Ultra DMA Transfer Capability Bit 15-11 0 Reserved (Ultra DMA mode 3 or above not supported) 10 X 1 = Ultra DMA mode 2 is selected 9 X 1 = Ultra DMA mode 1 is selected 8 X 1 = Ultra DMA mode 0 is selected 7-3 0 Reserved (Ultra DMA mode 3 or above not supported) 2 1 1 = Ultra DMA mode 2 and below are supported 1 1 1 = Ultra DMA mode 1 and below are supported 0 1 1 = Ultra DMA mode 0 and below are supported Word 91: Current Advanced Power Management Level Bit 15-8 40h Obsolete 7-0 XXh Current Advanced Power Management level set by Set Features Command (01h FEh)
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11.6.
Idle (E3h/97h)
Command Block Input Registers 1 0 Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
Table 55 Idle Command

Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 -
See Below -
V V V V V V V V 1 1 1 1 1 D 0 0 0 1 1
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Idle command causes the device to enter Idle mode immediately, and sets and starts the Standby Timer. When the Idle mode is entered, the device is spun up to operating speed. If the device is already spinning, the spin up sequence is not executed. During Idle mode, the device is spinning and ready to respond to host command immediately. Sector Count Output Parameters To The Device Standby Timer value. If zero, the Standby Timer is set for 109 minutes. If other than zero, the Standby Timer is set for (value x 5) seconds. The device will enter Standby mode automatically if the Standby Timer expires with no device access from the host. The Standby Timer value will be reinitialized if there is a device access before the timer expires.
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11.7.
Idle Immediate (E1h/95h)

Table 56 Idle Immediate Command

See Below -
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Idle Immediate command causes the device to enter Idle mode. The device is spun up to operating speed. If the device is already spinning, the spin up sequence is not executed. During Idle mode, the device is spinning and ready to respond to host commands immediately. The Idle Immediate command does not affect the Standby Timer.
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11.8.
Idle Immediate with Unload (E1h)

Command Block Input Registers 1 0 0 0 1 0 0 0 0 0 0 0 1 1 Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 1 1 7 6 5 4 3 2 1 0 -
Table 57 Idle Immediate Command with Unload

Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 0 0 0 0 0 1 1 6 1 0 1 1 1 1 5 0 0 0 0 0 1 1 4 0 0 0 0 1 D 0 3 0 0 1 1 0 0 2 1 0 1 1 1 0
See Below 0 0 0 1 0 0 -
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Idle Immediate command with Unload option causes the device to immediately unload the heads. Although the time to complete the unload operation is vendor specific, the typical value is within 500 ms of receiving the command. The device will stay at Low Power Idle mode, will not go into Standby mode and will not load the heads until receiving a new command.
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11.9.
Initialize Device Parameters (91h)

Command Block Input Registers 1 0 Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
Table 58 Initialize Device Parameters Command

Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 -
See Below -
V V V V V V V V 1 1 0 1 0 -
D H H H H 1 0 0 0 1
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN 0 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY 0 5 DF 0
4 DSC -
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Initialize Device Parameters command enables the host to set the number of sectors per track and the number of heads minus 1 per cylinder. The words 54-58 in Identify Device Information reflect these parameters. The parameters remain in effect until the following events; Another Initialize Device Parameters command is received The device is powered off Hard reset occurs Soft reset occurs and the Set Features option of CCh is set. Sector Count H Output Parameters To The Device The number of sectors per track. 0 does not mean there are 256 sectors per track, but there is no sector per track. The number of heads minus 1 per cylinder. The minimum is 0 and the maximum is 15.
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11.10. Read Buffer (E4h)

Table 59 Read Buffer Command
See Below -
Error Register
4 DSC -
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Buffer command transfers a sector of data from the device s buffer to the host. The sector transferred will be the same part of the buffer written to by the last Write Buffer command. The contents of the sector may be different if any reads or writes have occurred since the Write Buffer command was issued.
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11.11. Read DMA (C8h)

Table 60 Read DMA Command
Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 6 5 4 3 2 1 0 Command Block Input Registers Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
See Below V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V H H H H
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 1 1 1 1 0 D H H H H 0 1 0 0 0
Error Register
7 ICRC V 6 UNC V 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN V 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read DMA command reads one or more sectors of data from disk media, and then transfers the data from the device to the host. The host initializes a slave-DMA channel prior to issuing the command. The data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only on interrupt per command to indicate that data transfer has terminated and status is available. If an un-correctable error occurs, the read will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
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11.12. Read DMA EXT (25h)

Table 61 Read DMA EXT Command
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 1 0 0 1 1 D H H H H 0 0 1 0 1
Error Register
7 ICRC V 6 UNC V 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN V 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read DMA EXT command reads one or more sectors of data from disk media, and then transfers the data from the device to the host. The host initializes a slave-DMA channel prior to issuing the command. The data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only on interrupt per command to indicate that data transfer has terminated and status is available. If an un-correctable error occurs, the read will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
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11.13. Read Long (22h)

Table 62 Read Long Command
Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 1 Command Block Input Registers Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
See Below V
V V V V V V V V V V V V V V V V V V V V V V V V 1 0 L 0 1 1 D H H H H 0 0 0 1 0
V V V V V V V V V V V V V V V V V V V V V V V V H H H H
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN V 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Long command reads the designated one sector of data and the ECC bytes from the disk media, and then transfers the data and ECC bytes from the data and ECC bytes from the device to the host. After 512 bytes of data have been transferred, the device will keep setting DRQ=1 to indicate that the device is ready to transfer the ECC bytes to the host. The ECC bytes are transferred 8 bits at a time. The number of ECC bytes is 4 or 51 according to the setting of Set Feature option. The default setting is 4 bytes of ECC data. It should be noted that the device internally uses 51 bytes of ECC data on all data written or read from the disk. The 4 bytes mode of operation is provided for emulation. It is recommended that for testing the effectiveness and integrity of the device ECC functions that the 51 byte ECC mode should be used. The command makes a single attempt to read the data and does not check the data using ECC. Whatever is read is returned to the host. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
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11.14. Read Multiple (C4h)

Table 63 Read Multiple Command
V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V 1 1 L 1 1 0 D H H H H 0 0 1 0 0
Error Register
7 ICRC 0 6 UNC V 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN V 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Multiple command reads one or more sectors of data from disk media, and then transfers the data from the device to the host. The execution of the command is identical to the Read Sectors command except that an interrupt is generated for each block (as defined by the Set Multiple Mode command) instead of each sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
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11.15. Read Multiple EXT (29h)

Table 64 Read Multiple EXT Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Multiple EXT command reads one or more sectors of data from disk media, and then transfers the data from the device to the host. The execution of the command is identical to the Read Sectors EXT command except that an interrupt is generated for each block (as defined by the Set Multiple Mode command) instead of each sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
99/129
11.16. Read Sectors (20h)

Table 65 Read Sectors Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Sectors command reads one or more sectors of data from disk media, and then transfers the data from the device to the host. If an un-correctable error occurs, the read will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
100/129
11.17. Read Sectors EXT (24h)

Table 66 Read Sectors EXT Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Sectors EXT command reads one or more sectors of data from disk media, and then transfers the data from the device to the host. If an un-correctable error occurs, the read will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
101/129
11.18. Read Verify Sectors (40h)

Table 67 Read Verify Sectors Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Verify Sectors command verifies one or more sectors on the device. No data is transferred to the host. The difference of Read Sectors command and Read Verify Sectors command is whether the data is transferred to the host or not. If an un-correctable error occurs, the read verify will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
102/129
11.19. Read Verify Sectors EXT (42h)

Table 68 Read Verify Sectors EXT Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Read Verify Sectors EXT command verifies one or more sectors on the device. No data is transferred to the host. The difference of Read Sectors EXT command and Read Verify Sectors EXT command is whether the data is transferred to the host or not. If an un-correctable error occurs, the read verify will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
103/129
11.20. Recalibrate (1Xh)

Table 69 Recalibrate Command
Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 7 1 0 6 0 5 1 0 4 D 1 3 2 1 0 Command Block Input Registers Register Data Error Sector Count LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
See Below -
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN 0 3 0 0 2 ABT V 1 T0N V 0 AMN 0 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 COR 0
1 IDX 0
0 ERR V
The Recalibrate command moves the read/write heads from anywhere on the disk to cylinder 0. If the device can not reach cylinder 0, T0N (Track 0 Not Found ) will be set in the Error Register.
104/129
11.21. Seek (7Xh)

Table 70 Seek Command
See Below -
V V V V V V V V V V V V V V V V V V V V V V V V 1 0 L 1 1 1 D H H H H 1 -
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Seek command initiates a seek to the designated track and selects designated head.
105/129
11.22. Sense Condition (F0h:Vendor Unique)

Table 71 Sense Condition Command
See Below V V V V V V V V D -
V V V V V V V V V V V V V V V V V V V V V V V V 1 1 1 1 1 D 1 0 0 0 0
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN 0 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY V 6 DRDY V 5 DF 0
4 DSC V
3 DRQ -
2 obs -
1 obs 0
0 ERR V
The Sense Condition command is used to sense temperature in a device. This command is executable without spinning up. Output Parameters To The Device Features The Features register must be set to 01h. All other value are rejected with setting ABRT bit in the Status register. Input Parameters From The Device Sector Count The Sector Count register contains result value. Value Description 00h Temperature is equal to or lower than -20 degC 01h-FEh Temperature is (Value / 2 - 20) deg C FFh Temperature is higher than 107 degC
106/129
11.23. Sense Drive Temperature (FAh:Vendor Unique)

Table 72 Sense Drive Temperature Command
See Below V V V V V V V V D -
V V V V V V V V V V V V V V V V V V V V V V V V 1 1 1 1 1 D 1 1 0 1 0
Error Register
4 DSC V
3 DRQ -
2 obs -
1 obs 0
0 ERR V
The Sense Drive Temperature command is used to sense temperature in a device. This command is executable without spinning up. Output Parameters To The Device Features The Features register must be set to 00h. All other value are rejected with setting ABRT bit in the Status register. Input Parameters From The Device Sector Count The Sector Count register contains temperature reading (added 32 in order to avoid minus values)
107/129
11.24. Set Features (EFh)

Table 73 Set Features Command
Command Block Output Registers Register Data Features Sector Count LBA Low LBA Mid LBA High Device Command 1 1 1 1 1 7 6 5 4 3 2 1 0 Command Block Input Registers Register Data Error Sector Count 1 1 1 LBA Low LBA Mid LBA High Device Status 7 6 5 4 3 2 1 0 -
V V V V V V V V Note. 1 D 0 1
See Below -
Error Register
4 DSC -
3 DRQ -
2 COR 0
1 IDX 0
0 ERR V
The Set Features command establishes the following parameters which affect the execution of certain features as shown in below table by the value in the Features register. ABT will be set to 1 in the Error register if the Features register contains any unsupported value.
Table 74 Supported Features

Value 02h 03h 05h 44h 55h 66h 82h 85h AAh BBh CCh Operation Enable Write Cache Set transfer mode Enable Advanced Power Management Obsolete (Product specific ECC bytes (51 bytes) apply on Read/Write Long commands) Disable Read Look Ahead Disable reverting to power on defaults at Soft Reset Disable Write Cache Disable Advanced Power Management Enable Read Look Ahead Obsolete (4 bytes of ECC apply on Read/Write Long commands) Enable reverting to power on defaults at Soft Reset
Values 02h, 05h, AAh and BBh are the default features for the device, thus the host does not have to issue this command with these features unless it is necessary for compatibility reasons. Values 66h and CCh can be used to enable and disable whether the power on defaults will be set when a Soft Reset 108/129
C3K80 (PATA) Hard Disk Drive Specification occurs. The value 05h is used for advanced power management. The Sector Count register specifies the advanced power management level as below. The advanced power management level at POR is 60h. 80h FEh : Up to Low Power Idle mode 01h 7Fh : Up to Standby mode 00h, FFh : Reserved The value 85h is used to disable advanced power management.
109/129
11.25. Set Multiple Mode (C6h)

Table 75 Set Multiple Mode Command
See Below -
V V V V V V V V 1 1 1 1 0 D 0 0 1 1 0
Error Register
4 DSC -
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Set Multiple Mode command enables the device to perform Read and Write Multiple (EXT) commands and establishes the block size for these commands. The block size is the number of sectors to be transferred for each interrupt. The default block size after POR, or Hard Reset is 0, and Read Multiple and Write Multiple (EXT) commands are disabled. If an invalid block size is specified, and ABT bit in the Error register to indicate the command is aborted. Read Multiple and Write Multiple (EXT) commands will be disabled. Output Parameters To The Device Sector Count The block size to be used for Read Multiple and Write Multiple (EXT) commands. Valid block sizes can be selected from 0, 1, 2, 4, 8 or 16. If 0 is specified, then Read Multiple and Write Multiple (EXT) commands are disabled.
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11.26. Sleep (E6h/99h)

Table 76 Sleep Command
See Below -
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Sleep command causes the device to enter the Sleep mode immediately. When this command is issued, the device confirms the completion of the cached write commands before it asserts INTRQ. Then the device is spun down. If the device is already spun down, the spin down sequence is not executed. It is not required to use Soft Reset or Hard Reset to recover from the Sleep mode, but the device goes out from the Sleep mode by a host command.
111/129
11.27. SMART Function Set (B0h)

Table 77 SMART Function Set Command
V V V V V V V V V V V V V V V V 0 1 1 1 1 1 0 0 0 0 1 1 0 0 D 1 1 0 0 1 0 0 1 1 0 1 0 0
See Below -
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs -
0 ERR V
The SMART Function Set command provides access to Attribute Values, Attribute Thresholds and other low level subcommands that can be used for logging and reporting purpose and to accommodate special user needs. The SMART Function Set command has several separate subcommands which are selectable via the Features register when the SMART Function Set command is issued by the host.
112/129
C3K80 (PATA) Hard Disk Drive Specification In order to select a subcommand the host must write the subcommand code to the Features register before issuing the SMART Function Set command. The subcommand and their respective codes are listed below.
Table 78 SMART Subcommands

SMART Read Attribute Values SMART Read Attribute Threshold SMART Enable/Disable Attribute Autosave code D0h D1h D2h Description This sub-command returns the Attribute Value to the host. The total size of Attribute Values is 512 bytes. This sub-command returns the Attribute Threshold Value to the host. The total size of Attribute Threshold Values is 512 bytes. This sub-command enables/disables the attribute autosave feature of the device. A value of 00h in Sector Count register while this sub-command is being issued causes Attribute Autosave feature disabled. A value of F1h in Sector Count Register while this sub-command is being issued causes Attribute Autosave feature enabled. Any other Sector Count Register value will not change the current state of Autosave feature. However, regardless of the state of autosave feature, the device may perform saving SMART attributes when it makes transition to Standby mode or Sleep mode. The SMART disable operations sub-command also disables the autosave feature along with device s SMART operation. This sub-command causes the device to immediately initiate the set of activities that collect Attribute data in an off-line mode or execute a self-test routine in either captive or off-line mode. The contents of the LBA Low register direct the device which operation to be executed. LBA Low Operation to be executed 0h Execute SMART off-line data collection immediately 1h Execute SMART Short self-test immediately in off-line mode 2h Execute SMART Extended self-test immediately in off-line mode 7Fh Abort off-line mode self-test. 81h Execute SMART Short self-test immediately in captive mode 82h Execute SMART Extended self-test immediately in captive mode Off-line mode: The device posts command completion before executing the specific test. During execution of the operation, the device will not post BSY. If the execution of the operation is interrupted by a new command from the host, the device will abort or suspend the operation and will service the new command as soon as possible. After servicing interrupting command, the device will resume the operation or not start the operation depending on the interrupting command Captive mode: The device executes the operation after receipt of the command. At the end of operation, the device reports the execution result in self-test execution status byte and ATA registers as below. Status ERR bit set when self-test has failed Error ABT bit set when self-test has failed LBA Mid F4h when self-test has failed LBA Hign 2Ch when self-test has failed
SMART Execute Off-line Immediate
D4h
113/129
SMART Enable Operations
SMART Disable Operations SMART Return Status
C3K80 (PATA) Hard Disk Drive Specification D8h This sub-command enables access to all SMART capabilities within the device. The state of SMART will be preserved by the device across power cycle. Once enabled, the receipt of subsequent SMART Enable Operations sub-command will not affect any of the Attribute Values. D9h This sub-command disables all SMART capabilities within the device. The state of SMART will be preserved by the device across power cycle. DAh This sub-command is used to communicate the reliability status of the device to the host s request. If the device does not detect a Threshold Exceeded Condition but involving attributes are advisory, the device loads 4Fh into the LBA Mid register and C2h into the LBA High register respectively. If the device detects a Threshold Exceeded Condition for prefailure attributes, the device loads F4h into the LBA Mid register and 2Ch into the LBA High register respectively.
Device Attribute Data Structure The following table describes the 512 byte Attribute Value information being accessed by the host using SMART Read Attribute Values sub-command. All multi-byte fields shown in these data structures follow the ATA/ATAPI-7 specification for byte ordering, namely that the least significant byte occupies the lowest numbered byte address location the field.
Table 79 SMART Device Attribute Data Structure

Description Data Structure Revision Number 1 Device Attribute .. 30 Device Attribute Offline data collection status Self-test execution status Total time in seconds to complete off-line data collection activity
th st
Offset 0 2
Size (bytes) 2 12
350 362 363 364
12 1 1 2
Current segment pointer Off-line data collection capability SMART capability SMART device error logging capability Self-test failure check point Short self-test completion time in minutes Extended self-test completion time in minutes Reserved Vendor Specific Data structure check sum
366 367 368 370 371 372 373 374 386 511
1 1 2 1 1 1 1 12 125 1
114/129
C3K80 (PATA) Hard Disk Drive Specification Individual Attribute Data Structure The following table describes the 12 byte each attribute entry in the device attribute data structure.
Table 80 SMART Individual Attribute Data Structure

Description Attribute ID Number Status Flags Bit 15-6 5-2 1 0 Attribute Value Value 00h 01h FDh FEh FFh Reserved Reserved (00h) Description = 0 Reserved Reserved On-line collection Pre-failure/Advisory 3 Description
Invalid value not to be referred Minimum value Maximum value Value is not valid Invalid value not to be referred
Offset 0 1
Size (bytes) 1 2
4 11
7 1
Attribute ID Numbers
Table 81 SMART Attribute ID ID 0 1 3 4 5 7 8 9 10 12 192 193 194 196 197 199 220 Description Indicates this entry in the data structure is not used Raw Read Error Rate Spin Up Time Start/Stop Count Reallocated Sector Count Seek Error Rate Seek Time Power On Hours Spin Retry Count Power Cycle Count Power Off Retract Count Load/Unload Cycle Count Device Temperature Reallocation Event Count Current Pending Sector Count Ultra DMA CRC Error Count Disk Shift Value Pre-failure
115/129
11.28. Standby (E2h/96h)

Table 82 Standby Command
See Below -
V V V V V V V V 1 1 1 1 1 D 0 0 0 1 0
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Standby command causes the device to enter the Standby mode immediately, and sets the Standby Timer. When this command is issued, the device confirms the completion of the cached write commands before it asserts INTRQ. Then the device is spun down, but the interface remains active. If the device is already spun down, the spin down sequence is not executed. During the Standby mode, the device will respond to commands, but there is a delay while waiting for the spindle to reach operating speed. The timer starts counting down when the device returns to Idle mode. Output Parameters To The Device Standby Timer value. If zero, the Standby Timer is set to 109 minutes. If other than Sector Count zero, the timer is set to (value x 5) seconds. When the automatic power down sequence is enabled, the device will enter the Standby mode automatically if the timer expires with no device access from the host. The timer will be reinitialized if there is a device access before the timer expires.
116/129
11.29. Standby Immediate (E0h/94h)

Table 83 Standby Immediate Command
See Below -
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Standby Immediate command causes the device to enter the Standby mode Immediately. When this command is issued, the device confirms the completion of the cached write commands before asserts INTRQ. Then the device is spun down, but the interface remains active. If the device is already spun down, the spin down sequence is not executed. During the Standby mode, the device will respond to commands, but there is a delay while waiting for the spindle to reach operating speed. The Standby Immediate command will not affect the Standby Timer.
117/129
11.30. Write Buffer (E8h)

Table 84 Write Buffer Command
See Below -
Error Register
4 DSC -
3 DRQ -
2 COR 0
1 IDX 0
0 ERR V
The Write Buffer command transfers a sector of data from the host to the sector buffer of the device. The Read Buffer and Write Buffer commands are synchronized such that sequential Write Buffer and Read Buffer commands access the same 512 byte within the buffer.
118/129
11.31. Write DMA (CAh)

Table 85 Write DMA Command
Error Register
7 ICRC V 6 UNC 0 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY V 5 DF V
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write DMA command transfers one or more sectors of data from the host to the device, and then the data is written to the disk media. The host initializes a slave-DMA channel prior to issuing the command. Data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one interrupt per command to indicate that data transfer has terminated and status is available. If an un-correctable error occurs when write cache feature is disabled, the write will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
119/129
11.32. Write DMA EXT (35h)

Table 86 Write DMA EXT Command
Error Register
7 ICRC V 6 UNC 0 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY V 5 DF V
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write DMA EXT command transfers one or more sectors of data from the host to the device, and then the data is written to the disk media. The host initializes a slave-DMA channel prior to issuing the command. Data transfers are qualified by DMARQ and are performed by the slave-DMA channel. The device issues only one interrupt per command to indicate that data transfer has terminated and status is available. If an un-correctable error occurs when write cache feature is disabled, the write will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
120/129
11.33. Write Long (32h)

Table 87 Write Long Command
See Below V
V V V V V V V V V V V V V V V V V V V V V V V V 1 0 L 0 1 1 D H H H H 1 0 0 1 0
Error Register
7 ICRC 0 6 UNC 0 5 0 0 4 IDN V 3 0 0 2 ABT V 1 T0N 0 0 AMN 0 7 BSY 0 6 DRDY V 5 DF V
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write Long command transfers the data and the ECC bytes of the designated one sector from the host to the device, and then the data and the ECC bytes are written to the disk media. After 512 bytes of data have been transferred, the device will keep setting DRQ=1 to indicate that the device is ready to receive the ECC bytes from the host. The ECC bytes are transferred 8 bits at a time. The number of ECC bytes is 4 or 51 according to setting of Set Feature option. The default number after power on is 4 bytes. The device internally uses 51 bytes of ECC on all data read or writes. The 4 byte mode of operation is provided via emulation technique. As a consequence of this emulation, it is recommended that 51 byte ECC mode is used for all tests to confirm the operation of device ECC hardware. Unexpected result may occur if such testing is performed using 4 byte mode.
121/129
11.34. Write Multiple (C5h)

Table 88 Write Multiple Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write Multiple command transfers one or more sectors from the host to the device, and then the data is written to the disk media. The execution of command is identical to the Write Sectors command except that an interrupt is generated for each block (as defined by the Set Multiple Mode command) instead of for each sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
122/129
11.35. Write Multiple EXT (39h)

Table 89 Write Multiple EXT Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write Multiple EXT command transfers one or more sectors from the host to the device, and then the data is written to the disk media. The execution of command is identical to the Write Sectors EXT command except that an interrupt is generated for each block (as defined by the Set Multiple Mode command) instead of for each sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
123/129
11.36. Write Sectors (30h)

Table 90 Write Sectors Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write Sectors command transfers one or more sectors from the host to the device, and then the data is written to the disk media. If an un-correctable error occurs when write cache feature is disabled, the write will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
124/129
11.37. Write Sectors EXT (34h)

Table 91 Write Sectors EXT Command
Error Register
4 DSC V
3 DRQ -
2 obs 0
1 obs 0
0 ERR V
The Write Sectors EXT command transfers one or more sectors from the host to the device, and then the data is written to the disk media. If an un-correctable error occurs when write cache feature is disabled, the write will be terminated at the failing sector. Refer to the section of Sector Addressing Mode for Sector Count, LBA Low/Mid/High and Device registers.
125/129
11.38. Write Verify (3Ch, Vendor Unique)

In HTC3680XXHXCE00 implementation, Write Verify command is exactly same as Write Sectors command (30h). No read verification is performed after write operation. Refer to Write Sectors Command for parameters.
126/129
11.39. Error Posting

The following table summarizes the valid status and error value for all supported command set. V=Valid on this command
Table 92 Error Reporting

Error Register UNC IDNF ABRT V Status Register DRDY DF ERR V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
COMMAND Check Power Mode Execute Device Diagnostic Flush Cache (EXT) Identify Device Idle Idle Immediate Initialize Device Parameters Read Buffer Read DMA (EXT) Read Long Read Multiple (EXT) Read Sectors (EXT) Read Verify Sectors (EXT) Recalibrate Seek Sense Condition Sense Drive Temperature Set Features Set Multiple Mode Sleep SMART Function Set Standby Standby Immediate Write Buffer Write DMA (EXT) Write Long Write Multiple (EXT) Write Sectors (EXT) Write Verify
ICRC
AMNF
V V V V
V V V V V V
V V V V V
V V V V V
127/129
12.
Timings
The timing of BSY and DRQ in Status Register are shown in the following figure. The other timings are described in the Part 1 Functional Specification.
Table 93 Timeout Values

FUNCTION Power On INTERVAL Device Busy After Power On Device Ready After Power On Device Busy After Software Reset Device Ready After Software Reset Device Busy After Hard Reset Device Ready After Hard Reset Device Busy After Command Code Out Interrupt, DRQ For Data Transfer In Device Busy After Command Code Out Interrupt For Data Transfer Out Device Busy After Command Code Out Interrupt For Command Complete Device Busy After Command Code Out Power On Power On Device Control Register RST=1 Device Control Register RST=0 after RST=1 Bus RESET Signal Asserted Bus RESET Signal Asserted OUT to Command Register Status Register BSY=1 OUT to Command Register Status Register BSY=1 OUT to Command Register Status Register BSY=1 Out to Command Register START STOP Status Register BSY=1 Status Register BSY=0 and RDY=1 Status Register BSY=1 Status Register BSY=0 and RDY=1 Status Register BSY=1 Status Register BSY=0 and RDY=1 Status Register BSY=1 Status Register BSY=0 and DRQ=1 Interrupt Status Register BSY=1 Status Register BSY=0 and RDY=1 Interrupt Status Register BSY=1 Interrupt Status Register BSY=1 TIMEOUT 400 ns
31 sec 400 ns 31 sec 400 ns 31 sec 400 ns 30 sec
Software Reset
Hard Reset
Data In Command
Data Out Command
400 ns 30 sec
Non-Data Command
400 ns 30 sec 400 ns
DMA Data Transfer Command
Command category is referred to "8 Parallel ATA Command Protocol " on page 59. We recommend that the host system executes Soft reset and then retry to issue the command if the host system timeout would occur for the device.
128/129
Copyright Hitachi Global Storage Technologies Hitachi Global Storage Technologies 5600 Cottle Road San Jose, CA 95193 Produced in the United States 12/06
Microsoft, Windows XP, and Windows are trademarks of Microsoft Corporation in the United States, other countries, or both. Other product names are trademarks or registered trademarks of their respective companies. References in this publication to Hitachi Global Storage Technologies products, programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates. Product information is provided for information purposes only and does not constitute a warranty. Information is true as of the date of publication and is subject to change. Actual results may vary. This publication is for general guidance only. graphs may show design models. 22 December 2006 Photo-
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C3K80 (PATA) Hard Disk Drive Specification

Hitachi Global Storage Technologies

Hard Disk Drive Specification

Revision 1.0 22 Dec 2006

C3K80 (PATA) Hard Disk Drive Specification

OUTLINE OF THE DRIVE ........................................................................................................... 12

C3K80 (PATA) Hard Disk Drive Specification

C3K80 (PATA) Hard Disk Drive Specification

C3K80 (PATA) Hard Disk Drive Specification

Drive handling precautions

Do not press on the drive cover during handling.

C3K80 (PATA) Hard Disk Drive Specification

2. Outline of the drive

Advanced Power Management (APM)

C3K80 (PATA) Hard Disk Drive Specification

Part 1 Functional Specification

C3K80 (PATA) Hard Disk Drive Specification

3. Fixed disk subsystem description

The control electronics works with the following functions:

Head disk assembly data

The following technologies are used in the drive:

C3K80 (PATA) Hard Disk Drive Specification

4. Fixed disk characteristics

Table 1: Formatted capacity by model number

HTC368040H5CE00 512 436-873 2 1 16 63 16,383 78,140,160 40,007,761,920

HTC368030H5CE00 512 336-672 2 1 16 63 16,383 58,605,120 30,005,821,440

Table 2: Data sheet

C3K80 (PATA) Hard Disk Drive Specification

Adaptive formats are adopted. Typical format is described below.

Table 3: Cylinder allocation (40GB/p format)

C3K80 (PATA) Hard Disk Drive Specification

Table 4: Cylinder allocation (30GB/p format)

C3K80 (PATA) Hard Disk Drive Specification

Table 5: Performance characteristics

14 15 3600 3.0 1.0 288 max 33

C3K80 (PATA) Hard Disk Drive Specification

4.4.1.1 Average seek time (including settling)

4.4.1.2 Full stroke seek

C3K80 (PATA) Hard Disk Drive Specification

4.4.1.4 Average latency

4.4.1.5 Drive ready time

C3K80 (PATA) Hard Disk Drive Specification

4.4.2.1 Description of operating modes

Low power idle Standby Sleep

4.4.2.2 Operating mode at power on

4.4.2.3 Adaptive power save control

C3K80 (PATA) Hard Disk Drive Specification

Data buffer test

C3K80 (PATA) Hard Disk Drive Specification

Nonrecovered write errors

Nonrecoverable read error

Recovered read errors

C3K80 (PATA) Hard Disk Drive Specification

C3K80 (PATA) Hard Disk Drive Specification

Table 11: Environmental condition

The maximum storage period in the shipping package is one year.

C3K80 (PATA) Hard Disk Drive Specification

HDMARDY1 HSTROBE 1 IORDY DDMARDY1 DSTROBE 1 INTRQ 30 O 27 O