Hardware Design with VHDL

VHDL III

ECE 443

Sequential Logic A sequential circuit contains memory. Our focus is on synchronous sequential circuits -- those whose memory elements are controlled by a global clock. The most basic storage element is a D-ip-op (DFF). A positive edge-triggered DFF samples the value on d on the rising edge of clk. May contain an asynchronous reset signal which sets the FF to 0. The VHDL code that infers a DFF is as follows: library ieee; use ieee.std_logic_1164.all; entity d_ff is port( clk: in std_logic; d: in std_logic; q: out std_logic; ); end d_ff; ECE UNM 1 (9/16/08)

Hardware Design with VHDL DFF

VHDL III

ECE 443

architecture arch of d_ff is begin process(clk) begin if (clkevent and clk=1) then q <= d; end if; end process; end arch; The sensitivity list ONLY includes clk, i.e., the process does not activate when d changes. The rising edge is checked with clkevent and clk=1 expression. event indicates a change in the clk signal. The clk = 1 indicates a rising edge. If either of these is false, q maintains its current value (is not updated). Note the absence of the else statement. ECE UNM 2 (9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

DFF with Asynchronous Reset A DFF with asynchronous reset is used for system initialization. library ieee; use ieee.std_logic_1164.all; entity d_ff_reset is port( clk, reset: in std_logic; d: in std_logic; q: out std_logic; ); end d_ff_reset; architecture arch of d_ff_reset is begin process(clk, reset) begin if (reset = 1 ) then q <= 0;

ECE UNM

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

DFF with Asynchronous Reset elsif (clkevent and clk=1) then q <= d; end if; end process; end arch; Note that reset is in the sensitivity list and has higher priority than the rising edge of clk. Another option is to include an enable signal. library ieee; use ieee.std_logic_1164.all; entity d_ff_en_reset is port( clk, reset: in std_logic; en: in std_logic; d: in std_logic;

ECE UNM

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

DFF with Enable and Asynchronous Reset q: out std_logic; ); end d_ff_en_reset; architecture arch of d_ff_en_reset is begin process(clk, reset) begin if (reset = 1 ) then q <= 0; elsif (clkevent and clk=1) then if (en = 1) then q <= d; end if; end if; end process; end arch;

ECE UNM

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

DFF with Enable and Asynchronous Reset/Register Synthesis: d 0 d_next D 1 Q q

q_reg

clk reset

Register: A collection of DFFs controlled by same clock and reset signal. entity reg_reset is port( clk, reset: in std_logic; d: in std_logic_vector(7 downto 0); q: out std_logic_vector(7 downto 0); ); end reg_reset;

ECE UNM

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

Register/Register File architecture arch of reg_reset is begin process(clk, reset) begin if (reset = 1 ) then q <= (others => 0); -- equiv to "00000000" elsif (clkevent and clk=1) then q <= d; end if; end process; end arch; Register File: Consists of a collection of registers with: one input port one or more output ports a write address, w_addr, to indicate where to store data a r_addr to specify where to read data from

ECE UNM

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

Register File library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity reg_file is generic( B: integer:=8 -- number of bits/register W: integer:=2 -- number of registers (addr. bits) ); port( clk, reset: in std_logic; wr_en: in std_logic; w_addr, r_addr: in std_logic_vector(W-1 downto 0); w_data: in std_logic_vector(B-1 downto 0); r_data: out std_logic_vector(B-1 downto 0); ); end reg_file;

ECE UNM

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

Register File architecture arch of reg_file is type reg_file_type is array (2**W-1 downto 0) of std_logic_vector(B-1 downto 0); signal array_reg: reg_file_type; begin process(clk, reset) begin if (reset = 1) then array_reg <= (others =>(others=>0)); elsif (clkevent and clk=1) then if (wr_en = 1) then array_reg(to_integer(unsigned(w_addr))) <= w_data; end if; end if; end process; r_data <= array_reg(to_integer(unsigned(r_addr))); end process; ECE UNM 9 (9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

Register File/Design Examples New features: Since there is no 2-D array dened in std_logic_1164, a user-dened array-of-array data type, reg_le_type, is dened using the type construct. Access to the register array is done using array_reg(...w_addr...) with the appropriate type conversion of the argument. Note that in many FPGAs, special distributed RAMs exist so that the DFF in the CLBs are not needed. Typically these are specied using as a core, which we will cover soon.

ECE UNM

10

(9/16/08)

Hardware Design with VHDL

VHDL III

ECE 443

FSMs: Example library ieee; use ieee.std_logic_1164.all; entity fsm_eg is port( clk, reset: in std_logic; a, b: in std_logic; y0, y1: out std_logic; ); end fsm_eg; architecture two_seq_arch of fsm_eg is type eg_state_type is (s0, s1, s2); signal state_reg, state_next: eg_state_type; begin process(clk, reset) begin

ECE UNM

11

(9/16/08)

Hardware Design with VHDL FSMs: Example

VHDL III

ECE 443

if (reset = 1) then state_reg <= s0; elsif (clkevent and clk = 1) then state_reg <= state_next; end if; end process; process(state_reg, a, b) begin state_next <= state_reg; y0 <= 0; -- default 0 y1 <= 0; case state_reg is when s0 => if a = 1 then if b = 1 then state_next <= s2; y0 <= 1; ECE UNM 12 (9/16/08)

Hardware Design with VHDL FSMs: Example

VHDL III

ECE 443

else state_next <= s1; end if; end if; when s1 => y1 <= 1; if a = 1 then state_next <= s0; end if; end case; end process; end two_seg_arch;

ECE UNM

13

(9/16/08)