Logical Circuit Gate Sizing using MPSO guided by

Logical Effort An Examination of the 12-Stage

Ripple Carry Adder Circuit
*A. Johari, *M. K. Mohd Salleh, *A.K. Halim *I.M. Yassin, *S. Mohamed and **H.A. Hassan
*Faculty of Electrical Engineering, Universiti Teknologi Mara (UiTM), Shah Alam, Malaysia
**Faculty of Engineering, Universiti Selangor (UNISEL), Bestari Jaya, Malaysia
muham34653@yahoo.com.my


AbstractAutomated Complementary Metal Oxide
Semiconductor (CMOS) logic circuit design leads to the
reduction in costs associated with manpower and manufacturing
time. Conventional methods use repetitive manual testing guided
by Logical Effort (LE). LE provides an easy way to compare and
select circuit topologies, choose the best number of stages for
path and estimate path delay. In this paper, we propose the
Mutative Particle Swarm Optimization (MPSO) algorithm as a
method to automate the process of CMOS circuit design by
approaching the design process as an optimization problem. In
our work, we choose gate widths inside the circuit as parameters
to be optimized in order to achieve the target delay, and its
fitness is guided by the LE method. Various parameters, such as
swarm size and iterations were tested under different
initialization conditions to verify MPSOs performance on a 12-
stage ripple carry adder circuit. Results have indicated that the
MPSO algorithm was an effective method to apply to the circuit
design problem, with high convergence rates observed.
Keywords-Logical Effort, Automated circuit design, Particle
swarm optimization, Mutative Particle swarm optimization, ripple
carry adder
I. INTRODUCTION
Logical Effort (LE) [1] is a method for fast evaluation of
delays in logic paths. This method is a straightforward
technique to estimate delay and to choose the best number of
stages in a Complementary Metal Oxide Semiconductor
(CMOS) circuits [2]. LE has since been adopted as a basis for
many Computer-Aided Design (CAD) tools. It helps designer
to quickly estimate the minimum possible delay in a circuit,
and to choose the appropriate gate sizes to achieve this delay.
However, the sizing process still requires repetitive tests by the
designer to achieve the desired delay [3].
In this paper, the application of the Mutative Particle
Swarm Optimization (MPSO) algorithm is proposed as an
alternative method for automated means for CMOS circuit
design. We extend the works in [4, 5], but apply it to a more
complex circuit topology.
PSO is a population-based stochastic optimization
technique based on Swarm Theory (ST) and Evolutionary
Computation (EC) [6]. It is inspired by the seemingly
intelligent swarming behavior of animals in nature [7]. PSO
has a successful track record in solving many optimization
problems [8-12]. The algorithm is simple and computationally
inexpensive, yet fast and efficient [13-16].
This paper is organized as follows: Some previous works
are presented in Section II. The theoretical background to the
proposed approach is presented in Section III. The
experimental setup is presented in Section IV, and the results
and discussions are presented in Section V. Finally, Section VI
presents the conclusions.
II. PREVIOUS WORKS
A. Logical Effort (LE)
Circuit delay is an important factor to consider in digital
circuit design. Failure to consider the delay may lead to circuit
malfunctions and non-compliance to timing specifications.
Such failures are called delay faults [17].
The LE method [3] has been introduced to allow for both
quick and accurate analysis of digital circuit design. LE defines
the overall circuit delay in concrete mathematical terms,
combined to a linear Resistance-Capacitance (RC) delay mode
[3]. This method can be used for comparative analysis of
existing circuits, as well as to guide transistor sizing and
estimate the optimal number of stages in the circuit.
B. Adders and previous works on adders
Fast adders are widely used in CMOS circuits as part of the
Arithmetic-Logic Unit (ALU). Various types of adders have
been designed: half-adder, full-adder and ripple-carry adder.
All adders offer different tradeoffs between delay, area, and
power consumption. Analytical delay models help designers
evaluate these tradeoffs, but simply counting logic levels is
inadequate because circuit delay also depends on fan-out [18].
Previous works on adders design involves increasing its
speed by adjusting its topologies [19], gate width and routing
[18] and others. Modification of gate widths [2] is preferable
because only minor modifications need to be made to existing
circuit libraries. Hence, we extended this method of resizing
transistors to cover ripple carry adder in the critical path. This
extension is important as the goal of our performance analysis
is to have the best possible delay product in automated process.
Ripple carry adders are the basic building blocks for ALU
either in microprocessor or microcontroller (Figure 1). It
This work is sponsored by Universiti Teknologi Mara, Malaysia
2011 IEEE Colloquium on Humanities, Science and Engineering Research (CHUSER 2011), Dec 5-6 2011, Penang
978-1-4673-0020-9/11/$26.00 2011 IEEE 425
consists of 4 full adders in series where the su
bit-A and bit-B will generates (Sum) and (Co
FA
A
0
B
0
FA
A
0
B
0
C
o,0
=C
i,1
FA
A
0
B
0
C
o,1
=C
i,2
C
o,2
=C C
i,0
S
0 S
1
S
2
Figure 1 4-bit Ripple Carry Add

C. Particle Swarm Optimization (PSO)
PSO is a population-based stocha
technique inspired by animal swarming beha
The exploration of the solution space is per
agents called particles. The solution is
competitive and cooperative behavior of agen
The original PSO algorithm genera
continuous-form. The algorithm is simple an
inexpensive, yet fast and efficient [7, 14-16].
PSO has a successful track record
optimization problems [20]. Since PSO age
parallel in nature, PSO allows efficient and fa
the problem [21]. Furthermore, PSO req
mathematical operators (plus, minus and mu
optimization [7]. It is memory-inexpensive [
parameters need to be stored to update
Another benefit of PSO is that it r
computational and memory costs for each iter
III. THEORETICAL BACKGRO
A. Implementation of Logic Gate at Transist
Transistors form the basis of any logic
these transistors can be arranged of ways to
logic function. A list of several logic gate i
shown in Table I.
TABLE I. TRANSISTOR-LEVEL IMPLEMENTATIO
Symbol T
I
n
v
e
r
t
e
r


B
u
f
f
e
r


N
A
N
D


N
O
R



This work is sponsored by Universiti Teknologi Ma
ummation between
out).
FA
A
0
B
0
C
i,3
C
o,3
S
3

er
stic optimization
avior in nature [8].
rformed by simple
achieved by the
nts.
ates solutions in
nd computationally

in solving many
ents (particles) are
fast optimization of
quires only basic
ultiply) to perform
[16], as only a few
future iterations.
requires constant
ration [14].
OUND
tor Level
c gate. In CMOS,
perform a desired
implementations is
ON OF LOGIC GATES
Transistor Level


Transistors are annotated w
units so that each pull down st
[18]. The size of these
characteristics of the logic gate
in a logic circuit, these transisto
achieve the desired circuit delay
B. The Ripple Carry Adder Lo
A ripple carry adder is a l
addition, and is implemented u
Table I.
The core of ripple carry add
is composed of two half adder
and produces two outputs Sum
carry adder is build from 4 fu
delay quite slow because each
previous finished [22]. An imp
adder is shown in Figure 2.
Figure 2 Modified 4
C. Logical Effort (LE)
The logical effort LE is the
the gate input to the input cap
with the same unit effective re
logical effort and parasitic delay
adder circuit. The parasitic del
the total transistor width on
diffusion and gate capacitance a
TABLE II. LE & PARASITIC DEL
ADDER
Logic
Gate
Number
of Input
Inverter 1
Buffer 1
NAND 2
NOR 2

The single stage delay (J),
adding the stage effort () and p
J =
where stage effort () is
electrical effort of the gates (b)
ara, Malaysia
with widths measured in arbitrary
tack has unit effective resistance
transistors affects the delay
e. When the gates are combined
ors must be sized accordingly to
y.
ogic Circuit
logic circuit that performs 4-bit
using the logic gates described in
der is 1-bit full adder which itself
rs that takes two inputs, A and B
m and C
out
. Since 4-bit ripple
ull adders, it makes the adders
full adder has to wait until the
plementation of the ripple carry

-bit Ripple Carry Adder
ratio of the input capacitance of
acitance (3 units) of an inverter
esistance [18]. Table II lists the
y of each gate in the ripple carry
lay (p) is estimated by counting
n the output node, assuming
are approximately equal [18].
LAY OF LOGIC GATES IN MODIFIED FULL
CIRCUIT
Logical
Effort
Parasitic
Delay
1 1
1 1
4/3 2
4/3 2
as shown in (1) is measured by
parasitic delay (p) together :
= + p (1)

the product of logical (g)and
) as shown in (2) :
2011 IEEE Colloquium on Humanities, Science and Engineering Research (CHUSER 2011), Dec 5-6 2011, Penang
426
For each particle:
1) Do a velocity update as directed by Eq. (5).
2) Modify the particle position as Eq. (6).
3) Check the particle value, xid:
a) If the value is more than xMax, then pull
the value of xid back to xMax, and set vid
to 0 to stop searching in that direction.
b) If the value is less than xMin, then pull
the value of xid back to xMin, and set vid
to 0 to stop searching in that direction.
4) Rescale the solution using Eq. (7) and
evaluate the fitness function.
5) Compare particles fitness with gBest. If the
fitness is better than gBest, then update
gBest with the new fitness value.
6) Kill off half of the particle population with
the worst fitness, then replace them with
mutated versions of gBest using Eq. (8).
7) Resume optimization for next particle at 1).
8) Finish optimization either when the maximum
iterations reached, or when the objective has
been met
= g b (2)

The electrical effort of the gates (b) were effected by ratio
of fan out (Cout) and fan in (Cin) in terms of capacitance as
shown in (3) :

b = CoutCin (3)

Eq. (1) can be extrapolated to cater for multi-stage circuits.
In the case of multi-stage circuits, must be multiplied by the
branching effort (b) :

b = (C
on
+ C
o]]
)C
on
(4)

where C
on
is the capacitance in the critical path, and C
o]]
is
the capacitance which doesnt lay in the critical path. The
branching effort (b) is important in multistage design, because
it allows us to model a branch in a given network as its single-
path equivalent. Eq. (1) thus becomes:

= 0BE + P (5)

where the uppercase letters denote multi-stage application.
To find the minimum path delay, F
mn
, the effort for each stage
must be equal. This is done by substituting the Eq. (3) into Eq.
(2). Re-arranging Eq. (2) produces:
C
n
= 0 CoutFmin (6)

Once C
n
is known, this value can be distributed among
transistors in the stage.
D. The PSO algorithm
PSO is a population-based stochastic optimization
algorithm inspired by animal swarming behavior in nature [8].
PSO iteratively searches for solutions in the problem space by
taking advantage of the cooperative and competitive behavior
of simple agents called particles.
The constriction factor variant of the PSO (PSO
CF
)
algorithm was used in this paper due to its superior
convergence properties. PSO
CF
improves particle convergence
by gradually decreasing particle velocities as iterations
progress, so that particle movements near the optimum are
localized.
The PSO
CF
algorithm search is directed by its velocity (I
d
)
which modifies the particles position (X
d
):
I
d
=
_|I
d
+ C
1
(pBcst - X
d
) ronJ
1
C
2
(gBcst - X
d
) ronJ
2
]
(7)

X
d
= X
d
+ I
d
(8)

I
d
= particle velocity.
X
d
= particle position.
pBcst = particles best fitness so far.
gBcst = best solution achieved by the swarm so far.
C
1
= cognition learning rate
C
2
= social learning rate.
ronJ
1
, ronJ
2
= uniformly distributed random numbers
between 0 and 1.
_ =constant set according to C
1
and C
2
.
E. Modifications on PSO
CF
to perform delay optimization
Works by [4, 6] have used a scaling equation to rescale the
particle values in Eq. (8) with significant success in
optimization of discrete variables. In this paper, a similar
method was used. However, since the optimization was done in
continuous form, the scaling equation in [4, 6] was modified by
removing the rounding operator, which produces Eq. (9). Eq.
(9) was originally used in [23] to transform neural network
datasets to between a predefined range:
y = [
(
mcx
-
min
)(-
min
)

mcx
-
min
+ y
mn
(9)
where:
y = particle position.
y
mn
= lowest integer value position.
y
mux
= highest integer value position.
r
mn
= lowest range for continuous-valued solution.
r
mux
= upper range for continuous-valued solution.
F. Particle Mutation
The mutation of particles was used to prevent particles
from being trapped in suboptimal points during search[24].
Consider a swarm with N particles. After the particle positions
have been updated, the worst-performing N/2 particles were
eliminated, and were replaced with mutated versions of gBest.
The mutation was performed by making N/2 copies of gBest,
and adding small random values to them so that they are placed
nearby gBest. Therefore, the new particle positions:
X
d
= gBcst +(mFoctor ronJ
3
) (10)

where rand
3
is a random value between 0 and 1. The
pseudo code for MPSO is shown in Figure 3.
Figure 3 Pseudo code for MPSO algorithm.
2011 IEEE Colloquium on Humanities, Science and Engineering Research (CHUSER 2011), Dec 5-6 2011, Penang
427
IV. METHODOLOGY
A. Description of Experiments
For the problem presented, several experiments were
performed. For half adder experiments, the initial swarm was
uniformly distributed inside [0.3, 5.2]
D
, where D is 4, the
corresponding dimension for the number of gate widths to be
optimized. While, for the full adder experiment, the initial
swarm was distributed inside [0.5, 7]
D
, where D is 8. The
swarm sizes tested is shown in Table III.
For each swarm size, the experiments were repeated 5 times
(using different random initialization values generated using
the Mersenne-Twister Algorithm (MTA). The initial MTA
state (for the first repetition) starts from 0 and increased by
50,000 for next repetitions. This was done to measure the
convergence with different initial particle values, as well as to
ensure repeatability of the experiments. For author/s of only
one affiliation (Heading 3): To change the default, adjust the
template as follows.
TABLE III. SWARM SIZES FOR MPSO OPTIMIZATION
Swarm size Max. Iteration Interval [ymin, ymax]
5 10, 15, 20, 25, 30 [0.3, +5.5]
10 10, 15, 20, 25, 30 [0.3, +5.5]
15 10, 15, 20, 25, 30 [0.3, +5.5]
20 10, 15, 20, 25, 30 [0.3, +5.5]
25 10, 15, 20, 25, 30 [0.3, +5.5]
30 10, 15, 20, 25, 30 [0.3, +5.5]
B. PSO Parameter Setting
For the PSO algorithm, the constriction factor method was
used. The values of C
1
and C
2
were both set to 2.05 [25]. The
minimum and maximum values of X
d
were set to 0 and 1,
respectively, to constrain the particle values between 0 and 1.
The dynamic range of I
d
was set to between -1 (when X
d

moves from 1 to 0) and +1 (when X
d
moves from 0 to 1). The
process of LE optimization can be described with a flow chart
in Figure 4.

Figure 4. Logical Effort Optimization Process
C. Fitness Function
The delay or optimization objective was set to 84.11
where Tau () is a measurement of the response time with
units. This delay can be set according to the requirements of
the circuit design. The delays for several types of E are shown
in Table IV.
TABLE IV. DELAY OF 4-STAGE RIPPLE CARRY ADDER
Electrical Effort (H) Delay
16 84.11
8 76.79
4 70.53
2 65.15
1 60.56

During optimization, the gate widths were set according to
MPSO values, and the corresponding delay is calculated. The
difference between the calculated delay ( J
MPS0
) and the
desired delay (J
dcscd
) was determined as:
itncss = |J
dcscd
- J
MPS0
| (11)

A low fitness value indicates a good solution (as the fitness
minimizes the difference between the desired delay and the
delay calculated using MPSO), and vice versa. This fitness
value was then fed back to the MPSO algorithm for it to
optimize its search in the following iterations.
V. RESULTS & DISCUSSIONS
The convergence of the MPSO algorithm was tested for
different swarm sizes, iterations and initial seeds. For each
swarm size, the experiment was repeated 5 times with different
initial particle values generated using MTA. If MPSO managed
to achieve the optimal value of fitness, the optimization is
considered a success. Else, the optimization is considered a
failure.
From the ripple carry adder circuit in Fig. 1, the path delay
was first minimized with maximum electrical effort in Table
IV. Then we used this minimum delay as our timing constraint
for minimizing area. The best convergences plots of the half
adder delay by using MPSO algorithm are shown in Figure 5
and summarized in Table V.
TABLE V. SUMMARY OF CONVERGENCE PLOT
Result Particles Seed Iteration Difference
Best 1 15 150000 10 9.82 1u
-05
Best 2 25 50000 25 1.S7 1u
-04
Best 3 30 0 20 1.84 1u
-04

Best 4 15 200000 15 2.94 1u
-04
Best 5 5 150000 30 S.S9 1u
-04

From Table V, it can be seen that the swarm size of 15, 10
iterations at seeds equal to 150,000 gave the optimum delay
since it gave the lowest difference between the PSO-optimized
delay and the objective delay which is 9.82 1u
-uS
. The
convergence of MPSO with different swarm sizes was
relatively consistent, indicating that small swarm sizes were
sufficient to approximate the solution to the given problem.
The values of swarm size and iterations are adjustable for more
difficult circuit topologies.
2011 IEEE Colloquium on Humanities, Science and Engineering Research (CHUSER 2011), Dec 5-6 2011, Penang
428

Figure 5. Logical Effort Optimization Process

After optimization, all trials converged to 84.11., which
was the optimal fitness value. All trials managed to find the
optimal gate sizes for all logic gates in the full adder path. This
result indicates that the proposed method has successfully been
implemented to solve the test problem, even with different
initialization values.
TABLE VI. COMPARISON OF CONVERGENCE PLOT BETWEEN MPSO AND
PSO
Result
MPSO PSO
Iteration Difference Iteration Difference
Best 1 10 9.82 1u
-05
10 9.82 1u
-05
Best 2 25 1.S7 1u
-04
15 9.82 1u
-05
Best 3 20 1.84 1u
-04
20 9.82 1u
-05
Best 4 15 2.94 1u
-04
25 9.82 1u
-05
Best 5 30 S.S9 1u
-04
30 9.82 1u
-05

A comparison between the MPSO algorithm with the PSO
algorithm when applied to the 12-stage ripple carry adder
circuit is shown in Table VI. The MPSO method were expected
to find better solution in term of speed(iteration) or
solution(difference) but it can be seen that the best result for
MPSO same like PSO which is 9.82 1u
-05
. This is because
the ripple carry adder circuit has more dimensions where at
every iterations, the worst-performing particle have to be
eliminated hence effected the solutions.
The gate widths, without considering the wire capacitance
for the best case are shown in Figure. 6. As shown in the
figure, the continuous sizing area is expressed in terms of
capacitance. As expected, the areas for the gates are inside the
dimension that has been allocated before. The MPSO
algorithms managed to produce consistent results (indicated by
small different of delay found even with different seeds, swarm
sizes and iterations).

Figure 6. Ripple Carry Adder gate width found using MPSO.
.
VI. CONCLUSION

A novel PSO method by [4-6] was extended to find the
gate widths of an 12-stage Ripple Carry Adder circuit. The
method uses the MPSO algorithm to automatically find the
gate widths for the full adder logic gates based on a predefined
delay. Experiments show that the MPSO method was capable
to solve the LE problem well, even with increased complexity
of the test circuit, with consistent results throughout different
swarm sizes, iterations and initial conditions.
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