SERVICE MANUAL

Model:

PDP 42 73M

Safety Precaution................................................................................1-2 Technical Specifications...................................................................3-10 Block Diagram................................................................................11-12 Circuit Diagram................................................................................13-28 Basic Operations & Circuit Description...........................................29-33 Main IC Specifications....................................................................34-54 Panel Information............................................................................55-67 Spare Part list.................................................................................68-69 Exploded View ................................................................................ . .7 0 If You Forget Your V-CHIP Password .............................................. ..7 1 Software Upgrade...............................................................................72

This manual is the latest at the time of printing, and does not include the modification which may be made after the printing, by the constant improvement of product.

Safety Precaution
CAUTION
RISK OF ELECTRIC SHOCK DO NOT OPEN

The lightning flash with arrowhead symbol, within an equilateral triangle, is intended to alert the user to the presence of uninsulated dangerous voltage within the products enclo sure that may be of sufficient magnitude to constitute a risk of electric shock to persons. The exclamation point within an equilateral triangle is intended to alert the user to the presence of important operating and maintenance (servicing) instructions in the literature accompanying the appliance.

CAUTION: TO REDUCE THE RISK OF ELECTRIC SHOCK, DO NOT REMOVE COVER (OR BACK). NO USER-SERVICEABLE PARTS INSIDE. REFER SERVICING TO QUALIFIED SERVICE PERSONNEL ONLY.

PRECAUTIONS DURING SERVICING

1. In addition to safety, other parts and assemblies are specified for conformance with such regulations as those applying to spurious radiation. These must also be replaced only with specified replacements. Examples: RF converters, tuner units, antenna selection switches, RF cables, noise-blocking capacitors, noise-blocking filters, etc. 2. Use specified internal Wiring. Note especially: 1) Wires covered with PVC tubing 2) Double insulated wires 3) High voltage leads 3. Use specified insulating materials for hazardous live parts. Note especially: 1) Insulating Tape 2) PVC tubing 3) Spacers (insulating barriers) 4) Insulating sheets for transistors 5) Plastic screws for fixing micro switches 4. When replacing AC primary side components (transformers, power cords, noise blocking capacitors, etc.), wrap ends of wires securely about the terminals before soldering.

MAKE YOUR CONTRIBUTION TO PROTECT THE ENVIRONMENT

Used batteries with the ISO symbol for recycling as well as small accumulators (rechargeable batteries), mini-batteries (cells) and starter batteries should not be thrown into the garbage can. Please leave them at an appropriate depot.

WARNING:

Before servicing this TV receiver, read the SAFETY INSTRUCTION and PRODUCT SAFETY NOTICE.

SAFETY INSTRUCTION
The service should not be attempted by anyone unfamiliar with the necessary instructions on this apparatus. The following are the necessary instructions to be observed before servicing. 1. An isolation transformer should be connected in the power line between the receiver and the AC line when a service is performed on the primary of the converter transformer of the set. 2. Comply with all caution and safety related provided on the back of the cabinet, inside the cabinet, on the chassis or picture tube.

5. Make sure that wires do not contact heat generating parts (heat sinks, oxide metal film resistors, fusible resistors, etc.) 6. Check if replaced wires do not contact sharply edged or pointed parts. 7. Make sure that foreign objects (screws, solder droplets, etc.) do not remain inside the set.

3. To avoid a shock hazard, always discharge the picture tube's anode to the chassis ground before removing the anode cap. 4. Completely discharge the high potential voltage of the picture tube before handling. The picture tube is a vacuum and if broken, the glass will explode.

172

5. When replacing a MAIN PCB in the cabinet, always be certain that all protective are installed properly such as control knobs, adjustment covers or shields, barriers, isolation resistor networks etc. 6. When servicing is required, observe the original lead dressing. Extra precaution should be given to assure correct lead dressing in the high voltage area. 7. Keep wires away from high voltage or high tempera ture components. 8. Before returning the set to the customer, always perform an AC leakage current check on the exposed metallic parts of the cabinet, such as antennas, terminals, screwheads,metal overlay, control shafts, etc., to be sure the set is safe to operate without danger of electrical shock. Plug the AC line cord directly to the AC outlet (do not use a line isolation transformer during this check). Use an AC voltmeter having 5K ohms volt sensitivity or more in the following manner. Connect a 1.5K ohm 10 watt resistor paralleled by a 0.15F AC type capacitor, between a good earth ground (water pipe, conductor etc.,) and the exposed metallic parts, one at a time. Measure the AC voltage across the combination of the 1.5K ohm resistor and 0.15 uF capacitor. Reverse the AC plug at the AC outlet and repeat the AC voltage measurements for each exposed metallic part. The measured voltage must not exceed 0.3V RMS. This corresponds to 0.5mA AC. Any value exceeding this limit constitutes a potential shock hazard and must be corrected immediately. The resistance measurement should be done between accessible exposed metal parts and power cord plug prongs with the power switch "ON". The resistance should be more than 6M ohms.
AC VOLTMETER

PRODUCT SAFETY NOTICE

Many electrical and mechanical parts in this apparatus have special safety-related characteristics. These characteristics are offer passed unnoticed by visual spection and the protection afforded by them cannot necessarily be obtained by using replacement components rates for a higher voltage, wattage, etc. The replacement parts which have these special safety characteristics are identified by marks on the schematic diagram and on the parts list. Before replacing any of these components, read the parts list in this manual carefully. The use of substitute replacement parts which do not have the same safety characteristics as specified in the parts list may create shock, fire, or other hazards. 9. Must be sure that the ground wire of the AC inlet is connected with the ground of the apparatus properly.

Good earth ground such as the water pipe, conductor, etc.

Place this probe on each exposed metallic part

AC Leakage Current Check

272

Technical
1.

Specifications

PDP4273M

Standard Test Conditions All tests shall be performed under the following conditions, unless otherwise specified. 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Ambient light Viewing distance Warm up time PDP Panel facing : : : : 150ux (When measuring IB, the ambient luminance 0.1Cd/m2) 50cm in front of PDP 30 minutes no restricted PC, Chroma 2225 signal generator (with Chroma digital additional card) or equivalent, Minolta CA100 photometer no restricted Brightness, Contrast, Tint, Color set at Center(50) 100~120Vac 60Hz

Measuring Equipment : Magnetic field Control settings Power input : : :

Ambient temperature : : :

20C 5C (68F 9F) Resolution 1024 (H) x 1024 (V) Pixels

1.10 Display mode 1.11 Other conditions 1.11.1

With image sticking protection of PDP module, the luminance will descend by time on a same still screen and rapidly go down in 5 minutes. When measuring the color tracking and luminance of a same still screen, be sure t o accomplish the measurement in one minute to ensure its accuracy. Due to the structure of PDP, the extra-high-bright same screen should not hold over 5 minutes for fear of branding on the panel.

1.11.2

372

Technical

Specifications

PDP4273M

ELECTRICAL CHARACTERISTICS 2. Power Input 2.1 2.2 2.3 2.4 2.5 Voltage Input Current Maximum Inrush Current Test condition Frequency Power Consumption Test condition Power Factor Withstanding voltage : : : : : : : : : 100 ~120VAC 5.0 /2.5A <30 A (FOR AC110V ONLY) Measured when switched off for at least 20 mins 60Hz(3Hz) 330W Typical full white display with maximum brightness and contrast Meets IEC1000-3-2 1.5kVac or 2.2kVdc for 1 sec 60Hz

2.6 2.7 3.

Display 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Screen Size Aspect Ratio Pixel Resolution Peak Brightness Contrast Ratio (Dark room) Viewing Angle OSD language : : : : : : : 42 Plasma display 16:9 852x480 1400 cd/m (Typical, Panel only) 3000:1 (Ratio, Typical, in a dark room, Panel only) Over 160 English,French,Spanish.

4.

Signal 4.1 AV & Graphic input 4.1.1 Composite signal 4.1.2 Y,C Signal 4.1.3 Component signal 4.1.4 Graphic I/P 4.1.5EDID compatibility 4.1.6 I/P frequency : : : : : : AV S-Video YPbPr, HDMI,VGA compatible Analog: D-sub 15pin detachable cable Digital:HDMI DDC 1.3 fH: 31.5kHz to 60kHz/fV: 56.25Hz to 75Hz(1024x768 recommended)

472

Technical

Specifications
VGA(D-Sub 15 Pin Type) 1 D-Sub 9 Pin (RS-232 Input) 1 HD MI ( Ver. 1.1 ) connector 1 S-Video (Mini Din 4 Pin) 1 V i d e o Input (RCA Type) 1 YPbPr x 2 Stereo , Audio 6 Audio&Video Output (RCA Type) 1, SPDIF(Optical) x 1
PIP/PBP, Picture size, Picture Still, Sound mode,Last memory, Timer

PDP4273M

4.2 Audio input

4.3 Audio output

5.

Environment 5.1 Operating environment

5.1.1 Temperature : 5.1.2 Relative humidity: 5.2 Storage and Transport 5.2.1 Temperature : 5.2.2 Relative humidity:

5 to 33C 20% to 85%(non-condensing) -20C to 60C(-4 to 140F) 5% to 95%

6.

Panel Characteristics 6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 Type Size : : FHP(A3) 42,932.94mm(W)X532.80mm(H) (W/Ostand) 16:9 Over 160 1024X1024 39.2 kg (Net) 16.7 millions of colors (R/G/B each 256 scales) Average 60:1 (In a bright room with 150Lux at center) Typical 10000:1 (In a dark room 1/100 White Window pattern at center). Typical 1500cd/ (1/25 White Window) Contrast; Brightness and Color control at normal setting Full white pattern Average of point A,B,C,D and E +/- 0.01

Aspect ratio : Viewing angle : Resolution : Weight : Color : Contrast : Peak brightness :

6.10 Color Coordinate Uniformity : Test Pattern :

572

Technical

Specifications
: Contrast at center (50); Brightness center (50); Color temperature set at Natural x=0.2850.02 y=0.2900.02

PDP4273M

6.11 Color temperature

6.12 Cell Defect Specifications Subject to Panel supplier specification as appends. 7. Front Panel Control Button 7.1 SEL. Up / Down Button VOL. Left/Right Button MENU Button SOURCE Button : : : : Select the Up/Down item in OSD menu. Push the key to increase the volume left or right. When selecting the adjusting item in OSD menu increase or decrease the data-bar. Display or Exit the OSD menu. Press this button and use up/down button to sellect the signal sources. AV, S-Video, YPbPr 1,YPbPr 2, VGA or HDMI. Switch on main power, or switch off to enter power Saving modes. Turn on or off the unit.

7.2 7.3 8.

STANDBY Button Main Power Switch

: :

OSD Function

8.1 Picture : Brightness; Contrast; Saturation; Peaking; Phase; Sharpness; Frequency; Picture Mode (Normal, Bright, Cinema, User); Color Temp (Warm, Normal, Cool); etc. 8.2 Window : Image Size (Fill All, Force 4:3, Letter Box, Wide, Anamorphic, etc); H Position; V Position; H Resolution; Freeze Window (Off, On) 8.3 Audio : Balance; Audio Mode (BBE, Cinema, Music, News, User) (Internal, External); AVC (Off, On) Equalizer (120Hz, 500Hz, 1.2kHz, 3kHz, 12kHz) 8.4 Options : Osd Timeout (5 Sec, 15 Sec, 60 Sec); Menu Background (Opaque, Translucent); Language(English, French, Spanish); Default Setting; Close Caption Mode; Close Caption; Content Blocking; Timer 8.5 Layout : Full Screen; PIP; Split Screen

672

Technical Specications
9. Agency Approvals Safety : Emissions : UL, FCC, FDA UL, FCC, FDA

PDP4273M

10. Reliability MTBF : 20,000 hours(Use moving picture signal at 25C ambient) 11. Accessories User manual x1, Remote control x1, Stand x 1, Battery x 2, AC Cable x 1 12. Remote Control 1 Standby( ): Press this button to turn off to standby and turn on from standby. 2 Mute( ): Press this button to quiet the sound system. Press again to reactivate the sound system. 3 P. Still: Press this button to hold on the screen. Press again to normal. 4 P. Size: When the input source is YPbPr 1, YPbPr 2, VGA or HDMI, press this button, the picture will change according to Fill All, Force 4:3, Letter Box, Wide or Anamorphic. When the input source is AV or S-Video, press this button, the picture will change according to Fill All, 4:3, Letter Box, Wide or Anamorphic. 5 S. Sele: Press this button to select the sound output from Main Window or Sub Window. 6 P. Mode : Press the button to select different picture effect. 7 Time: Press this button to pop up the Clock Set menu. 8 Sleep: Press this button to select the sleep time. 9 Display: Press the button to display the source information. 10 Auto: The Display automatically adjusts the phase, vertical / horizontal position when pressing this button in VGA mode. 11 Layout: Press this button to pop up Layout menu. 12 C/C: Press this button to enter the Closed Caption Function. (Only for AV or S-Video) (Continued on next page)

772

Technical Specications

PDP4273M

13 V-Chip: Press this button to enter the V-Chip Function. (Only for AV or S-Video) 14 Number buttons: Use these buttons to enter the password. 15 Swap: Press this button to switch the Main window or Sub window pictures in PIP and Split Screen. 16 F. White: Press this button to show a full white picture. 17 PIP POS. : Press the button to select different Image Position in PIP Mode. 18 PIP Size : Press the button to select different Image Size in PIP Mode. 19 VOL +/- : Press these buttons to increase or decrease the volume. 20 Sound: Press the button to select different sound effect. 21 W. Sele: Press this button to select the Main Window or Sub Window. 22 Source: Press this button and use / button to select the signal sources. AV, S-Video, YPbPr 1, YPbPr 2, VGA or HDMI. 23 PIP: Press this button to change different Picture Mode. 24 Menu: Press this button to pop up the OSD Menu and press it again to exit the OSD Menu. 25 OK : Press to enter or conrm. / : They are used as / buttons in the OSD Menu screen. / : They are used as / buttons in the OSD Menu screen. They also can be used for the selection of the program when the OSD Menu is not shown on the screen, but only for the Model with Tuner.

872

Technical Specications
13. Support the Signal Mode 13.1. VGA Mode, HDMI Mode or HDTV Mode (YPbPr 1 or YPbPr 2) Horizontal Frequency (kHz) 31.50 37.90 48.40 64.00 33.75 45.00 31.468 33.75 45.00 31.468 15.734 Vertical Frequency (Hz) 60.00 60.32 60.00 60.01 60.00 60.00 59.94 60.00 60.00 59.94 59.94

PDP4273M

Mode

Resolution 640 x 480 800 x 600 1024 x 768 1280 x 1024 1080i 720p 480p 1080i 720p 480p 480i

VGA Mode

HDMI Mode

HDTV Mode (YPbPr1/YPbPr2)

Dot Clock Frequency (MHz) 25.18 40.00 65.00 108.00 74.25 74.25 27.00 74.25 74.25 27.00 13.50

13.2.PIP/PBP Screen Mode Items Main Large Sub Middle Small Main Sub VGA (Max.) 1024 1024 1024 1024 1024 1024 x x x x x x 768 768 768 768 768 768 HDMI/YPbPr1/YPbPr2 720p 1080i 480p OK OK OK OK OK OK X OK OK X OK OK OK OK OK OK OK OK

PIP

PBP

Note: - X means out of range (can not show). - When the signal received by the Display exceeds the allowed range, a warning message shall appear on the screen. - You can conrm the input signal format from the on-screen. - VGA 1280 x 1024 Mode dont recommend working in PIP/PBP Screen Mode.

972

Technical

Specifications

PDP4273M

PHYSICAL CHARACTERISTICS 14. Power Cord Length Type 15. Cabinet 15.1 Color : black colour as defined by colour plaque reference number : : 1.8m nominal optional

15.2 Weight(W/Ostand) Net weight 15.3 Dimensions Width Height Depth : : : : 39.2kg (W/O stand&handles) 1039mm 719.9mm 109.5mm

1072

Block Diagram

Product Specification of PDP Module

LVDS Input

Control Signal (Serial Interface) APL Data

Input Interface Controller

Memory Controller

Vs(180V~190V) Va(55V~65V) Vcc(+5V)

Driver Timing Controller

Display data, Driver timing

Color Plasma Display Panel 852 X 480 pixels

Address Driver

Applied Voltage level is specified at the time when Full-White pattern is displayed on the panel.

1172

Common sustain driver

Scan Driver

Block Diagram

MAIN/AUDIO BOARD

CS4344 Audio DAC

1272

Circuit Diagram
Main (Video) board Audio/Tuner board Keypad board Remote control receiver board Remote control board

1372

5 JP902 SPDIFOUT 1 2 L915 C954 3 VIN VCC GND

U902 5V 3 C910 GND INPUT OUTPUT TAB 2 4 C901 1 C911 C904 OVDD3.3V# L900 C916 PLL1.8V C917 C918 C907 OVDD3.3V# L903 AVDD3.3V# TVDD3.3V C924 C925 C956 C909 L914 AVDD3.3V C949 C950 C951 C952

5V

Using digital interface: DVdd (1.8V) (DVdd+CVdd) 130mA 234mW PVd (1.8V) (PVd+ALVdd) 30mA 54mW

R923 SGND AVDD3.3V# 2 4 C902 C913 C905 L901 C919 CVDD1.8V C920 C921 C908 R920 10 90 100 54 33 45 32 48 30 56 59 PLL1.8V HDMI-1.8V 2 4 C903 C915 C906 R905 SCL_H5V SDA_H5V R903 DDC5V R906 C938 82 83 C937 46 R947 GCOAST R908 HD1_R/Pr U905 7 DDC_SCL5 6 DDC_SDA5 5 4 C947 VCLK SCL SDA GND VCC NC1 NC2 NC3 8 1 2 3 HD1_G/Y C929 HD1_B/Pb HD1_G/Y C940 C941 HD1_B/Pb C942 C943 C944 79 74 73 68 61 64 HD2_Cr HD2_Y HD2_Cb GYCbCr_Cb GYCbCr_Cb R909 R910 R941 5V DDC_SCL5 DDC_SDA5 HDMI_5V L913 C930 R915 2 D911 1 3 DDC5V R942 R943 R944 R945 R946 SGND HPD_DET R912 HD1_R/Pr HD1_G/Y HD1_B/Pb GYCbCr_Cr GYCbCr_Y GYCbCr_Cb HDMI_D0HDMI_D0+ HDMI_D1HDMI_D1+ HDMI_D2HDMI_D2+ HDMI_CK+ HDMI_CKRP909 DDC_SCL3 DDC_SDA3 HDCP_SCL HDCP_SDA SDA#SO SCL#SO 34 35 37 38 40 41 43 44 49 50 51 52 TVDD3.3V RX0RX0+ RX1RX1+ RX2RX2+ RXC+ RXCDDC_SCL DDC_SDA MCL MDA ALGND OGND1 OGND2 OGND3 DGND1 CGND1 CGND2 TGND1 TGND2 TGND3 C946 77 71 70 66 60 63 RAIN0 GAIN0 SOG0 BAIN0 VS0 HS0 RAIN1 GAIN1 SOG1 BAIN1 VS1 HS1 HD1_R/Pr C939 62 COAST/EXTCK R907 RTERM G7 G6 G5 G4 G3 G2 G1 G0 SCL SDA L902 DVDD1.8V C922 C923 C935 C936 R904 57 67 72 76 80 L904 OVDD3.3V CVDD1.8V DVDD1.8V PLL1.8V G C926 C927 C928 DDC5V R925 TVDD3.3V R922 Q902 DDC_SDA5 CVDD1 CVDD2 ALVDD OVDD1 OVDD2 OVDD3 TVDD1 TVDD2 PVDD1 PVDD2 DVDD AVDD1 AVDD2 AVDD3 AVDD4 D R924 S DDC_SDA3 DDC_SCL5 D R919 S Q901 DDC_SCL3 R921

Vd (3.3V) (Avdd+TVdd) 80mA 264mW

D

D U903 5V 3 C912 GND INPUT OUTPUT TAB

Vdd (3.3V) (Ovdd) 99mW

10-120mA, 30mA typical

Using analog interface: DVdd PVd Vd 60mA 108mW 20mA 36mW 270mA 891mW

U904 D3V3B 3 C914 GND INPUT OUTPUT TAB

FILT

DDC5V

DDC5V

R7 R6 R5 R4 R3 R2 R1 R0

92 93 94 95 96 97 98 99 2 3 4 5 6 7 8 9 12 13 14 15 16 17 18 19 88 87 86 85 84 89

ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 ADCG7 ADCG6 ADCG5 ADCG4 ADCG3 ADCG2 ADCG1 ADCG0 ADCB7 ADCB6 ADCB5 ADCB4 ADCB3 ADCB2 ADCB1 ADCB0 ADC_DE ADC_HS ADC_SOG ADC_VS ADC_FIELD ADC_DCLK

RP905

RP906

GRE7 GRE6 GRE5 GRE4 GRE3 GRE2 GRE1 GRE0 GGE7 GGE6 GGE5 GGE4 GGE3 GGE2 GGE1 GGE0 GBE7 GBE6 GBE5 GBE4 GBE3 GBE2 GBE1 GBE0 GPEN GFBK GHS GVS FIELD GCLK GSOG I2S_MCLK I2S_MCLK I2S_SCLK I2S_LRCLK I2S_DATA R937 R936 R935

GRE[7..0]

C GGE[7..0]

RP903

D901

D902

RP904

C948 JP901 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

U901

T1 T2 T3 T4

DATA2+ DATA2S DATA2DATA1+ DATA1S DATA1DATA0+ DATA0S DATA0CLK+ CLKS CLKCEC NC SCL SDA CEC/GND +5V HPDET

HDMI_D2+ HDMI_D2HDMI_D1+ HDMI_D1HDMI_D0+ HDMI_D0HDMI_CK+ HDMI_CK-

VGA_VS VGA_HS GYCbCr_Cr GYCbCr_Cr GYCbCr_Y GYCbCr_Y C945

B7 B6 B5 B4 B3 B2 B1 B0 DE HSOUT SOGOUT VSOUT/A0 FIELD DCLK

RP901

GBE[7..0]

RP902

RP907 GPEN GFBK GHS GVS FIELD GCLK GSOG

R918 R917 R916

S/PDIF MCLKIN MCLKOUT SCLK LRCLK I2S0 I2S1 I2S2 I2S3 PWRDN PGND1 PGND2 AGND1 AGND2 AGND3 AGND4

28 20 21 22 23 27 26 25 24

S/PDIF

R929 RP908 I2S_SCLK I2S_LRCLK I2S_DATA 14 OVDD3.3V C955

R938

SCLK R928 R927 R926 DATA/R LRCK/L R933

C2 V2 Y2 DATA/R LRCK/L

20 21 22 23

HPD_DET HDMI_D0+ HDMI_D0HDMI_D1+ HDMI_D1HDMI_D2+ HDMI_D2HDMI_CK+ HDMI_CK-

AVDD3.3V 81 R914 R930 1 R931 7 U907A 2 R932 3 U907B 4 R934 SPDIFOUT C953

D903 D904 D905 A D906 D907 D908 D909 D910

1 11 91

29

31 47

36 39 42

53

VCLK SCL SDA GND

VCC NC1 NC2 NC3

55 58 65 69 75 78

R913

7 6 5 4

8 1 2 3

A JP903 Title

C934 SGND DDC_SCL5 DDC_SDA5 3 2 1

9-HDMI-R
Number 21-Jan-2006 F:\4238\PC_B\4238.DDB Sheet of Drawn By: 6 Revision

U906

Size B Date: File:

1472

D3V3D D U1502
D7_SRAM D7_SRAM D6_SRAM D5_SRAM D4_SRAM D3_SRAM D2_SRAM D1_SRAM D0_SRAM D6_SRAM

D 8

GPIO_P33 GPIO_P32 GPIO_P31 GPIO_P30 TT_SEL R1527 D3V3D

R1514
SDA_S3V

D5_SRAM D4_SRAM

SDA_S3V SCL_S3V

D3_SRAM D2_SRAM D1_SRAM D0_SRAM

RP1501

RP1502 SC1_SW0 SC1_SW1 SC2_SW0 SC2_SW1 C1512

R1515 C1513

SCL_S3V

29 28 27 26 25 23 22 21 R1506 5 30

I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1 /WE /CE1 CE2 /OE

/WR_SRAM

R1513 3450_rest D3V3D D3V3D

6
/RD_SRAM

P2.0 VSSC P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 P1.5

P1.4 SDA

SCL P1.3 P1.2 P1.1 A16_LN P1.0

R1507

32

C1511 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

C
A15_SRAM A14_SRAM /RD_SRAM /WR_SRAM

A7_SRAM SCL_NVRAM SDA_NVRAM

A5 A4 P0.6 P0.7 VSSA CVBS0 CVBS1 A15_BK SYNC_FILTER IREF A13 A12 A3 A2 A1 FRAME VPE /COR P3.4 VDDA B G R A0 RAMBK1

A6_SRAM

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

P2.7 P3.0 A17_LN P3.1 P3.2 P3.3 A15_LN A14 /RD /WR VSSC VSSP P0.5 NC A7 SCL_NVRAM SDA_NVRAM P0.2 NC NC VPE P0.3 A6 P0.4 P3.7

U1501

VDDP NC RESET /RESET XTALOUT XTALIN OSCGND NC A8 A9 A10 A11 VDDC VSSC NC VSSP P3.6 NC NC NC VSYNC P3.5 HSYNC VDS RAMBANK0

X1501
XTALOUT XTALIN

GND

R1505

A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

9 10 7 11 4 12 1 31 2 3 13 14 15 16 17 18 19 20

VCC

A17_SRAM A16_SRAM

RP1503

A15_SRAM A14_SRAM A13_SRAM A12_SRAM

RP1504

A11_SRAM A10_SRAM A9_SRAM A8_SRAM

RP1505

A7_SRAM A6_SRAM A5_SRAM A4_SRAM

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84

83 82

81 80 79 78 77 76

RP1506 R1508 R1509

A3_SRAM A2_SRAM A1_SRAM A0_SRAM

C C1504 C1505 24

A8_SRAM A9_SRAM A10_SRAM A11_SRAM

D3V3D

U1503
SDA_NVRAM SCL_NVRAM

5 6 7

SDA SCL WP VCC

GND NC2 NC1 NC0

4 SC1_SW1 3 2 1 Q1501

R1516

D3V3D SC1_SW0 Q1502 D1501 SC2_SW

R1519

D3V3D

TT_VVVS TT_VVHS TT_FSO R1528 R1529 D3V3D

R1517

R1520

D1502 SC1_SW

B 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 D3V3_TT_A C1510
A13_SRAM A12_SRAM A17_SRAM A5_SRAM A4_SRAM

C1519

C1501

R1501

A3_SRAM

A2_SRAM

A1_SRAM

A0_SRAM

SGND
CVBS0 CVBS1

A16_SRAM

B_OUT

G_OUT

R_OUT

SGND

SC2_SW1 Q1503

R1522

D3V3D SC2_SW0 Q1504 D1503

R1525

D3V3D

SGND

R1523

R1526

D1504

R1510 R1511 TV_CVBS_M# TV_CVBS_S# C1514 C1515 R1521 C1503 C1502 R1502 R1503 C1516 C1517 R1504 C1518 R1512

TT_R TT_G TT_B

D3V3D

SGND

SGND C1506 C1507 C1508 Title Size B Date: File: 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 6

15_TELETEXT_DECODER
Number Revision

1572

5 A5V

U1101 5V 3 GND INPUT OUTPUT TAB 2 4 C1109 C1110 C1111 C1112 C1113 C1114 C1105 1 VV33 R1112

L1112

R1121 TV_CVBS_M# CVBS_O R1114 C1164 Q1101 C1171 R1113 C1163 R1104 R1106 3230_VO 3230_VO D

C1108 D

R1103 MREST R1101 SCL_S3V R1102 C1124 SDA_S3V C1141

5VVV

SGND RP1105 VY7 VY6 VY5 VY4 RP1106 VY3 VY2 VY1 VY0 RP1107 VY7 VY6 VY5 VY4 VY3 VY2 VY1 VY0 VUV7 VUV6 VUV5 VUV4 VUV3 VUV2 VUV1 VUV0 C1139 R1109 R1110 VVCLK VVHS R1123 VVVS VVCLK VVHS TT_VVHS VVVS TT_VVVS Install RP1105~RP1109 if cancel deinterlace IC B VY[7..0] VUV7 VUV6 VUV5 VUV4 RP1108 VUV3 VUV2 VUV1 VUV0 VB3 VB2 VB1 VB0 VB[7..0] RP1109 #VPEN VVVS VVHS VVCLK VUV[7..0] VPEN VVS VHS VCLK VB7 VB6 VB5 VB4 VG3 VG2 VG1 VG0 VG[7..0] C VG7 VG6 VG5 VG4

C1142 C1143

C1146

C1145

C1144

SGND L1107 V_AVCVBS 13 14 15 70 R1115 VV33 C1160 C1159

SGND C1148

5VVV C1147 RP1101 RP1102 RP1103 RP1104

10 29 36 45 52 19 20 21 22 23 69 76 59

C1116 SGND L1108 V_TVCVBS C1150 C1151 R1116 C1117 C1115 C1118 SGND L1102 V_SVideo_C R1117 C1128 C1149 C1120 C1121 SGND B L1111 V_SVideo_Y C1154 C1156 R1118 V_TT_B SGND V_TT_R V_TT_FSO V_TT_G C1166 C1167 C1168 R1127 C1122 C1119

74 73 75 71 72 5 4 6 2 1 3 79 62 63

VIN3 VIN2 VIN4 CIN VIN1 Y2/G2 U2/B2 V2/R2 Y1/G1 U1/B1 V1/R1 FBIN1 VDDCAP

Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 LLC2 LLC HS INTLC AVO HCLP VS VREF VRT

SGND 31 32 33 34 37 38 39 40 41 42 43 44 47 48 49 50 27 28 56 53 54 #VPEN R1107 55 R1105 57 R1108 78 REF_V 66

VOUT

U1102
ADR:0x88
GNDCAP APGND CLK5 FPDAT CLK20 APVDD

GND ASGND ASGND PLGND YGND CGND SPGND AFGND ISGND ISGND ISGND I2CSEL VGAV TEST OE#

XTALI XTALO

VDD PLVDD YVDD CVDD SPVDD FFIE FFWE FFRST FFRE FFOE AFVDD ISVDD VSTBY

SCL SDA RST#

A5V C1137 C1135 C1138 C1136 5V

L1103 5VVV L1101 C1106 C1104 C1107

12

25 60 58 24 26 C1133

R1119 L1104 VYCbCr_Y X1101 L1105 VYCbCr_Cb C1130 A VYCbCr_Cr R1124 C1173 C1125 C1126 C1127 C1172 C1174 R1125 R1126 L1106 C1131

C1132 C1123 C1140 C1134 SGND A Title Size B Date: File: 3 4 5 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 6 SGND C1103 SGND SGND

11 7 64 30 35 46 51 65 68 77 80 67 17 16 18

11-DECODERV
Number Revision

SGND 1 2

SGND

1672

U1401 5V 3 D GND INPUT OUTPUT TAB 2 L1412 4 C1409 C1410 C1411 C1412 C1413 C1414 C1405 1 R1412 GV33

A5V

CVBS_S_O

R1414 C1464 5VVG R1413 Q1401

C1463

SGND R1403 MREST C1424 SGND G_AVCVBS G_AVCVBS L1407 SDA_S3V SCL_S3V 13 14 15 C1460 C L1408 G_TVCVBS C1417 C1450 C1451 R1416 C1415 L1402 G_SVideo_C R1417 C1428 C1449 C1419 C1420 SGND L1411 G_SVideo_Y C1454 B G_TT_G SGND GYCbCr_Y GYCbCr_Y L1404 G_TT_B L1405 G_TT_R G_TT_FSO GYCbCr_Cr GYCbCr_Cr L1406 12 25 60 58 24 26 11 7 64 30 35 46 51 65 68 77 80 67 17 16 18 9 R1419 X1401 C1432 C1423 C1440 C1434 SGND SGND C1430 C1431 SGND A Title Size B Date: File: 1 2 3 4 5 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 6 A SGND R1420 C1433 5VVG SGND SGND C1403 C1406 C1404 C1407 C1467 C1468 R1427 C1466 2 1 3 79 62 63 C1456 R1418 C1421 C1422 4 6 U2/B2 V2/R2 Y1/G1 U1/B1 V1/R1 FBIN1 VDDCAP APGND CLK5 FPDAT CLK20 APVDD XTALI XTALO GNDCAP LLC2 LLC HS INTLC AVO HCLP VS VREF VRT 27 28 56 53 54 55 57 78 66 R1409 R1410 R1408 R1407 R1422 R1405 GHS R1423 REF_G GHS TT-GHS GCLK GHS FIELD GPEN TT-GHS GVS 72 5 VIN1 Y2/G2 SGND C1418 75 71 VIN4 CIN 73 VIN2 SGND C1459 R1415 R1402 C1416 VDD PLVDD YVDD CVDD SPVDD FFIE FFWE FFRST FFRE FFOE AFVDD ISVDD VSTBY VOUT SCL SDA RST# 74 VIN3 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 UV7 UV6 UV5 UV4 UV3 UV2 UV1 UV0 70 10 29 36 45 52 19 20 21 22 23 69 76 59 SGND 31 32 33 34 37 38 39 40 41 42 43 44 47 48 49 50 R1401 GV33 C1448 C1447 SGND RP1401 GGE7 GGE6 GGE5 GGE4 GGE3 GGE2 GGE1 GGE0 GBE7 GBE6 GBE5 GBE4 GBE3 GBE2 GBE1 GBE0 C1439 C GGE[7..0] SGND 5VVG R1406 TV_CVBS_S TV_CVBS_S C1441 C1442 C1443 C1446 C1445 C1444 C1471 R1404 R1421 TV_CVBS_S#

RP1402

RP1403

GBE[7..0]

U1402
ADR:0x8E

RP1404

GYCbCr_Cb

GYCbCr_Cb

GND ASGND ASGND PLGND YGND CGND SPGND AFGND ISGND ISGND ISGND I2CSEL VGAV TEST OE#

C1437 C1435

C1438 C1436 5V 5VVG L1401

R1424 C1473 C1474 C1425 C1426 C1472 C1427

R1425 R1426

14-DECODER_G
Number Revision

1772

C860

C861 U803

TT_VVVS D SDA_S5V SCL_S5V R855 R856

13 14 15 5V_V_CCD 4 6

Vin/INTRO SDA SCK SEN SMS HIN VIDEO CSYNC LPF

R G B

18 2 3 1

R860 R861 R862

V_TT_R V_TT_G V_TT_B

V_TT_R V_TT_G V_TT_B D

I2C/SEL SDO BOX VDD RREF VSS(A)

16 SGND 17 12 10 C862 C863 C864 R864 R865 R866 R867 C865 11 5V A5V L801 R853 R863 5V_V_CCD SCL_S5V V_TT_FSO V_TT_FSO SCL_S5V D R854

R815

TT_VVHS 3230_VO C855 R857

SGND 5 7 8 9 R858

S Q801

SCL_S3V V33SW

G G

R852

SGND C C856 C857 C858 C859 R859 C804 C807 C803

Q802 C C806 SDA_S5V SDA_S5V D S SDA_S3V

R814 SGND C814 C815 U802 GVS SDA_S5V SCL_S5V R801 R802 5V_G_CCD B TT-GHS TV_CVBS_S C809 R803 13 14 15 4 6 SGND 5 7 8 9 R804 SGND 5V_G_CCD C810 C811 C812 C813 R805 C802 C808 C801 C805 L802 A5V Vin/INTRO SDA SCK SEN SMS HIN VIDEO CSYNC LPF R G B I2C/SEL SDO BOX VDD RREF VSS(A) 18 2 3 1 16 17 12 10 C817 C818 C819 R810 R811 R812 11 R813 C820 R809 G_TT_FSO G_TT_FSO B R806 R807 R808 G_TT_R G_TT_G G_TT_B G_TT_R G_TT_G G_TT_B SGND

SGND

SGND

Title Size A4 Date: File:

8-CCD_DECODER
Number 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 4 Revision

1872

3 D3V3B

4 D3V3B

6 U1301C RESET

7 C1354 DCLK DVS DHS DEN J17 C20 D18 N19 Y20 W20 V20 V19 U20 U19 R16 R18 T20 T19 R20 R19 P20 P19 P18 M18 M17 L17 N20 M20 M19 L20 L19 K17 R1317 R1318 R1319 R1320 DR1 RP1302 DR5 DR6 DR0 DR7 RP1303 DR3 DR2 DR4 DG1 RP1304 DG0 DG3 DG2 DG7 RP1305 DG6 DG5 DG4 DB0 RP1306 DB3 DB1 DB2 DB4 RP1307 DB7 DB6 DB5

R1305 R1306

R1329 R1321 R1322 R1323 Y11 E5 D6 A3 C5 Y12 V12 V11 W11 U1301D U4 T4 V3 U3 Y1 W2 T3 V2 U2 W1 R4 V1 P4 R3 T2 U1 T1 R2 R1 P3 V10 Y10 Y9 W9 V9 Y8 W8 V8 W7 U8 V7 W6 Y6 V6 U7 U6 W3 Y3 W12 V5 W4 W5 Y5 Y4 V4 U10 W10 B20 C19 V14

GCOAST GBLKSPL GFBK U1301A D GCLK GPEN GVS GHS GSOG GRE[7..0] A10 B9 A9 C10 B10 GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7 GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 GRO0 GRO1 GRO2 GRO3 GRO4 GRO5 GRO6 GRO7 GGO0 GGO1 GGO2 GGO3 GGO4 GGO5 GGO6 GGO7 GBO0 GBO1 GBO2 GBO3 GBO4 GBO5 GBO6 GBO7 E4 C3 B1 F4 C2 C1 D3 D2 C11 B12 B11 A8 B8 C8 A7 B7 B18 A20 B17 A19 B16 A17 A16 A15 A6 C7 B6 A5 D7 B5 C6 A4 C13 B15 A14 B14 A13 C12 B13 A12 C18 E17 C17 B19 E16 C16 C15 D14 GCLK GPEN GVS GHS GSOG GRE0 GRE1 GRE2 GRE3 GRE4 GRE5 GRE6 GRE7 GGE0 GGE1 GGE2 GGE3 GGE4 GGE5 GGE6 GGE7 GBE0 GBE1 GBE2 GBE3 GBE4 GBE5 GBE6 GBE7 GRO0 GRO1 GRO2 GRO3 GRO4 GRO5 GRO6 GRO7 GGO0 GGO1 GGO2 GGO3 GGO4 GGO5 GGO6 GGO7 GBO0 GBO1 GBO2 GBO3 GBO4 GBO5 GBO6 GBO7 GFBK GREF GBLKSPL GCOAST GHSFOUT A11 D10 C14 A18 C9 X1301 C1301 C1302

R1307 R1308

DCLK DVS DHS DEN DRE[7..0] DRE1 DRE5 DRE6 DRE0 DRE7 DRE3 DRE2 DRE4 DGE1 DGE0 DGE3 DGE2 DGE7 DGE6 DGE5 DGE4 DBE[7..0] DBE0 DBE3 DBE1 DBE2 DBE4 DBE7 DBE6 DBE5 DRE[7..0] DRE3 DRE7 DRE0 DRE2 DRE1 DRE5 DRE4 DRE6 DGE3 DGE2 DGE5 DGE4 DGE1 DGE0 DGE7 DGE6 DBE[7..0] DBE2 DBE5 DBE3 DBE4 DBE6 DBE1 DBE0 DBE7 181 LVDS R0 R6 R1 R7 R2 R0 R3 R1 R4 R2 R5 R3 R6 R4 R7 R5 B DGE[7..0] C DGE[7..0]

VGASEL

RESET MCKEXT DCKEXT XI XO RXD TXD IRRCVR0 IRRCVR1 PORTA0 PORTA1 PORTA2 PORTA3 PORTA4 PORTA5 PORTA6 PORTA7 PORTB0 PORTB1 PORTB2 PORTB3 PORTB4 PORTB5 PORTB6 PORTB7 PORTC0 PORTC1 PORTC2 PORTC3 PORTC4 PORTC5 PORTC6 PORTC7 CPUTMS CPUTCK CPUDI CPUDO MODE0 MODE1 MODE2 MODE3 ADR24B

R1301 RXD TXD IR_181 NMI R1303 SDA_H3V SCL_H3V SDA_S3V SCL_S3V SDA_H3V SCL_H3V

GGE[7..0]

U1301B E1 E3 F3 D1 N2 VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 VG0 VG1 VG2 VG3 VG4 VG5 VG6 VG7 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 R1334 E2 F1 F2 G3 G2 H3 H2 G1 J4 H1 J3 J2 J1 K3 K2 K1 L2 L1 L3 L4 M3 M1 N1 M2

R1304

VCLK VVS VHS FIELD VPEN VR[7..0]

VCLK VVS VHS FIELD VPEN VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7

REMARK: HARDWARE I2C: SDA1 SCL1 SOFTWARE I2C: VSDA VSCL

GAFEOE MUTE SEL1 SEL0 KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KEY6 SP_RELAY D3V3B COMMUNIC P_SCLK P_SDATA P_SLE DTXON HPD_DET 3450_rest R1325 R1332 R1331 R1326 R1324 R1333

D1302

V13 W13 Y13 Y14 W14 Y15 W15 V15 R17 W18 V18 Y18 U18 Y19 W19 T18 T17 V16 W16 Y16 V17 U17 W17 Y17 P1 Y2 M4 N3 U16 N4 T5 P2 U15

A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 PW181 MISC D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 RD WR BHEN ROMOE ROMWE RAMOE RAMWE CS1 CS0 EXTINT NMI DNC1 DNC2 DNC3

A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

A[19..1]

DRE1 DRE5 DRE6 DRE0 DRE7 DRE3 DRE2 DRE4 DGE1 DGE0 DGE3 DGE2 DGE7 DGE6 DGE5 DGE4

D[15..0]

DBE0 DBE3 DBE1 DBE2 DBE4 DBE7 DBE6 DBE5

GBE[7..0]

D3V3B

R1309

VG[7..0]

MREST VG0 VG1 VG2 VG3 PW181 Video Port VG4 VG5 VG6 VG7 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 Q1303

GRO[7..0]

R1310

K19 DRO0 K20 DRO1 K18 DRO2 J20 PW181 Display Port DRO3 J18 DRO4 J19 DRO5 H20 DRO6 H19 DRO7 DGO0 DGO1 DGO2 DGO3 DGO4 DGO5 DGO6 DGO7 DBO0 DBO1 DBO2 DBO3 DBO4 DBO5 DBO6 DBO7 H18 H17 G20 G19 G18 F20 F19 F18 E20 E19 E18 F17 D20 D19 D16 D17

DR1 DR5 DR6 DR0 DR7 DR3 DR2 DR4 DG1 DG0 DG3 DG2 DG7 DG6 DG5 DG4 DB0 DB3 DB1 DB2 DB4 DB7 DB6 DB5

RP1308

RP1309

PW181 Graphics Port

VB[7..0]

GGO[7..0]

ROMOEn ROMWEn

RP1310

D3V3B R1311 R1312 R1313

D3V3B

RP1311

GBO[7..0]

RP1312

SCL_H5V

SCL_H5V

D R1314 G

S Q1301

SCL_H3V RNMI2 D3V3C R1316 5V 3 C1303 C1324 1 SDA_H3V GND INPUT OUTPUT TAB 2 4 C1355 C1326 D3V3B U1303 D3V3B 3 GND INPUT OUTPUT TAB 2 4 C1357 C1312 1 C1344 L1304 V15 C1313 C1331 C1330 C1329 C1328 C1325 U1302 L1302 C1304 V25 C1305 C1306 C1307 C1308 C1309

RP1313

5Vstby R1315

G Q1302 S

SDA_H5V

SDA_H5V

D R1335

For Samsung/Formosa panel 2005.05.22

D3V3B

V25

V15p

V15

C1314 C1315

C1322 C1321 C1320 C1319 C1318 C1317 C1316

T8 R8 R7 R6 M16 M5 L16 J16 G16 G15 G6 G5 F15 F14 F7 F6 F5 E8 E6

U13 U11 U9 U5 T16 A2

T15 T14 T13 T12 T11 T10 T9 T7 T6 R15 R14 R13 P16 P15 P6 P5 N16 N15 N6 N5 L5 K16 K5 J5 H16 H5 F16 E15 E14 E13 E12 E11 E10 E9 E7 U1301E

C4 B4

VIO19 VIO18 VIO17 VIO16 VIO15 VIO14 VIO13 VIO12 VIO11 VIO10 VIO9 VIO8 VIO7 VIO6 VIO5 VIO4 VIO3 VIO2 VIO1

VCC6 VCC5 VCC4 VCC3 VCC2 VCC1

VPP2 VPP1

VDD35 VDD34 VDD33 VDD32 VDD31 VDD30 VDD29 VDD28 VDD27 VDD26 VDD25 VDD24 VDD23 VDD22 VDD21 VDD20 VDD19 VDD18 VDD17 VDD16 VDD15 VDD14 VDD13 VDD12 VDD11 VDD10 VDD9 VDD8 VDD7 VDD6 VDD5 VDD4 VDD3 VDD2 VDD1

V15 C1333 C1334 C1335 C1336 C1337 C1338 C1339 C1340 C1341 C1342 C1343

PW818 POWER AND GROUND GND59 GND58 GND57 GND56 GND55 GND54 GND53 GND52 GND51 GND50 GND49 GND48 GND47 GND46 GND45 GND44 GND43 GND42 GND41 GND40 GND39 GND38 GND37 GND36 GND35 GND34 GND33 GND32 GND31 GND30 GND29 GND28 GND27 GND26 GND25 GND24 GND23 GND22 GND21 GND20 GND19 GND18 GND17 GND16 GND15 GND14 GND13 GND12 GND11 GND10 GND9 GND8 GND7 GND6 GND5 GND4 GND3 GND2 GND1 A A V15 1 C1346 Y7 U14 U12 R5 P17 N18 N17 N13 N12 N11 N10 N9 N8 M13 M12 M11 M10 M9 M8 L18 L13 L12 L11 L10 L9 L8 K13 K12 K11 K10 K9 K8 K4 J13 J12 J11 J10 J9 J8 H13 H12 H11 H10 H9 H8 H4 G17 G4 D15 D13 D12 D11 D9 D8 D5 D4 B3 B2 A1 C1349 C1350 L1301 C1332 V15p C1351 C1352 C1353 Title Size 2 A3 Date: File: 1 2 3 4 5 6 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 7 8

13-SCALER
Number Revision

1972

U1201A 82 83 84 85 86 87 88 89 92 93 94 VY[7..0] VY0 VY1 VY2 VY3 VY4 VY5 VY6 VY7 VUV0 VUV1 VUV2 VUV3 VUV4 VUV5 VUV6 VUV7 95 96 97 98 99 100 101 102 109 110 111 112 113 114 115 116 105 106 107 108 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 SVHS SVVS SVCLK VG0 VG1 VG2 VG3 VG4 VG5 VG6 VG7 VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 PVCLK CREF PVVS PVHS DR0 DR1 DR2 DR3 DR4 DR5 DR6 DR7 DG0 DG1 DG2 DG3 DG4 DG5 DG6 DG7 DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 157 158 159 2 3 4 5 6 149 150 151 152 153 154 155 156 139 140 141 142 143 144 145 148 RP1201 VR0 VR1 VR2 VR3 VR4 VR5 VR6 VR7 VG0 VG1 VG2 VG3 VG4 VG5 VG6 VG7 VB0 VB1 VB2 VB3 VB4 VB5 VB6 VB7 VR[7..0] SCL_S3V SDA_S3V V33SW R1201 R1202 R1204 R1205 R1206 R1207 R1208 V33SW U1201B 127 128 129 130 131 119 120 125 126 117 118 R1203 MREST C1244 R1215 132 73 72 135 X1201 74 VCLK VVS VHS C1251 U1202 5V GND 26 27 24 25 AV331 C1211 U1204 5V 3 C1243 GND INPUT OUTPUT TAB 2 4 C1245 C1222 V33SW C1203 R1214 3 INPUT OUTPUT TAB 2 4 C1242 C1205 C1206 C1207 C1208 C1209 V25SW C1241 C1218 81 TDO TCK TDI TMS TRST I2CA1 I2CA2 SCL SDA PW1231 HOST IF BLOCK XTALI XTALO RESET DEN TESTCLK TEST CGMS

RP1202

RP1203

VG[7..0]

C1201 C1202

31RAMA0 40 31RAMA1 38 31RAMA2 36 31RAMA3 34 31RAMA4 33 31RAMA5 35 31RAMA6 37 31RAMA7 39 31RAMA8 41 31RAMA9 43 31RAMA10 42 31RAMA11 45 31RAMA12 46 31RAMA13 44 V33SW 47 51 R1209 R1210

RP1204

68 MD15 66 MD14 64 MD13 62 MD12 60 MD11 58 MD10 56 MD9 54 MD8 55 MD7 57 MD6 59 MD5 61 MD4 63 MD3 PW1231 MEMORY 65 BLOCK MD2 67 MD1 69 MCLKFB MD0 MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MCLK MRAS MCAS MWE 48 49 50 R1216 R1217 R1218

31RAMD15 31RAMD14 31RAMD13 31RAMD12 31RAMD11 31RAMD10 31RAMD9 31RAMD8 31RAMD7 31RAMD6 31RAMD5 31RAMD4 31RAMD3 31RAMD2 31RAMD1 31RAMD0

RP1205

VB[7..0]

U1201C V33SW C1204 1 3 9 14 27 43 49 Vdd VddQ VddQ Vdd Vdd VddQ VddQ

VUV[7..0]

RP1206

C VVCLK VVVS VVHS

136 R1212 PW1231 VIDEO BLOCK DCLK 137 R1211 DVS 138 R1213 DHS ADSVM ADR ADG ADB VREFIN VREFOUT RSET COMP 12 21 18 15

MACRO

WE CAS RAS DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 CKE

16 31WEn 17 31CASn 18 31RASn 2 4 5 7 8 10 11 13 42 44 45 47 48 50 51 53 V33SW 37 31RAMD0 31RAMD1 31RAMD2 31RAMD3 31RAMD4 31RAMD5 31RAMD6 31RAMD7 31RAMD8 31RAMD9 31RAMD10 31RAMD11 31RAMD12 31RAMD13 31RAMD14 31RAMD15

38 31RAMA0 23 31RAMA1 24 31RAMA2 25 31RAMA3 26 31RAMA4 29 31RAMA5 30 31RAMA6 31 31RAMA7 32 31RAMA8 33 31RAMA9 34 31RAMA10 22 31RAMA11 35 31RAMA12 20 31RAMA13 21

CLK A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 BA0 BA1 U1203

ADR:0x64
B 8 71 104 134 1 9 53 79 91 122 147 78 76 123 11 29 32 17 20 23 14 VSS0 VSS1 VSS2 VSS3 PVSS0 PVSS1 PVSS2 PVSS3 PVSS4 PVSS5 PVSS6 DPAVSS DPDVSS MPAVSS ADDVSS ADAVSS ADGVSS AVS33B AVS33G AVS33R U1201D VDD0 VDD1 VDD2 VDD3 PVDD0 PVDD1 PVDD2 PVDD3 PVDD4 PVDD5 PVDD6 DPAVDD DPDVDD MPAVDD 7 70 103 133 30 52 80 90 121 146 160 77 75 AV25p2 124 V25SW

VssQ VssQ Vss Vss VssQ VssQ Vss /CS DQML DQMH NC NC

B C1226

V33SW1 V33SW C1210 C1212 C1213 C1214 C1215 C1216 C1217 AV25p1 C1249 V25SW L1201 AV25A V33SW C1219 C1220 C1221 C1223 C1250 L1205 AV331 C1237 C1238 C1239 C1240

PW1231 POWER AND 10 GROUND ADDVDD AV25a 28 ADAVDD 31 ADGVDD AVD33B AVD33G AVD33R 16 19 22 AV331 13

V33SW

L1203

V33SW1 C1227 C1228 C1229 C1230 C1231 C1232 C1233

V25SW

L1204

AV25P1 C1234 C1235 C1236 C1248

V25SW

L1202

AV25P2 C1224 C1225 C1246 Title Size B Date: File: 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 6

6 12 28 41 46 52 54 19 15 39 36 40

C1247

AVS33SVM AVD33SVM

12-DEINTERLACE
Number Revision

2072

A5V L1004 D YPbPr_Pr YPbPr_Y YPbPr_Pb YPbPr_Pr VGA R YPbPr_Y VGA G YPbPr_Pb VGA B SGND VCC 2 3 5 6 11 10 14 13 VGASEL VGASEL 1 15 S1A S2A S1B S2B S1C S2C S1D S2D GND IN EN DA U1004 DB DC DD 4 7 9 12 HD1_R/Pr HD1_G/Y HD1_B/Pb HD1_R/Pr C1026 16

5V L101 3 C101 U101

R104

Audio DAC

GND

INPUT OUTPUT TAB

2 4 C102 C103 D

U102 C110 1 2 3 DATA SCLK LRCK MCLK VQ AOUTR VA GND AQUTL FILT+ C107 10 9 8 C109 7 6 C108 C Suit for AD9880+MSP3420 2005.09.20 L R103 DATA/R C112 R R102 LRCK/L C111

HD1_G/Y HD1_B/Pb

I2S_DATA I2S_SCLK I2S_LRCLK R101 I2S_MCLK C105

4 5 C106

C104 TVDD3.3V 14

C R1005 VGAHS R1015

SGND 1 C1041

R1007 2 U1007A 7 3 4 U1007B

R1009 VGA_HS VGA_HS

R1006 VGAVS R1016 5V B D1001 D1002 5V 11 C1042 10 U1007C

R1008 13 12 U1007D

R1010 VGA_VS VGA_VS D1006 R1019 D1007 R1020 R1021 5V 1 D1015 B D1005 U1008 DDCC DDCD L1001 L1002 VGA B R1022 VGA G 7 6 5 4 VCLK SCL SDA GND VCC NC1 NC2 NC3 8 1 2 3 3 5V D1004 L1003 VGA R R1011 R1012 R1013 Title Size SGND A4 Date: File: 2 3 21-Jan-2006 F:\4238\PC_B\4238.DDB Sheet of Drawn By: 4 Number SC104 VGA5V 2

5V D1003

5V

JP1001
15 VGAVS VGAHS DDCC DDCD 11 SC102 A 17 16 14 13 12 5 10 4 9 3 8 2 7 1 6

VGA5V

C1003

SC101

SC103

10-PROGRESSIVE_ADC
Revision

SGND

AGND 1

2172

A[19..1] D ROMOEn ROMWEn RESETn D3V3B R401 R402 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 C 25 24 23 22 21 20 19 18 8 7 6 5 4 3 2 1 48 17 16 26 28 11 12 14 47

U401 CE OE WE RESET NC BYTE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 FLASH_8M NC Vdd DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 A19 NC RY/BY Vss Vss 13 D3V3B 37 29 31 33 35 38 40 42 44 30 32 34 36 39 41 43 45 9 10 15 46 27 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 C401

ADR:0xA0/MEMORY ADR:0xD0/COMPANION

C418 C419 SW402 D3V3B 1 2 R404 NMI R405 C406 5Vstby 5V C402 L405 C SDA_H5V SCL_H5V R407 L404 R408 5 6 7 8

U402
SDA SCL WP VCC GND NC2 NC1 NC0 4 3 2 1

5V JP401 R409 1 3 2 4 D3V3B R410

L401

5V# C417

16 U404 VCC

C420

1 C409 3 4 D3V3B JP402 A2 A4 A6 A9 A11 A12 A14 A17 A19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 A1 A3 A5 A7 A8 A10 A13 A15 A16 A18 R411 R412 R413 TXD TXD R417 11 10 RXD RXD R418 C416 R416 12 9 C415 D3V3B C410 5

C1+ C1C2+

C411 V+ 2

VC2T1_IN T2_IN R1_OUT GND R2_OUT T1_OUT T2_OUT R1_IN R2_IN

C412 1 6 2 7 3 8 4 9 5

11 JP403 232_OUT 232_IN C413 C414 10

14 7 13 8

L403

L402

D15 D14 D5 D4 D3 D2 D9 D8

D7 D6 D13 D12 D11 D10 SW401 D1 D0 1 2 RSTINn TLCCT C408 C407 7 2 3 1 R414 U403 SENCE Vdd RESin RESET CT RESET CONTROL GND 8 6 5 4

15

D3V3B TXD RXD C405 R415 SDA#SO SCL#SO RESET RESETn R406 SDA#SO SCL#SO R419 R420 R421 R422 RESET

JP404 5V 4 3 2 1

D[15..0] A A

Title Size A3 Date: File: 1 2 3 4 5 6

4-FLASH
Number 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 7 8 Revision

2272

1 For sumsung panel standard LVDS jack 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 LVD33 L501 C520 C522

4 Formosa panel CPUGO RELAY_ON# P_SDATA P_SDATA D

R512 LVD_PLL33 JP501 C524 TX0L502 C521 C523 TX0+ LVD_VCC TX1C525 TX1+ TX25 7 9 6 8 10 12 14 16 18 20 For LG panel standard LVDS jack 1 2 3 4 5 6 7 TX28 TX2+ 9 CK10 CK+ 11 TX312 TX3+ 13 14 15 16 17 18 19 20 21 22 23 24 25 26 p_dispen# 27 p_sdata# 28 p_sclk# 29 p_sle# 30 31 TX0TX0+ TX1TX1+ NC SGND Title 5 13 21 29 53 Size A4 Date: File: P_SDATA# P_SCLK# P_SLE# P_DISPEN# PDWN C526 L503 IRQ C529 L506 P_SLE R511 SDA_S3V 1 3 2 4 R510 SCL_S3V PDPGO C528 R503 R504 L504 C527 R513 L505

TX0TX0+ D TX1TX1+ TX2TX2+ CKCK+ TX3TX3+

CPUGO

Formosa panel PDPGO VS_ON# P_SCLK P_SCLK

TX2+ 11 CKC501 C502 R501 RS TX3+ 19 R502 21 22 13

P_SLE

CK+ 15 TX3- 17

P_DISPEN

P_DISPEN C

1 9 26 For LG panel TxCLK_IN TxIN0 TxIN1 TxIN2 TxIN3 TxIN4 TxIN6 TxIN27 TxIN5 TxIN7 TxIN8 TxIN9 TxIN12 TxIN13 TxIN14 TxIN10 TxIN11 TxIN15 TxIN18 TxIN19 TxIN20 TxIN21 TxIN22 TxIN16 TxIN17 TxIN24 TxIN25 TxIN26 TxIN23 DRE2 DRE3 DRE4 DRE5 DRE6 DRE7 DRE0 DRE1 DGE2 DGE3 DGE4 DGE5 DGE6 DGE7 DGE0 DGE1 DBE2 DBE3 DBE4 DBE5 DBE6 DBE7 DBE0 DBE1 51 52 54 55 56 3 50 2 4 6 7 11 12 14 8 10 15 19 20 22 23 24 16 18 27 28 30 25 VCC VCC VCC 31

NC

SGND

LVDS_VCC PLL_VCC

44 34

For sumsung panel DRE0 DRE1 DRE2 DRE3 DRE4 DRE5 DRE6 DRE7 DGE0 DGE1 DGE2 DGE3 DGE4 DGE5 DGE6 DGE7 DBE0 DBE1 DBE2 DBE3 DBE4 DBE5 DBE6 DBE7 DCLK DRE[7..0] DCLK

TxOUT0TxOUT0+ TxOUT1TxOUT1+ TxOUT2TxOUT2+ TxOUT3TxOUT3+ TxCLKOUTTxCLKOUT+

GND

48 47 46 45 42 41 38 37 40 39

TX0TX0+ TX1TX1+ TX2TX2+ TX3TX3+ CKCK+

U502 5V 3 INPUT OUTPUT TAB 2 4 C507 C506 1 B LVD33

C510

C505

DGE[7..0]

U501

PWR_DWN R_FB

32 DTXON 17 LVD33

/ DS90C385AMTD PLL_GND PLL_GND LVDS_GND LVDS_GND LVDS_GND 35 33 R508 49 43 36 DTXON R509

DBE[7..0] DHS DVS DEN DHS DVS DEN

GND GND GND GND GND

5-LVDS&TMDS
Number 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 4 Revision 00 ANDY

2372

1 D3V3B L606 D3V3#

2 U604 5V 2 4 GND OUTPUT INPUT TAB 3 5VSC 2 4 1 U603

3 R630 D6V D605 D3V3# GND OUTPUT INPUT TAB 3 RELAY_ON# 5Vstby#

4 JP608 1 2 3 4 5 6 7 8 9

C623

C614

C622 C621

C613

L602 5V 5VSC L608 C626 C618 C625 C617 R628 JP607 1 2 3 4 5 6 7 8 9 10 11 VS_ON# RELAY_ON# D

C601 D3V3C C624 For SDI V3 HD Panel 2005.06.14 D3V3D L628 5V_mcu L607 1 D

C603

L601

5Vstby

L605

RELAY_ON L623 VS_ON 5VDetect L624 L625 C649 C650

RELAY_ON# 5Vstby# VS_ON# C648

C631

C630

R629 C651 C654 C655 C612 C602

D3V3_TT_A L629 R635

D610

R639

R640

R641

R642

R643

C643

C642

5Vstby Q603 C644 LED_R C

C VS_ON SB_5VCN 5VDetect

SGND 1 2 3

U602 PA3 PA2 PA1 PA0 PB2 PB1/_BZ PB0/BZ VSS PA4 PA5 PA6 PA7 OSCO OSCI VDD /RES 18 17 16 15 14 13 12 11 10 RST IR_mcu mut# key_stby SDA# SCL# OSCO OSCI 5V_mcu 5VDetect P_ON/SLEEP P_DISPEN COMMUNIC R616 C608 VS_ON 1 2 3 4 5 6 7 8 9 PA3 PA2 PA1 PA0 PB2

U601 PA4 PA5 PA6 PA7 OSCO OSCI VDD /RES 18 17 16 SDA# 15 SCL# 14 13 12 OSCO OSCI 5V_mcu PB0/BZ VSS mut#

D601

MUTE R627 key_stby Q605 Q606 5Vstby 5Vstby IR_mcu IR_181 R625 Q607 C611 R620 5Vstby R624 L620 L621 L622 5V

R617 C628 R618 C629

SDA_H5V SCL_H5V

D3V3B

LED_G IR_5V

P_ON/SLEEP 4 P_DISPEN 5

R619

R621

R622 R623

R632 R631 C640 C632 R633 C641

P_DISPEN COMMUNIC

COMMUNIC 6 7 8 B IR_mcu 9

PB1/_BZ

X601 R626 C610

11 RST 10 C609

D3V3B

From pannel B JP604 A

PC0/_INT PC1/TMR

PC0/_INT PC1/TMR

D3V3B R608 R611 R612 R613 R614

D3V3B R601

5Vstby R605 KEY0 KEY1 KEY2 KEY3 KEY4 KEY5 KEY6

D602 D603 D604

P_ON/SLEEP

R602

Q601

R606

RELAY_ON

L611 L612 L613 L614 L615 L616 L617 C633 C634 C635 C636 C637 C638 C639

STANDBY P+ PVV+ MENU INPUT

13 12 11 10 9 8 7 6 5 4 3 2 1

R615

R609

R607 A

R603 Q602 R604 Title Size B Date: File:

R610

To Key Board

6-POWER MANAGE
Number 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 6 Revision

2472

1 5V_E R748

2 5V_E R761

3 5V_E R765

R705 Cb Q733 D C760 R749 GYCbCr_Cb C759 C763 R763 Cr Q734 GYCbCr_Cr C762 C766 R767 Y TV_M Q735 GYCbCr_Y C765 A5V L748 2 3 4 SGND JP701 2 Pr_in 1 Cr_in 4 Pb_in 3 Cb_in 6 HD_Y_in 5 YUV_Y_in R742 7 8 9 R736 SGND L750 C Cb_in C740 R750 Cb_in# 5V D701 R723 R725 GYCbCr_Cr TT_R SC1_R TT_G SC1_G TT_B SC1_B TT_FSO SC1_BOX TT_SEL 2 3 5 6 11 10 14 13 1 15 SGND 5V_E SGND 16 SGND AGND R790 R706 C706 Cutoff frequency : 6.4MHz R720 C753 R722 R741 SGND Cb C736 Q701 VYCbCr_Cb C737 A5V L749 3 4 R730 GYCbCr_Cb TV_S C705 1 2 U703 VIN ENABLE RFC VCC GSEL VF VOUT GND 8 7 6 5 R707 C707 SGND L738 C711 R719 R721 SGND C701 1 U702 VIN ENABLE RFC VCC GSEL VF VOUT GND 8 7 6 5 R702 C703

V_TVCVBS

V_TVCVBS G_SVideo_Y G_SVideo_C G_SVideo_Y G_SVideo_C G_AVCVBS SCL_S5V SC2_SW GPIO_P31 GPIO_P30 GPIO_P32 GPIO_P33 SC2_BOX SC2_R SC2_G SC2_B SC1_SW SC1_BOX SC1_R SC1_G SC1_B

R735 R745 R734 R744 R733 R743

V_SVideo_Y V_SVideo_C D V_AVCVBS

R703 C704 R704 G_AVCVBS SCL_S5V SC2_SW GPIO_P31 GPIO_P30 GPIO_P32 GPIO_P33 G_TT_FSO G_TT_R G_TT_G G_TT_B SC1_SW

A5V

5V_E

R787

R701 C702 Cutoff requency : 6.4MHz

C710

SGND

R710

G_TVCVBS

G_TVCVBS

R768 R769 R770 R771

R708 C708 SDA_S5V 3450_rest MUTE SP_RELAY 3230_VO V_AVCVBS V_SVideo_C V_SVideo_Y

A5V

R709

L739 C709

A5V

49 47 45 43 41 39 37 35 33 31 29 27 SDA_S5V 25 3450_rest 23 21 MUTE SP_RELAY 19 3230_VO 17 15 TV_M TV_S 13 V_AVCVBS11 V_SVideo_C 9 V_SVideo_Y 7 AV_LOUT 5 AV_ROUT 3 1 +8V JP703

50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2

A5V

V2 C2 Y2 C2 V2 Y2

VCC

TT_R Cr_in L751 SGND Cr_in# 5V D702 C742 R751 R737 R724 C754 R726 C738 Cr Q702 VYCbCr_Cr C739 P15V330 Truth Table IN EN ON Switch 0 0 S1A S1B S1C S1D 1 0 S2A S2B S2C S2D x 1 Disabled TT_B TT_FSO TT_SEL R731 TT_G

S1A S2A S1B S2B S1C S2C S1D S2D

DA U704 DB DC DD GND

SGND 4 V_TT_R 7 9 V_TT_G V_TT_B

V_TT_R V_TT_G V_TT_B V_TT_FSO DVI_L_IN# DVI_R_IN# R776 R780

AGND SGND

DVI_L_IN 3 DVI_R_IN 2 JP705

12 V_TT_FSO

R711

C732

R712

YUV_Y_in

L752

SGND YUV_Y_in# 5V R752 D703 R727

SGND

5V_E

IN EN

GYCbCr_Y SGND A5V R794 R732 C751 Y Q703 VYCbCr_Y C752 R788 SGND SGND SGND R_O R756 R757 AGND DVI_R_IN# C722 C723 C724 C726 C719 C720 C721 8 7 C725 AGND AV_R1 AV_R2 AV_R3 AV_R4 AV_L1 AV_L2 AV_L3 AV_L4 C789 C790 C787 AV_R1 AV_R2 AV_R3 16 AGND U701 Y0A Y1A Y2A Y3A Y0B Y1B Y2B Y3B VDD YPbPr_R_IN# 12 14 15 11 1 5 2 4 ZA ZB A1 A0 VSS VEE E 13 R_O C756 3 9 10 6 SEL1 SEL1 C743 R792 Q704 Q705 R793 SEL0 C741 SEL0 AGND L_O C757 AGND AV_ROUT AV_LOUT R740 R739 AV_R4 8V_4052 AV_L1 AV_L2 AV_L3 AV_L4 R72 R73 R74 R75 R76 R715 R716 R717 C734 C730 C735 R718 R77 R78 R79 R71 C780 C781 C731 R70 +8V 8V_4052 L756 8V_4052 YUV_L_IN# YUV_R_IN# YPbPr_L_IN# YPbPr_R_IN# R779 R783 R778 R782 YUV_L_IN 3 YUV_R_IN 1 YPbPr_L_IN 4 YPbPr_R_IN 2 5 SGND AGND JP704 R791 C714 C713 C715 C716 C718 R772 R773 R774 R775 5V SC2_BOX SC2_R SC2_G SC2_B R784 R785 R786 V2 C2 R713 C729 R714 Y2 C733

C744

R729

SGND

C728

AGND JP707 VGA_L4# VGA_R4# R777 R781 VGA_L4 VGA_R4 3 4 2 1 B

Pb_in

L753

SGND YPbPr_Pb 5V R738 R728

C746

R753

D704

C755

Pr_in

L754

SGND YPbPr_Pr 5V

C748

R754

D705 VGA_R4#

L_O

R758 R759

1 6

HD_Y_in

L755

SGND YPbPr_Y

YUV_R_IN# DVI_L_IN# 5V

AGND

C750

R755

D706

VGA_L4# YPbPr_L_IN# YUV_L_IN#

Title Size A3 Date: File:

7-VIDEO&AUDIO IN
Number 14-Oct-2005 Sheet of F:\4228\4228_temp_ddb\4228_Temp.DDB Drawn By: 7 8 Revision

SGND 1 2 3 4 5 6

2572

Audio.Board.BH(M-CH).05.06.14.sch-1 - Tue Aug 16 22:15:14 2005

2672

DUBHE OSD Ver1.1_NAKS.sch-1 - Mon Oct 18 11:47:11 2004

2772

0025.sch-1 - Mon May 16 09:25:50 2005

2872

Basic Operations & Circuit Description MODULE

There are 1 pc. panel and 12 pc.s PCB including 2 pc.s Y/Z Sustainer board, 2 pc.s Y Drive board, 6 pc.s X Extension boards, 1 pc. Control (Signal Input) and 1 pc. Power board in the Module.

SET
There are 6 pc.s PCBs including 1 pc. AUX. PSU Board, 1 pc. Keypad board, 1 pc. Remote Control Receiver board, 1 pc. L/R Speakers and 1 pc. Main (Video) board in the SET.

2972

Main Power Supple

Internal Speaker terminal

Y-Driver Top

Sub Power Supple

Y-Sustainer Z-sustainer

Y-Driver Bottom

EMI Filter & AC Intel

Local Key

Audio

Stand

Main(Video)

33/7 5

3072

PCB function

1. Power: (1). Input voltage: AC 100V~120V, 45Hz~60Hz. Input range: AC 90V(Min)~265V(Max) auto regulation. (2). To provide power for PCBs. 2. Main (Video InterFace) board: To converter TV signals, S signals, AV signals, Y Pb/ Cb Pr/Cr signals, DVI signals and D-SUB signals to digital ones and to transmit to Control board. 3. Control board: Dealing with the digital signal for output to panel. 4. Y-Sustainer / Z-Sustainer board: (1). Receiving the signals from Control and high voltage supply. (2). Output scanning waveform for Module. 5. Y-Drive board: Receive signal from Y sustainer, output horizontal scanning waveform to the panel. 6. X extension board (6pcs): Output addressing signals. 7. Tuner/Audio Board: Process and Amplifying the audio signal to speakers and convert TV RF signal to video/audio signal and send to Main board.

3172

PCB failure analysis

1. CONTROL : 2. MAIN (video) : a. Abnormal noise on screen. b. No picture. a. Lacking color, Bad color scale. b. No voice. c. No picture but with signals output, OSD and back light. d. Abnormal noise on screen. 3. POWER : No picture, no power output. 4. Z - Sustainer : a. No picture. b. Color not enough. c. Flash on screen. 5. Y - Sustainer : Darker picture with signals. 6. X - Extension : Abormal vertical noise on screen. 7. Audio Board or AUX PSU: a. No voice. (Make sure Mute/OFF) . b. Noise.

3272

Basic operation of Plasma Display

1. After turning on power switch, power board sends 5Vst-by Volt to Micro Processor

2. The micro Processor memorize the last state of Power, When the last state of power is on or receive power on signal from local Key or Remote control, Micro Processor will send on control signal to power. Then Power sends (5Vsc, 9Vsc, 24V and RLYON, Vs ON) to PCBs working. This time VIF will send signals to display Image, OSD on the panel and start to search available signal sources. If the audio signals input, them will be amplified by Audio AMP and transmitted to Speakers. 3. If some abnormal signals are detected (for example: over volts, over current, over temperature and under volts), the system will be shut down by Power off.

3372

Main IC Specifications

- PW181 Image Processor, Scaler - PW1231 Digital Video Signal Processor - VPC 323XD Comb-filter Video Processor - Z86229 NTSC Line 21 CCD decorder - MSP34x0G Multistandard Sound Processor -AD9880 Analog/HDMI Dual Display Interface -PI5V330 Wideband/Video Quad 2-Channel MUX/DEMUX -SM5304AV Video Buffer with Built-in Analog LPF -TDA2616 2 X 12 W hi-fi audio power amplifier with mute -SAA5360 Multi page intelligent teletext decoder -AT24C32 Z-Wire Serial EEPROM -HT48R06A-1 8-Bit Cost-Effective I/O Type MCU

3472

PW181
Product Specification
General Description
The PW181 ImageProcessor is a highly integrated system-on-a-chip that interfaces computer graphics and video inputs in virtually any format to a fixed-frequency flat panel display. Computer and video images from NTSC/PAL to WUXGA at virtually any refresh rate can be resized to fit on a fixedfrequency target display device with any resolution up to WUXGA. Video data from 4:3 aspect ratio NTSC or PAL and 16:9 aspect ratio HDTV or SDTV is supported. Multiregion, nonlinear scaling allows these inputs to be resized optimally for the native resolution of the display. Advanced scaling techniques are supported, such as format conversion using multiple programmable regions. Three independent image scalers coupled with frame locking circuitry and dual programmable color lookup tables create sharp images in multiple windows, without user intervention. Embedded SDRAM frame buffers and memory controllers perform frame rate conversion and enhanced video processing completely on-chip. A separate memory is dedicated to storage of on-screen display images and CPU general purpose use. Advanced video processing techniques are supported using the internal frame buffer, including motion adaptive, temporal deinterlacing with film mode detection. When used in combination with the new third-generation scaler, this advanced video processing technology delivers the highest quality video for advanced displays. Both input ports support integrated DVI 1.0 content protection using standard DVI receivers. A new advanced OSD Generator with more colors and larger sizes supports more demanding OSD applications, such as on-screen programming guides. When coupled with the new, faster, integrated microprocessor, this OSD Generator supports advanced OSD animation techniques. Programmable features include the user interface, custom start-up screen, all automatic imaging features, and special screen effects.
TV Signal Video Input
TV Tuner Video Decoder

Crystal

Com puter Com puter TV Signal

TV Tuner

ADC/ TMDS

PW181
ADC/ TMDS

Display

Video Decoder

ROM

Video Input

PW181 System Block Diagram

Features
Third-generation, two-dimensional filtering techniques Third-generation, advanced scaling techniques Second-generation Automatic Image Optimization Frame rate conversion Video processing On-Screen Display (OSD) On-chip microprocessor JTAG debugger and boundary scan Picture-in-picture (PIP) Multi-region, non-linear scaling Hardware 2-wire serial bus support

Applications
Multimedia Displays Plasma Displays Digital Television
Device
PW181-10V PW181-20V

Application
Up to XGA Displays Up to UXGA Displays

Package
352 PBGA

3572

PRELIMINARY / CONFIDENTIAL

a
FEATURES 140 MSPS Maximum Conversion Rate 300 MHz Analog Bandwidth 0.5 V to 1.0 V Analog Input Range 500 ps p-p PLL Clock Jitter at 110 MSPS 3.3 V Power Supply Full Sync Processing Sync Detect for Hot Plugging Midscale Clamping Power-Down Mode Low Power: 500 mW Typical 4:2:2 Output Format Mode APPLICATIONS RGB Graphics Processing LCD Monitors and Projectors Plasma Display Panels Scan Converters Microdisplays Digital TV

110 MSPS/140 MSPS Analog Interface for Flat Panel Displays AD9883A
FUNCTIONAL BLOCK DIAGRAM
RAIN CLAMP A/D 8 ROUTA

GAIN

CLAMP

A/D

GOUTA

BAIN

CLAMP

A/D

BOUTA MIDSCV

HSYNC COAST CLAMP FILT

SYNC PROCESSING AND CLOCK GENERATION

DTACK HSOUT VSOUT SOGOUT REF REF BYPASS

SCL SDA A0

SERIAL REGISTER AND POWER MANAGEMENT

AD9883A

GENERAL DESCRIPTION

The AD9883A is a complete 8-bit, 140 MSPS monolithic analog interface optimized for capturing RGB graphics signals from personal computers and workstations. Its 140 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports resolutions up to SXGA (1280 1024 at 75 Hz). The AD9883A includes a 140 MHz triple ADC with internal 1.25 V reference, a PLL, and programmable gain, offset, and clamp control. The user provides only a 3.3 V power supply, analog input, and Hsync and COAST signals. Three-state CMOS outputs may be powered from 2.5 V to 3.3 V. The AD9883As on-chip PLL generates a pixel clock from the Hsync input. Pixel clock output frequencies range from 12 MHz to

140 MHz. PLL clock jitter is 500 ps p-p typical at 140 MSPS. When the COAST signal is presented, the PLL maintains its output frequency in the absence of Hsync. A sampling phase adjustment is provided. Data, Hsync, and clock output phase relationships are maintained. The AD9883A also offers full sync processing for composite sync and sync-on-green applications. A clamp signal is generated internally or may be provided by the user through the CLAMP input pin. This interface is fully programmable via a 2-wire serial interface. Fabricated in an advanced CMOS process, the AD9883A is provided in a space-saving 80-lead LQFP surface-mount plastic package and is specified over the 0C to 70C temperature range.

REV. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: Fax:

3672

PW1231A
Product Specification
General
The PW1231A is a high-quality, digital video signal processor that incorporates Pixelworks patented deinterlacing, scaling, and video enhancement algorithms. The PW1231A accepts industry-standard video formats and resolutions, and converts the input into many desired output formats.The highly efficient video algorithms result in excellent quality video. The PW1231A combines many functions into a single device, including a memory controller, auto-configuration, and others. This high level of integration enables simple, flexible, cost-effective solutions that require fewer components.
Crystal

Video

Video Decoder

PW1231A PW1231AL

Digital Output

PW1231A System Block Diagram

SDRAM

Features
Built-In Memory Controller Motion-Adaptive Deinterlace Processor Intelligent Edge Deinterlacing Digital Color/Luminance Transient Improvement (DCTI/DLTI) Interlaced Video Input Options, including NTSC and PAL Independent horizontal and vertical scaling Copy Protection Two-Wire Serial Interface

Applications: For use with Digital Displays

Flat-Panel (LCD, DLP) TVs Rear Projection TVs Plasma Displays LCD Multimedia Monitors Multimedia Projectors

Device
PW1231A PW1231AL

Application
Up to XGA

Package
160-pin PQF

NOTE: L denotes lead (Pb) free

8100 SW Nyberg Road Tualatin, OR 97062 USA Telephone: 503.612.6700 FAX: 503.612.6713 www.pixelworks.com

PRELIMINARYCONFIDENTIAL
3772

P/N 001-0097-00 Rev B July 2003

a
Preliminary Datasheet
FEATURES
Analog/HDMI Dual Interface Supports High-Bandwidth Digital Content Protection RGB to YCbCr two-way color conversion Automated clamping level adjustment 1.8/3.3V Power Supply 100-pin LQFP Pb-Free Package RGB and YCbCr Output Formats

Analog/HDMI Dual Display Interface

3/26/2004

AD9880

FUNCTIONAL BLOCK DIAGRAM

Analog Interface R/G/B or YPbPrIN0 R/G/B or YPbPrIN1 HSYNC 0 HSYNC 1 HSYNC 0 HSYNC 1 SOGIN 0 SOGIN 1 COAST CLAMP CKINV CKEXT FILT SCL SDA Serial Register and Power Management 2:1 MUX 2:1 MUX 2:1 MUX 2:1 MUX Clamp A/D R/G/B 8X3 or YCbCr

Analog Interface
8-bit Triple Analog to Digital Converters 150 MSPS Maximum Conversion Rate Macrovision Detection 2:1 Input Mux Full Sync Processing Sync Detect for Hot Plugging Mid-Scale Clamping

2 Sync Processing and Clock Generation

DATACK HSOUT VSOUT SOGOUT RGB YCbCr Matrix

REFOUT REFIN

Ref MUXES

R/G/B 8X3 YCbCr (4:2:2 or 4:4:4)

2

Digital Video Interface

HDMI 1.0, DVI 1.0 150 MHz HDMI Receiver Supports High-Bandwidth Digital Content Protection (HDCP 1.1)

DATACK HSOUT VSOUT /A0 SOGOUT DE

Digital Interface R/G/B 8X3 RX0+ RX0RX1+ RX1RX2+ RX2RXC+ RXCRTERM MCL MDA DDCSCL DDCSDA 2 or YCbCr DATACK DE Hsync HDMI Receiver Vsync SPDIF OUT 8 Channel I2S OUT MCLK LRCLK HDCP

Digital Audio Interface

HDMI 1.0 compatible audio interface S/PDIF (IEC90658 compatible) digital audio output Multi-channel I2S audio output (up to 8 channels) APPLICATIONS Advanced TV HDTV Projectors LCD Monitor GENERAL DESCRIPTION The AD9880 offers designers the flexibility of an analog interface and High-Definition Multimedia Interface (HDMI) receiver integrated on a single chip. Also included is support for High bandwidth Digital Content Protection (HDCP). Analog Interface The AD9880 is a complete 8-bit 150 MSPS monolithic analog interface optimized for capturing Component Video (YPbPr) and RGB graphics signals. Its 150 MSPS encode rate capability and full power analog bandwidth of 300 MHz supports all HDTV formats (up to 1080p) and FPD resolutions up to SXGA (1280 x 1024 at 75 Hz). The analog interface includes a 150 MHz triple ADC with internal 1.25V reference, a Phase Locked Loop (PLL), and programmable gain, offset, and clamp control. The user provides only 1.8V and 3.3V power supply, analog input, and Hsync. Three-state CMOS outputs may be powered from 1.8V to 3.3V. The AD9880s on-chip PLL generates a pixel clock from Hsync. Pixel clock output frequencies range from 12 MHz to 150 MHz.

AD9880

PLL clock jitter is typically less than 500 ps p-p at 150 MHz. The AD9880 also offers full sync processing for composite sync and Sync-on-Green (SOG) applications. Digital Interface The AD9880 contains a HDMI 1.0 compatible receiver and supports all HDTV formats (up to 1080p) and display resolutions up to SXGA (1280 x 1024 at 75 Hz). The receiver features an intra-pair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays may now receive encrypted video content. The AD9880 allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission as specified by the HDCP 1.1 protocol. Fabricated in an advanced CMOS process, the AD9880 is provided in a space-saving 100-lead LQFP surface-mount plastic package and is specified over the 0 C to 70 C temperature range.

AD9880 Preliminary Technical Information

Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Analog Devices, Inc., 2004

One Technology Way, P.O Box 9106, Norwood, MA 020629106, USA Tel: 617/3294700 Fax: 6173268703

3872

PRELIMINARY DATA SHEET

VPC 323xD

Comb Filter Video Processor

1. Introduction The VPC 323xD is a high-quality, single-chip video front-end, which is targeted for 4:3 and 16:9, 50/60-Hz and 100/120 Hz TV sets. It can be combined with other members of the DIGIT3000 IC family (such as DDP 331x) and/or it can be used with 3rd-party products. The main features of the VPC 323xD are high-performance adaptive 4H comb filter Y/C separator with adjustable vertical peaking multi-standard color decoder PAL/NTSC/SECAM including all substandards four CVBS, one S-VHS input, one CVBS output two RGB/YCrCb component inputs, one Fast Blank (FB) input integrated high-quality A/D converters and associated clamp and AGC circuits multi-standard sync processing linear horizontal scaling (0.25 ... 4), as well as non-linear horizontal scaling Panoramavision PAL+ preprocessing line-locked clock, data and sync, or 656-output interface peaking, contrast, brightness, color saturation and tint for RGB/ YCrCb and CVBS/S-VHS high-quality soft mixer controlled by Fast Blank
1 1 -- , --, ----- , or PIP processing for four picture sizes ( 1 4 9 16 1 --of normal size) with 8-bit resolution 36

15 predefined PIP display configurations and expert mode (fully programmable) control interface for external field memory I2C-bus interface one 20.25-MHz crystal, few external components 80-pin PQFP package

1.1. System Architecture Fig.11 shows the block diagram of the video processor

CIN VIN1 VIN2 VIN3 VIN4 VOUT

Analog Front-end

Adaptive Comb Filter NTSC PAL

Color Decoder NTSC PAL SECAM Saturation Tint

Mixer

2D Scaler PIP Panorama Mode Contrast Brightness

Output Formatter ITU-R 656 ITU-R 601 Memory Control

Y OUT CrCb OUT YCOE FIFO CNTL

Cr

Cr

AGC 2 ADC

Cb

Cb

Peaking

RGB/ YCrCb FB RGB/ YCrCb

Processing Y Analog Component U/B Cr Matrix Front-End Contrast V/R Saturation Cb Brightness 4 x ADC FB FB Tint

Y/G

I2C Bus

Clock Gen.

Sync + Clock Generation

LL Clock H Sync V Sync AVO

20.25 MHz I2C Bus

Fig. 11: Block diagram of the VPC 323xD

Micronas

3972

"

"

"%$ #   $ 

$#
$%"#




  

"

/: -/7 

#4//.


2 3928 +- +1/ $ 4/7 2  # 

#8+2.+6. $/ 4
"+21/   83  

2 #-6//2  74 +  37/. +48 32 21 /7

983 +8 - +8+  86+-8 32 6316+ "+8 21 $ / 30 + /7 /7

Complete Stand-Alone Line 21 Decoder for ClosedCaptioned and Extended Data Services (XDS) Preprogrammed to Provide Full Compliance with EIA608 Specifications for Extended Data Services Automatic Extraction and Serial Output of Special XDS Packets (Time of Day, Local Time Zone, and Program Blocking) Programmable XDS Filter for a Specific XDS Packet Cost-Effective Solution for NTSC Violence Blocking inside Picture-in-Picture (PiP) Windows

Minimal Communications and Control Overhead Provide Simple Implementation of Violence Blocking, Closed Captioning, and Auto Clock Set Features Programmable, On-Screen Display (OSD) for Creating Full Screen OSD or Captions inside a Picture-inPicture (PiP) Window User-Programmable Horizontal Display Position for easy OSD Centering and Adjustment I2C Serial Data and Control Communication Supports 2 Selectable I2C Addresses

" #" $ 
Capable of processing Vertical Blanking Interval (VBI) data from both fields of the video frame in data, the Z86229 Line 21 Decoder offers a feature-rich solution for any television or set-top application. The robust nature of the Z86229 helps the device conform to the transmission format defined in the Television Decoder Circuits Act of 1990, and in accordance with the Electronics Industry Association specification 608 (EIA608). The Line 21 data stream can consist of data from several data channels multiplexed together. Field 1 consists of four data channels: two Captions and two Texts. Field 2 consists of five additional data channels: two Captions, two Texts, and Extended Data Services (XDS). The XDS data structure is defined in EIA608. The Z86229 can recover and display data transmitted on any of these nine data channels. The Z86229 can recover and output to a host processor via the I2C serial bus. The recovered XDS data packet is further defined in the EIA608 specification. The on-chip XDS filters in the Z86229 are fully programmable, enabling recovery of only those XDS data packets selected by the user. This functionality allows the device to extract the required XDS information with proper XDS filter setup for compatibility in a variety of TVs, VCRs, and Set-Top boxes. In addition, the Z86229 is ideally suited to monitor Line 21 video displayed in a PiP window for violence blocking, CCD, and other XDS data services. A block diagram of the Z86229 is illustrated in Figure 1.

#  

4072

PRELIMINARY DATA SHEET

MSP 34x0G
Current ICs have to perform adjustment procedures in order to achieve good stereo separation for BTSC and EIA-J. The MSP 34x0G has optimum stereo performance without any adjustments. All MSP 34xxG versions are pin compatible to the MSP 34xxD. Only minor modifications are necessary to adapt a MSP 34xxD controlling software to the MSP 34xxG. The MSP 34x0G further simplifies controlling software. Standard selection requires a single I2C transmission only. The MSP 34x0G has built-in automatic functions: The IC is able to detect the actual sound standard automatically (Automatic Standard Detection). Furthermore, pilot levels and identification signals can be evaluated internally with subsequent switching between mono/ stereo/bilingual; no I2C interaction is necessary (Automatic Sound Selection). The MSP 34x0G can handle very high FM deviations even in conjunction with NICAM processing. This is especially important for the introduction of NICAM in China. The ICs are produced in submicron CMOS technology. The MSP 34x0G is available in the following packages: PLCC68 (not intended for new design), PSDIP64, PSDIP52, PQFP80, and PLQFP64.

Multistandard Sound Processor Family Release Note: Revision bars indicate significant changes to the previous edition. The hardware and software description in this document is valid for the MSP 34x0G version B8 and following versions.

1. Introduction The MSP 34x0G family of single-chip Multistandard Sound Processors covers the sound processing of all analog TV-Standards worldwide, as well as the NICAM digital sound standards. The full TV sound processing, starting with analog sound IF signal-in, down to processed analog AF-out, is performed on a single chip. Figure 11 shows a simplified functional block diagram of the MSP 34x0G. This new generation of TV sound processing ICs now includes versions for processing the multichannel television sound (MTS) signal conforming to the standard recommended by the Broadcast Television Systems Committee (BTSC). The DBX noise reduction, or alternatively, Micronas Noise Reduction (MNR) is performed alignment free. Other processed standards are the Japanese FM-FM multiplex standard (EIA-J) and the FM Stereo Radio standard.

Sound IF1 ADC Sound IF2

Demodulator

Preprocessing

Loudspeaker Sound Processing

DAC

Loudspeaker Subwoofer

Source Select

I2S1 I2S2 SCART1

Headphone Sound Processing

DAC

Headphone

Prescale

I2S DAC

SCART2 SCART3 SCART4 MONO

SCART DSP Input Select

SCART1 ADC Prescale DAC SCART Output Select SCART2

Fig. 11: Simplified functional block diagram of the MSP 34x0G

Micronas

12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012

PI5V330

Product Features:
High-performance, low-cost solution to switch between video sources Wide bandwidth: 200 MHz Low ON-resistance: 3 Low crosstalk at 10 MHz: 58 dB Ultra-low quiescent power (0.1 A typical) Single supply operation: +5.0V Fast switching: 10 ns High-current output: 100 mA Packages available: 16-pin 300-mil wide plastic SOIC (S) 16-pin 150-mil wide plastic SOIC (W) 16-pin 150-mil wide plastic QSOP (Q)

Low ON Resistance Wideband/Video Quad 2-Channel MUX/DEMUX

Product Description:
Pericom Semiconductors PI5V series of mixed signal video circuits are produced in the Companys advanced CMOS low-power technology, achieving industry leading performance. The PI5V330 is a true bidirectional Quad 2-channel multiplexer/demultiplexer that is recommended for both RGB and composite video switching applications. The VideoSwitch can be driven from a current output RAMDAC or voltage output composite video source. Low ON-resistance and wide bandwidth make it ideal for video and other applications. Also this device has exceptionally high current capability which is far greater than most analog switches offered today. A single 5V supply is all that is required for operation. The PI5V330 offers a high-performance, low-cost solution to switch between video sources. The application section describes the PI5V330 replacing the HC4053 multiplier and buffer/amplifier.

Functional Block Diagram

S1A S2A S1B S2B S1C S2C S1D S2D DECODER/DRIVERS

DA DB

16-Pin Product Configuration

IN S1A

DC DD

S2A DA S1B S2B DB GND

1 2 3 4 5 6 7 8

16 15 14 16-PIN 13 Q16 12 S16 11 W16 10 9

VCC EN S1D S2D DD S1C S2C DC

Product Pin Description

EN IN
Pin Name S1A, S2A S1B, S2B S1C, S2C S1D, S2D IN EN DA, DB, DC, DD GND VCC Description Analog Video I/O

Truth Table
EN 0 0 1 IN 0 1 X ON Switch S1A, S1B, S1C, S1D S2A, S2B, S2C, S2D Disabled

Select Input Enable Analog Video I/O Ground Power

PS7032C

08/07/97

4272

4372

4472

4572

4672

4772

4872

Features
Low-Voltage and Standard-Voltage Operation
5.0 (VCC = 4.5V to 5.5V) 2.7 (VCC = 2.7V to 5.5V) 2.5 (VCC = 2.5V to 5.5V) 1.8 (VCC = 1.8V to 5.5V) Low-Power Devices (ISB = 2=A @ 5.5V) Available Internally Organized 4096 x 8, 8192 x 8 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate Write Protect Pin for Hardware Data Protection 32-Byte Page Write Mode (Partial Page Writes Allowed) Self-Timed Write Cycle (10 ms max) High Reliability Endurance: 1 Million Write Cycles Data Retention: 100 Years ESD Protection: >3,000V Automotive Grade and Extended Temperature Devices Available 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages

2-Wire Serial EEPROM

32K (4096 x 8) 64K (8192 x 8)

Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The devices cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions.

AT24C32 AT24C64

Pin Configurations
Pin Name A0 - A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect
A0 A1 A2 GND

8-Pin TSSOP
1 2 3 4 8 7 6 5 VCC WP SCL SDA

2-Wire, 32K Serial E2PROM

8-Pin PDIP
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA

8-Pin SOIC
A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA
Rev. 0336G04/01

4972

Absolute Maximum Ratings*

Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Block Diagram

Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the

Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0 are zero. WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC, all write operations to the upper quandrant (8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to GND.

Memory Organization
AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address.

AT24C32/64
5072

HT48R06A-1/HT48C06
8-Bit Cost-Effective I/O Type MCU
Features
Operating voltage: HALT function and wake-up feature reduce power

fSYS=4MHz: 2.2V~5.5V fSYS=8MHz: 3.3V~5.5V

13 bidirectional I/O lines An interrupt input shared with an I/O line 8-bit programmable timer/event counter with over-

consumption
Up to 0.5ms instruction cycle with 8MHz system clock

at VDD=5V
Allinstructionsinoneortwomachinecycles 14-bit table read instruction Two-level subroutine nesting Bit manipulation instruction 63 powerful instructions Low voltage reset function 16-pin SSOP package

flow interrupt and 8-stage prescaler

On-chip crystal and RC oscillator Watchdog Timer 102414 program memory ROM 648 data memory RAM Buzzer driving pair and PFD supported

18-pin DIP/SOP package

General Description
The HT48R06A-1/HT48C06 are 8-bit high performance, RISC architecture microcontroller devices specifically designed for cost-effective multiple I/O control product applications. The mask version HT48C06 is fully pin and functionally compatible with the OTP version HT48R06A-1 device. The advantages of low power consumption, I/O flexibility, timer functions, oscillator options, HALT and wake-up functions, watchdog timer, buzzer driver, as well as low cost, enhance the versatility of these devices to suit a wide range of application possibilities such as industrial control, consumer products, subsystem controllers, etc.

Block Diagram
1 6 2 + 

1 JA HHK F J + EH ? K EJ 5 6 ) + 2 H C H= 4 2 H C H= + K JA H 5 6 ) +  1  6 6 + 6 4 4 + 2 +  7 : 2 HA I ? = A H 6 4 2 +  B5
; 5

2 +  1 I JHK ? JE 4 A C EI JA H 2 7 :

, ) 6 ) A HO

9 , 6 5 9 , 6 2 HA I ? = A H 9 , 6 7 : 4 +  2 +  * * 4 6 * 2 *  2 * 2 + 

B5

; 5

"

2 + + 1 I JHK ? JE , A ? @ A H ) 6 E E C / A A H= J H 7 7 : 2 +

4 6 +

5 +

5 6 ) 6 7 5

2 * + 2 2 *

5 D EBJA H

2 ) + 2 5 + 5 +  4 - 5 8 , , 8 5 5

4 6 )

) + +

2 )

2 ) 

2 ) %

Rev. 1.30

August 7, 2003

5172

HT48R06A-1/HT48C06
Pin Assignment
2 ) !  ! " # $ %  & 6 '     2 ) !  ! " # $ % &      ' 2 ) 2 )  2 )  2 *  * 8 5 5 2 +  1 6 2 +  6 4  $  #  "  ! 2 ) " 2 ) # 2 ) $ 2 ) % 5 + 5 +  8 , , 4 - 5 2 ) 2 )  2 )  2 * 2 *  * 2 *  * 8 5 5 2 +  1  &  %  $  #  "  ! 2 ) " 2 ) # 2 ) $ 2 ) % 5 + 5 +  8 , , 4 - 5 2 +  6 4

0 6 " & 4  $ )  0 6 " & +  $  $ 5 5 2 )

0 6 " & 4  $ )  0 6 " & +  $  & , 12 ) 5 2 )

Pad Assignment
HT48C06
2 )   & 2 )  % 2 ) !  $        ! " # 8 5 5 2 *  * $ % & 4 - 5 2 +  6 2 +  1 ' 8 , ,   2 ) "  # 2 ) #  " 2 ) $  !

2 )  2 * 2 *  *

2 ) % 5 +

5 + 

* The IC substrate should be connected to VSS in the PCB layout artwork.

6 4

Rev. 1.30

August 7, 2003

5272

HT48R06A-1/HT48C06
Pad Description
Pad Name I/O Options Pull-high* Wake-up Description Bidirectional 8-bit input/output port. Each bit can be configured as wake-up input by options. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). Bidirectional 3-bit input/output port. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). The PB0 and PB1 are pin-shared with the BZ and BZ, respectively. Once the PB0 and PB1 are selected as buzzer driving outputs, the output signals come from an internal PFD generator (shared with a timer/event counter). Negative power supply, ground Bidirectional I/O lines. Software instructions determine the CMOS output or Schmitt trigger input with a pull-high resistor (determined by pull-high options). The external interrupt and timer input are pin-shared with the PC0 and PC1, respectively. The external interrupt input is activated on a high to low transition. Schmitt trigger reset input. Active low Positive power supply OSC1, OSC2 are connected to an RC network or Crystal (determined by options) for the internal system clock. In the case of RC operation, OSC2 is the output terminal for 1/4 system clock.

PA0~PA7

I/O

PB0/BZ PB1/BZ PB2

I/O

Pull-high* I/O or BZ/BZ

VSS

PC0/INT PC1/TMR

I/O

Pull-high*

RES VDD OSC1 OSC2

I I O

Crystal or RC

* All pull-high resistors are controlled by an option bit.

Absolute Maximum Ratings

Supply Voltage ...........................VSS-0.3V to VSS+6.0V Input Voltage..............................VSS-0.3V to VDD+0.3V Storage Temperature ............................-50C to 125C Operating Temperature...........................-40C to 85C

Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.

Rev. 1.30

August 7, 2003

5372

HT48R06A-1/HT48C06
D.C. Characteristics
Symbol Parameter Test Conditions VDD 3V Operating Current (Crystal OSC) 5V IDD2 IDD3 ISTB1 3V Operating Current (RC OSC) 5V Operating Current (Crystal OSC) Standby Current (WDT Enabled) 5V ISTB2 3V Standby Current (WDT Disabled) 5V VIL1 VIH1 VIL2 VIH2 VLVR IOL Input Low Voltage for I/O Ports, TMR and INT Input High Voltage for I/O Ports, TMR and INT Input Low Voltage (RES) Input High Voltage (RES) Low Voltage Reset I/O Port Sink Current 5V IOH 3V I/O Port Source Current 5V RPH 3V Pull-high Resistance 5V VOH=0.9VDD 3V LVR enabled VOL=0.1VDD No load, system HALT 5V 3V No load, system HALT No load, fSYS=8MHz No load, fSYS=4MHz Conditions fSYS=4MHz fSYS=8MHz No load, fSYS=4MHz Min. 2.2 3.3 0 0.7VDD 0 0.9VDD 2.7 4 10 -2 -5 40 10 Typ. 0.6 2 0.8 2.5 3 3.0 8 20 -4 -10 60 30 Max. 5.5 5.5 1.5 4 1.5 4 5 5 10 1 2 0.3VDD VDD 0.4VDD VDD 3.3 80 50 Ta=25C Unit V V mA mA mA mA mA mA mA mA mA V V V V V mA mA mA mA kW kW

VDD

Operating Voltage

IDD1

Rev. 1.30

August 7, 2003

5472

FHP A3 PANEL DATASHEET

5572

FHP A3 PANEL DATASHEET

5672

FHP A3 PANEL DATASHEET

5772

FHP A3 PANEL DATASHEET

5872

FHP A3 PANEL DATASHEET

5972

FHP A3 PANEL DATASHEET

6072

FHP A3 PANEL DATASHEET

6172

FHP A3 PANEL DATASHEET

6272

FHP A3 PANEL DATASHEET

6372

FHP A3 PANEL DATASHEET

6472

FHP A3 PANEL DATASHEET

6572

FHP A3 PANEL DATASHEET

6672

FHP A3 PANEL DATASHEET

6772

Spare Part List for PDP4273M

Date: 2006/01/05

Item 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

Part Number E6205-42BD01 900-420203-01B 786-421D01-01 771E421D01-01 771L421D01-01 E7801-081001 771-421D01-04 771-421D01-02 E7801-200001 771-421D01-05 E4101-027001 E4801-125001 E4802-015001 205-42SD03-01R 206-42SD02-01R E3219-002003 E3404-157001 E3421-927007 E3421-927008 E3421-925020 E3421-926095 E3421-926054 E3421-926055 E3421-926107 E3421-925057

Part Description 42 ED PDP MODULE 42 GLASS FILTER SPK ASSY FOR 421D(4273M) SILVER MAIN PCBA AUDIO PCBA POWER PCBA KEY PCBA RCA CONVERT PCBA PCB ASSY PSU MAIN FPF23P-100/240A MURATA IR RECEIVE PCBA POWER SWITCH SPEAKER TWEETER SPEAKER FRONT CABINET SPEAKER BACK CABINET POWER SWITCH AC POWER CORD WIRE ASSY 6P L=900MM EMI FOR (FORMOSA) WIRE ASSY 3P L=450 AC CORD FORMOSA EMI WIRE ASSY 300MM 3WIRES FOR 42 LCD POWER CONNECT WIRE ASSY 1.25MM 20P/30P L=450 (LVDS W-EMI) FOR FHP WIER ASSY 6P/6P 2.5MM L=260MM EMI WIRE ASSY 11P/5P+5P 2.5MM L=340MM EMI WIRE ASSY P2.5 3P L=200 FOR AUDIO CONVERT WIRE ASSY 2.0 9P/9P L=150MM FOR (FHP MAIN POWER TO DIF BOARD) WIRE ASSY 3.96 8P/8P L=230MM FOR (FHP MAIN POWER TO XSUS BOARD)

Usage / unit 1 1 1 1 1 1 1 1 1 1 1 4 2 1 1 1 1 1 1 1 1 1 1 1 1

Unit piece piece set set set set set set set piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece

26

E3421-925058

Piece

6872

Spare Part List for PDP4273M

Date: 2006/01/05

Item 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62

Part Number E7501-052001 E7301-010002 277-46SD01-03S 267-46SD01-01S 269-46SD01-01S 481-42D116-01S 483-42D103-01 436-421D02-01S 402-42D107-01S 248-46D201-01 510-421D01-SMU01K 518-421D01-01K 300-42SD03-02C 300-42SD04-02C 300-42SD05-01C 244-34B811-01 310-504505-01T 310-041104-01V 310-111404-07V 580-P421DHS-MU01L 579-50AA02-01 388-421D01-01H 388-42SB04-01H 388-42D103-01H 387-421D01-SMU01H 384-42D103-SMU02H 590-421D01-01 593-421D01-01 579-42D102-09 579-421D01-01 579-42D103-02 568-P46T02-02 579-42D105-01 579-421D03-01 734-BM0306-01

Part Description REMOTE CONTROL AAA SIZE BATTERY FUNCTION KNOB POWER LENS REMOTE RECEIVE LENS PCBA SHIELD BOX PCBA SHIELD TOP COVER TERMINAL FRAME METAL BACK COVER HANDLE FOR PLASMA TOP CARTON BOX BOTTOM CARTON BOX TOP CUSHION BOTTOM CUSHION POLYFOAM SHEET CARTON BOX HANDLE MAIN UNIT PLASTIC BAG POLYBAG 4"X11"X0.04 INSTRUCTION MANUAL PLASTIC BAG11"X14"X0.04 INSTRUCTION MANUAL DANGER CAUTION LABEL SPEAKER INPUT PLATE POWER SOCKET LABEL CAUTION LABEL MODEL PLATE LABEL TERMINAL LABEL WARRANTY SHEET INSERTION CARD MODEL PLATE SERIAL NUMBER BAR CODE LABEL POWER SWITCH LABEL WARNING LABEL PROTECTIVE EARTH LABEL POP LABEL STAND BASE

Usage / unit 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1

Unit piece pair piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece piece Piece piece piece piece piece piece piece Set

200-42D141-SMK01AV FRONT CABINET BLACK

6972

If you forget your V-Chip Password

- Omnipotence V-Chip Password: 5898. - Press MENU button. - Press Up, Down buttons to highlight "V-Chip" Control. - Press OK button to pop up "INPUT PASSWORD". - Use the Number buttons (0~9) to enter the omnipotence Password 5898. - Press Down to highlight "Password change" Control. - Press OK button to confirm and will pop up "Password Change" item. - Change to your familiar Password again.

Software upgrade
- Connect the RS-232C input jack to an external control device (such as a computer) and software upgrade.

Type of connector; D-Sub 9-pin male

No. 1 2 3 4 5 6 7 8 9 Pin name No connection RXD (Receive data) TXD (Transmit data) DTR (DTE side ready) GND DSR (DCE side ready) RTS (Ready to send) CTS (Clear to send) No Connection

1 5

9 6

RS-232C configurations
7-wire configuration (Standard RS-232C cab PC PDP PC 3-wire configuration (For PDP software upgrade) PDP

RXD TXD GND DTR DSR RTS CTS

2 3 5 4 6 7 8
D-Sub 9

3 2 5 6 4 8 7
D-Sub 9

TXD RXD GND DSR DTR CTS RTS

RXD TXD GND DTR DSR RTS CTS

2 3 5 4 6 7 8
D-Sub 9

3 2 5 4 6 7 8
D-Sub 9

TXD RXD GND DTR DSR RTS CTS

7172

Software upgrade Process

- Power Switch OFF. - Connect the serial port of the control device to the RS-232 jack on the PDP back panel. RS-232C connection cables are not supplied with the PDP. - Power Switch ON. The power indicator on the front of the panel should now display red, means that the PDP is in standby mode. - Copy the software (Flash Upgrader) to the computer. - Open the software (Flash Upgrader.exe) - Point "Flash" on the interface of the Flash Upgrader.exe. - Press STANDBY button on the front panel or POWER button of Remote control, Power indicator green, the PDP is in power ON mode, software start upgrader immediately. - Waiting for the upgrader programing, when it is finished, the PDP will auto power on. - After the upgrader is finished, shut down the power switch, take out the RS-232C connection after the power indicator is extinguished. Note: The computer and PDP must be keep Power ON in the software upgrade processing.

7272