Scribd Logo
Upload

Welcome to Scribd!

  • Different Low Power Techniques: Trade-Offs Associated With The Various Power Management Techniques

    Uploaded by

    naveen silveri
    36 views2 pages
    The document discusses various low power techniques for SoC designs including dynamic power control techniques like clock gating and variable frequency, and leakage power control techniques like power gating and multi Vt cells. It notes that power gating and dynamic voltage and frequency scaling require more changes than techniques like multi Vt or clock gating. Unless large leakage optimization is needed, techniques like multi Vt or clock gating are generally beneficial. The best approach combines techniques based on design complexity and requirements.

    Original Description:

    good

    Original Title

    lpdesing.docx

    Copyright

    © Attribution Non-Commercial (BY-NC)

    Available Formats

    DOCX, PDF, TXT or read online from Scribd

    Did you find this document useful?

    Is this content inappropriate?

    Report this Document
    The document discusses various low power techniques for SoC designs including dynamic power control techniques like clock gating and variable frequency, and leakage power control techniques like power gating and multi Vt cells. It notes that power gating and dynamic voltage and frequency scaling require more changes than techniques like multi Vt or clock gating. Unless large leakage optimization is needed, techniques like multi Vt or clock gating are generally beneficial. The best approach combines techniques based on design complexity and requirements.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    36 views2 pages

    Different Low Power Techniques: Trade-Offs Associated With The Various Power Management Techniques

    Uploaded by

    naveen silveri
    The document discusses various low power techniques for SoC designs including dynamic power control techniques like clock gating and variable frequency, and leakage power control techniques like power gating and multi Vt cells. It notes that power gating and dynamic voltage and frequency scaling require more changes than techniques like multi Vt or clock gating. Unless large leakage optimization is needed, techniques like multi Vt or clock gating are generally beneficial. The best approach combines techniques based on design complexity and requirements.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    Download as docx, pdf, or txt
    of 2

    Michael Keating et al.

    [1] lists several low power techniques to tackle the dynamic and static power consumption in modern SoC designs. Dynamic power control techniques include clock gating, multi voltage, variable frequency, and efficient circuits. Leakage power control techniques include power gating, multi Vt cells. Common methods supported by EDA tools include clock gating, gate sizing, low power placement, register clustering, low power CTS, multi Vt optimization. Some of the low power techniques in use today are listed in below table.

    Different Low Power Techniques

    Trade-offs associated with the various power management techniques [2]Above table summarizes

    trade-

    offs associated with different power management techniques. Power gating and DVFS demand large methodology change whereas multi vt and clock gating affect least. Unless large leakage optimization is not necessary it is always beneficial to go with either multi vt or clock gating techniques. Based on the design complexity and requirements combination of any low power techniques can be adopted. Multi vt optimization along with the power gating is found to be efficient in some of the complex designs. Advanced improvements in the implementation (i.e. fabrication) technology has allowed substrate biasing techniques to be used heavily as it does not pose any architectural and design verification challenges and also provides high leakage reduction.

    "Latch" Vs "Flip Flop"


    A flip-flop is Edge sensitive: Output only changes on rising (or falling) edge of clock. A latch is Level sensitive: Output changes whenever clock/Enable is high (or low) A common implementation of a flip-flop is a pair of latches (Master/Slave flop). Latches are sometimes called transparent latches, because they are transparent (input directly connected to output) when the clock is high. The clock to a latch is primarily called the enable. For more information have a look at the picture below.

    Deprecated Hardware: Latches: Use flops, not latches 1. Latch-based designs are susceptible to timing problems 2. The transparent phase of a latch can let a signal leak through a latch causing the signal to affect the output one clock cycle too early 3. Its possible for a latch-based circuit to simulate correctly, but not work in real hardware, because the timing delays on the real hardware dont match those predicted in synthesis Flip-flops: 1. Limit yourself to D-type flip-flops 2. Some FPGA and ASIC cell libraries include only D-type flip flops. Others, such as Alteras APEX FPGAs, can be configured as D, T, JK, or SR flip-flops.

    For every signal in your design, know whether it should be a flip-flop or combinational. Examine the log file e.g. dc shell.log to see if the flip-flops in your circuit match your expectations, and to check that you dont have any latches in your design. Do not assign a signal to itself (e.g. a <= a; is bad). If the signal is a flop, use an enable to cause the signal to hold its value. If the signal is combinational, then assigning a signal to itself will cause combinational loops, which are very bad.

    You might also like