April 15, 2008

MODERATOR:
Aaron Hand Executive Editor, Electronic Media Semiconductor International

Ultra-high purity chemical pumps, mixers, and liquid heaters

www.idex-hs.com

April 15, 2008

MODERATOR:
Aaron Hand Executive Editor, Electronic Media Semiconductor International

Panelists
Jeffrey Butterbaugh Chairman, ITRS Front End Processes TWG Chief Technologist FSI International Anthony Muscat Associate Professor Department of Chemical & Environmental Engineering University of Arizona D. Martin Knotter Senior Principal Scientist Contamination Expertise Center NXP Semiconductors Brian Kirkpatrick Senior Member of Technical Staff Texas Instruments
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

A View of The Challenges From the 2007 ITRS

Jeffery W. Butterbaugh FSI International 3455 Lyman Boulevard Chaska, Minnesota 55347 USA phone: 952-448-8089 e-mail: jeff.butterbaugh@fsi-intl.com

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

The Crux of the Scaling Problem

. . . . traditional transistor and capacitor formation materials, silicon, silicon dioxide, and polysilicon have been pushed to fundamental material limits and continued scaling has required the introduction of new materials. The current situation can be defined as materiallimited device scaling. In addition, new approaches to device structure, such as non-planar multi-gate devices, will be needed for future performance scaling. . . .

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

More than Moore

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Front End Surface Preparation

2007 Highlights
Excerpts from Table FEP3a Front End Surface Preparation Requirements

Watermarks metric removed from table

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Thermal/Thin Films/Doping

2008

2011 2010

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

2007 Highlights
Excerpts from Table FEP4a Thermal/Thin Films/Doping/Etch Requirements

Etch

Atomic Layer Etching adding to potential solutions table

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Stacked DRAM
2007 Highlights
Excerpts from Table FEP5a DRAM Stacked Capacitor Requirements

Excerpts from Figure FEP7 DRAM Stacked Capacitor Potential Solutions

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

2007 Highlights
Excerpts from Table FEP7 Flash Requirements

Flash

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Perspective on Front End of Line Wafer Cleaning Solutions for 45 and 32 nm

Anthony Muscat Department of Chemical and Environmental Engineering University of Arizona, Tucson, AZ 85721

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Novel Materials and Device Issues

Fermi level pinning Cleaning multicomponent substrates Passivate and tie up dangling bonds Closer integration of surface preparation with deposition

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Fermi Level Pinning at Critical Interfaces

Passlack et al., IEEE Electron Device Letters 23(9) (2002) 508.

Electronic states in the bandgap at AlGaAs/Ga2O3 interface full of electrons, which pins Fermi level in depletion mode devices
O at interface pins III-V materials

Causes of Fermi level pinning/unpinning at oxide/III-V interfaces not well understood

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Cleaning Multicomponent Substrates: InAs

Liquid phase HF on InAs(100)

Removed In2O3 and As2O5 As-rich bulk metal and overlayer contained As2O3 but not As-F As atoms could be responsible for Fermi level pinning
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Cleaning Multicomponent Substrates: InSb

Liquid phase HF on InSb(100)

Removed In2O3 and Sb2O5 Sb-rich overlayer contained Sb-F Bulk InSb stoichiometric
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Integrated Clean and Deposition: Al2O3 on InSb

Interfacial reaction between surface species and ALD precursors

Reacted In2O3 and InF3 Reacted elemental As and AsF 3 to As2O5 and As2O3 Large driving force to form bonds with Al
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Wafer Environment Control

Martin Knotter Impact determination MEDEA+ 2T102 HYMNE WP3.1 April, 02, 2008

Challenges for 32 and 45 nm technology

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Challenge Is: What Do We Really Need?

Specification in Wafer Environment and Surface Contamination are based on (order of occurrence):
1. Best available on the market (supplier driven, sometimes because customer X asks) 2. Extrapolations from the past 3. Short loops 4. Fab X, with unknown contamination finger print and fudge kill ratios

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Do We Understand Failure Path?

Where? How? Contaminant in water/air

When? How?

Contaminant on wafer

Failing dies

It is not easy to use controlled contamination in a wafer fab for impact determination statistics of noise of unknown origin
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

HYMNE Work Package 3.1 Impact Determination High Yield driven MaNufacturing Excellence in sub 65 nm CMOS
is a European Project
Partners in WP3.1:

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

NEW Work in Progress: Non-uniform Contamination

Uniform distribution is the spec (partly because of analytical limitation) Do we have a serious analytical issue?
3.1.1. Controlled contamination 3.1.2. Short Loops (see Adrien Danel Surface Potential Measurements) 3.1.3. Kill ratio analysis (see Faisal Wali: particles in Fab X) 3.1.4. Deposition Probability (see Y. Borde: metal contamination through solid contacts)

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

NXP Contribution
Impact of random contamination is best determined in mature fabs
NXP turns into automotive and already finds impact in their 350-nm products

Automotive and not advanced CMOS is the driver for contamination specifications?

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Summary of Statements
1. The contamination roadmap is supplier driven, while IC manufacturer should tell the supplier what he needs (based on facts) 2. We have an analytical problem for quantification of non-uniform contamination 3. Automotive requirements should drive the contamination roadmap

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Front End of Line Wafer Cleaning Solutions for 45 and 32 nm

Brian Kirkpatrick External Development and Manufacturing Texas Instruments b-kirkpatrick1@ti.com

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

 Energy conservation
Economics

Surface Preparation Impact on Device Performance

Its not just gasoline Ioff as important as Ion Not just battery operated

Which devices

Increasing consequences
Heat dissipation Reliability Battery life Average device packing density will diverge from Moores Law unless Jg held constant with decreasing Toxinv

Macro level problems Cooling server farms

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Surface Preparation Impact on Device Performance

Resulting change in requirements
Jg reduction
High-k dielectrics
Can theoretically reduce Jg by a factor of 100 Hf- and Zr-based oxides and silicates

Roughness of any kind must be controlled

Surface roughness Line edge roughness (LER) Corner rounding

Controlling Work Function

Dual work function metal gates Midgap metal nitrides, capping layers, low WF metal silicides, high WF noble metals
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Surface Preparation Impact on Device Performance

Cross-contamination concerns for high-k / metal gates
Restricting tool usage Backside cleans to allow some sharing (metrology, photolithography, not high temperature) Rigorous testing methods

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Surface Preparation to Support Structure Formation

High-k / metal gate integration approach drives surface preparation steps
Mid bandgap, or dual work function approach FUSI, gate first, partial gate first or gate last

FUSI

For surface preparation, almost all process changes driven by first three choices Silicide like cleans early in flow Similar integration as polysilicon gates Similar challenges with significantly different materials (dual work function complicates issue) Some process steps drive alternate chemistries that are dependant on tool capabilities
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Gate first

Surface Preparation to Support Structure Formation

Example; Post gate etch clean Brief exposure to concentrated chemistry ideal. If brief exposure not possible, then achieve required cleaning capability and etch selectivity by moving to higher temperatures with the buffers to modify pH.

Partial gate first

Wet processes being used to remove the replacement gate electrode
High-k material exposed during wet etch Extreme selectivity requirement Sidewalls and LDD implants may already be in place Post CMP clean involving metals required around the gate process step

Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Surface Preparation to Support Structure Formation

Managing material consumption
Not just silicon (see separate presentation)
Isolation Loop = Active silicon Gate Loop = Silicon recess USJ Loop = Sidewall loss, silicon recess SiGe Loop = Sidewall loss, silicon recess profile and depth control Contact = Sidewall profile, silicide consumption

Eliminating unnecessary cleans (again) Optimizing and minimizing photo reworks Process changes
Increased use of single wafer tools Paradigm shift
FEOL; Less ash All wet BEOL; Insitu ash (within plasma etch tools) External process
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Surface Preparation to Support Structure Formation

Through-silicon vias (TSVs)
Advanced interconnect method
Post-etch cleans with huge, deep trenches exposed Dependant on integration, micro-machining like steps may be required TSVs require post-CMP clean on very thin wafers
Wafer carriers Need to completely remove damaged layer

MuGFETs High-mobility channels

Ge, III-V compounds (GaAs) on horizon Carbon nanotubes, graphenes, InAs and InSb starting to be discussed
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008

Panelists
Jeffrey Butterbaugh Chairman, ITRS Front End Processes TWG Chief Technologist FSI International Anthony Muscat Associate Professor Department of Chemical & Environmental Engineering University of Arizona D. Martin Knotter Senior Principal Scientist Contamination Expertise Center NXP Semiconductors Brian Kirkpatrick Senior Member of Technical Staff Texas Instruments
Webcast: Wafer Cleaning Solutions for 45 and 32 nm, Semiconductor International, 4/15/2008