ADA Conversion Project Oriented Laboratory

lektronik abor
Laboratory on Digital and Mixed-Signal Computer-Aided Design Automation
A / D / A Conversion System Using DE2 and DA2 Boards
Prof. Dr. Martin J. W. Schubert Electronics Laboratory Regensburg University of Applied Sciences Regensburg
M. Schubert
(P)RED: System Design for DSP Using the DE2 and DA2 Boards
Regensburg Univ. of Appl. Sciences
Abstract. A A/D converter and a D/A converter is to be explained and built using the DE2 and DA2 boards. This document details several modules of the project.
1 Introduction
System Layer
requirements freeze
Requirement Analysis System Design

Iteration
System Test Integration Test Functional Test Module Test Module Implementation
system release
test freeze
Subsystem Layer design freeze
Subsystem Design Module Design
implementation freeze
Module Layer
Fig. 1: V-Model as model to precede with coding and testing of the modules. This tutorial is addressed to three groups of students: 1. A//D and D/A conversion with emphfasis on modulation, 2. Digital signal processing (DSP) and 3. Digital circuit design using VHDL [1], [2], [3] and Matlab [4], [5], [6] and the Altera DE2 board [7], [8], [9]. Preconditions: This tutorial presumes that the user is familiar with the authors document Getting Started with DE2 and DA2 Boards [10]. Furthermore how write state-machines using VHDL [11] and Matlab [12] and some cases how to handle fixed-point numbers [13].
Experience has shown that the most important precondition of circuit design is to understand the functionality and translate it into a clear schematics. Take a sheet of paper or any graphics program to do so, name all components and signals, assign bit-widths and the signal-flow directions. Show it to your supervisor.
The organization of this document is as follows: Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Chapter 6 introduction, presents system- and subsystem-layer information. presents theoretical background and laboratory project tasks on DSP theory, preferably to be solved with Matlab, module layer: laboratory VHDL project tasks. draws relevant conclusion.
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2 System and Subsystem Layer

2.1 Requirement Analysis
analog
ADC
digital
DAC
analog
Fig. 2.1: Requirement: Analog-to-digital converter (ADC) and digital-to-analog converter (DAC) as interfaces to the analog world for a Field-Programmable Gate Array (FPGA). Given is the Altera DE2 Evaluation board [7], [8], [9], [10] operating an Altera Cyclone II FPGA [7], [9]. Interaction with the analog world requires an ADC that converts an analog voltage to digital and a DAC that converts digital data to analog voltages.
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2.2 System Layer

(a) engen
(enable-flags generator) 10 MHz 1 MHz 100 KHz 10 KHz 1 KHz 100 Hz 10 Hz 1 Hz
(b)
eff
c d e CLOCK_50 ck r global_reset q c
(c)
z-1
global_enable CLOCK_50
enable clock_50MHz
global_reset
sel1 3 analog world
mux0
en0 cDsr
sel2 3
mux2
en2
sel0 3
mux1
en1 analog world
Uadc,in
rate: fs0
ADC
DsAdcOut
cAdcOutWidth data rate: fs2
Ddac,in DAC mux

cDacInWidth data rate: fs2 cUsr rate: fs1
Udac,out
Freq clock enable reset
OscOut
digital harmonic
oscillator
cOscOutWidth
User Logic
dac1dout dac2dout
display
76 54 3210
DsAdcOut
(a) A/D - D/A conversion system, (b) FF design view, (c) FF DSP view, (d) Top-level view synthesized by Quartus II 8.1 [7], [9], [16]. Fig. 2.2: Top-level view oc component de2_adac : Sketched (above) synthezied (below).
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Part(a) of the figure illustrates the block diagram of the digital parts of the A/D/A Conversion system within the DE2 board, contained in the top-level component de2_adac. engen: Enable-flag generator: CLOCK_50: input signal, 50MHz clock rate, global_enable: input global enable, typically connected to push-button key[1], global_reset: input global enable, typically connected to push-button key[0] envec(7:0): output-enable vector, envec(x) is '1' for one out of 10x clock cycles.
muxi:
8-input multiplexer: envec(7:0): input signal, envec(x) is '1' for one out of 10x clock cycles. seli: input select signal, integer range 0...7, eni: output-enable vector, eni=envec(seli). In the de2_adac component the user selects fs2 by sw(2:0) while and the oversampling rates fs0 , fs1 are computed. Uadc,in: input voltage, models as VHDL signal of type REAL. en0: input enable signal, determines oversampling frequency fs0, cDsr: input constant, down-sampling ratio: cDsr = fs0 / fs2, Dadc,out: digital output word of the ADC delivered at data rate fs2.
ADC: ADC (for ModelSim simulation [14], [15] analog part modeled behavioral):
DAC: DAC (for ModelSim simulation [14], [15] analog part modeled behavioral):
Ddac,in: digital output word of the ADC delivered at data rate. en1: input enable signal, determines oversampling frequency fs1, cUsr: input constant, up-sampling ratio: cUsr = fs1 / fs2, Udac,out: analog output voltage, delivered at data rate fs1. oscillator: A harmonic digital oscillator which can be used to test the DAC without ADC. display: 7-segment display driver.
Part (b) of the figure illustrates that all flipflops of this design receive the same global reset signal and the same clock signal. The global_reset, typically connected to push-button key[0] of DE2 board [7], [10]. The clock input of all flipflops will typically driven by signal CLOCK_50, a 50MHzclock signal supplied by Altera [7]. A rising clock edge can toggle a flipflop when its enable entry is '1'. Part (c) of Fig. 2.2 shows the data processing view of a flipflop with a number of c input/output bits. The sampling frequency fs is enclosed within z=ejT whereat T=1/fs. Part (d) of Fig. 2.2 shows the comlete system after Top-level view synthesized by Quartus II 8.1 [7], [9], [16]..
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2.3 Subsystem Layer

(a) X integrator quantizer Y lowpass f X'
constant k modulator demodulator
(b) U
(analog)
sclk
m digital lowpass
(c)
n
sclk
m<n DAC quantizer analog lowpass (analog)
(digital) (digital)
ADC DAC
Fig. 2.3: (a) principle: quantizer in a loop as modulator and lowpass as demodulator, (b) application as A/D converter and (c) D/A converter. We have decided to use modulators for A/D and D/A conversion. They trade oversampling ratio (i.e. speed) versus accuracy. A commercial reason for such a choice is that this converter type moves most of the hardware efforts from the analog to the digital side. For educational purposes this modulator is very suitable to highlight many aspects of digital signal processing (DSP). Fig. 2.3(a) illustrates the principle of modulation [17]-[20]: A quantizer lowers the bitwidth of the data stream, often to a single bit with a comparator as quantizer. This loss in data accuracy is compensated for by driving an oversampled loop such, that the input data is coded as mean value of the output data stream. To regain the input accuracy we have to extract the mean value of the modulated data stream, which is done by a lowpass. Consequently, a lowpass is a demodulator. Fig. 2.3(b) illustrates the application of modulation / demodulation for A/D conversion: The loop extends over both analog an digital domain. The domain boundaries are crossed by the A/D and D/A converters, whereat the ADC is also the quantizer. Demodulation is done with a digital lowpass containing the biggest part of digital signal processing problems. Fig. 2.3(c) illustrates the application of modulation / demodulation for D/A conversion: The loop extends the digital domain only. The domain boundary is crossed by a coarse resolution (often 1 bit) D/A converter, the input accuracy is regained on the analog side by averaging, performed by the lowpass. This lowpass can be realized physical device, e.g. simply as mass.
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3 Theoretical Background
3.1 Sampling, Aliasing and Anti-Aliasing Filters
In the analog domain we use indices A and B, for attenuation and bandwidth, in the digital domain we use indices C and D for cutoff and damping, respectively.
3.1.1
Required Anti-Alias Attenuation for M-Bit A/D Conversion

) U = . 2
The effective voltage of sinusoidal signal with Amplitude is: U s , eff This sinusoidal voltage has a peak-to-peak voltage of 2.
Assuming that this 2 exactly cover the input voltage range of a M-bit ADC, then this ) ) 2U 2U M M voltage span is subdivided into 2 -1 2 steps of size = M . 2 1 2M Assuming that quantization errors have the same probability to occur within the interval -/2.../2, then the effective quantization noise voltage is U q , eff = (p.336 of [21]). 2 3 ) ) 2U / 2 M U = = M Consequently, the signalInserting the model for delivers U q , eff = 2 3 2 3 2 3 to-noise ratio caused by the ADCs quantization process is SNR = Psignal Pnoise U s , eff = U q , eff = 2M 3 2
2 2
M 3 SNRdB = 10 log10 ( SNR) = 20 log10 2 2
As a factor 2 corresponds to one bit on the one hand and to 20 log10 (2) = 6.0206dB on the other, and a factor 3 / 2 corresponds to 20 log10 3 / 2 = 1.7609dB , the signal-to-noise ratio produced by the quantization process of a M-bit quantizer can be expressed as SNRdB = 10 log10 ( SNR ) = ( M 6.02 + 1.76)dB . If the signal power of sin(2ft) has to be attenuated to the quantization-noise power of a least significant bit (LSB or ) for f fA, then the required attenuation of such frequencies is AdB = SNRdB = (M 6.02 + 1.76)dB . If the power of an aliasing signal sin(2ft) has to be suppressed to the impact of a half LSB of the ADC, then the required attenuation for f fA is AdB = (( M + 1) 6.02 + 1.76)dB = (M 6.02 + 7.78)dB .
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3.1.2
Required Order of Anti-Aliasing Filters

0 lH(jf)l / dB AdB fB fA log f
Bandwidth fB denotes the filters pass-band. Stop-band attenuation A is guaranteed for f fA and AdB=20log10(A). Assume equal amplitudes at the filters input. Then UB the pass-band and UA the attenuated stop-band output amplitude, so that UA AUB.
Fig. 3.1.2: lowpass asymptotes.
Abbreviating "log10" with "lg" the required filter order is

N | AdB | lg(U A ) lg(U B ) lg(U A / U B ) = = lg( f A ) lg( f B ) lg( f A / f B ) 20dB lg f A fB
| AdB | N = ceil fA 20dB lg f B
With function ceil for rounding up minimum filter order is
Example: AdB = -60dB, fB=2KHz, fA = 8 KHz N ceil(4.98) N = 5.

Consequences: ADCs use high sampling rates to relax the demands of analog antialiasing filters. Principle: fA in the formula above is replaced by fA=fs-fD with fs being the sampling rate and fs 2fD. Consequently, filter-order reduction is proportional to
N ~ 1/log((fs-fD)/fB) 1/log(fs) if fs. For moderate sampling rates fs, when the slope of the log function is large, the success is strong but decreases with increasing fs. On the other hand, we will see in chapter 3.2 that the costs of digital anti-aliasing filters increase ~fs2 but can be alleviated by using zeros of particular filters (so-called sinc-filters). Search the optimum solution on system level.
Practical Comment: If anti-aliasing filtering is necessary, a Butterworth filter is appropriate. It has a flat baseband transfer function and 3dB attenuation in the asymptotes kink at fB, independently from filter order N.
Butterworth lowpass transfer function: | H BW ( jf ) |=
1 1+ ( f / fB )
2N
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3.1.3
Matching Analog Anti-Aliasing and Digital Lowpass Filters

digital lowpass aliasing
lHfilterl / dB analog anti-aliasing filter 0 digital lowpass
AdB
f'n
fC
fD fB
fs/2
fA= fs-fD
fs-fC
fn1
fs
fn2
fs+fC
fs+fD
Fig. 3.1.3: Necessity for an analog anti-aliasing filter: Guarantee sufficient attenuation at fA=fs-fD to suppress aliasing e.g. from fn to f'n.
Sampling at frequency fs aliases frequencies fn > fs to f'n = |fn-kfs| with k being an integral number such that f'n < fs. A sampler followed by a digital filter with cutoff frequency fC and desired damping reached at fD will alias all frequencies in the bands kfsfD into the range 0...fD. To avoid this an analog anti-aliasing filter has to be applied before the sampler that guarantees the desired suppression of alias noise as illustrated by the red dashed curve in Fig. 3.1.3. For this reason, most A/D conversion systems have analog anti-aliasing lowpasses before the sampler. An exception are ADCs: Due to their high sampling frequency they have no or very relaxed anti-aliasing lowpasses in the analog domain and perform the lowpass filtering after sampling in the digital domain. Pushing circuitry from the analog to the digital domain is a main reason for their high acceptance for practical applications.
3.1.4
Examples: Tailoring Analog Anti-Aliasing Filters
Exercise 1: Given is a 8-bit ADC. Aliasing noise power must not exceed the quantization noise power of a half LSB. What is the required attenuation of aliasing frequencies? ............................................................... ............................................................... Exercise 2: Situation sketched in Fig. 3.1.4(a): The ADC feeds a telecommunication line, sampling frequency fs=8KHz, baseband edge fB=3.4KHz. What is the required order of the analog anti-aliasing filter?
...............................................................
...............................................................
...............................................................
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(a)
lHfilterl / dB analog antialiasing filter 0 aliasing fs/2
AdB
f' n
fB
fA
fn1
fs
fn2
fn3
2fs
fn4
(b)
lHfilterl / dB analog anti-aliasing filter 0 digital lowpass aliasing digital lowpass
AdB
f' n
fC
fD fB
fs/2
fA= fs-fD
fs-fC
fn1
fs
fn2
fs+fC
fs+fD
Fig. 3.1.4: Demands for an analog anti-aliasing filter: Guarantee sufficient attenuation at fA=fs-fD to suppress aliasing signals e.g. from fnx to f'n. Exercise 3: Situation sketched in Fig. 3.1.4(b): The bandwidth available for the telecommunication customer remains unchanged at 3.4KHz but will be limited by a digital filter: Cutoff frequency fC=3.4KHz, required damping DdB=AdB to be reached at fD=4KHz, sampling frequency fs= 500KHz. The analog anti-aliasing filters bandwidth is set to fB=16KHz. (It has to be > 3.4KHz but should not attenuate this frequency). What is the required order of the analog anti-aliasing filter?
Bandwidth of the analog anti-aliasing lowpass:
fB = .........................................................
Attenuation frequency of the lowpass:
fA = .........................................................
Required order of the anti-aliasing lowpass:
N = .........................................................
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3.2
Considerations for Digital Anti-Alias Filtering

x 3 0 1 2 4 t
In the digital domain we are interested in relative frequencies F = f/fs =fT rather than the absolute frequency f or the sampling frequency fs=1/T. According to Shannon and Nyquist the relative frequency range is F=0..., because F> is subject to aliasing. Figure 3.2.1 illustrates with F= that we need 1/F clock cycles and (1+1/F) taps to sample one time period of a wave with frequency F and consequently - wavelength 1/F.
Fig. 3.2.1: sampled waveform
A digital lowpass with pass-band FB=fB/fs has to suppress frequencies F > FB. It is a rule of thumb that the minimum length of a lowpasses impulse response is 1/FB or larger. Depending on selectivity (i.e. FA/FB) stop-band attenuation and pass-band-ripple the required filter length may be 5...10*1/FB. Frequency domain: fs0 = 10fs2 = 50 fB.
lH(jf)l / dB
0 0 fB f s2 fs0 f
Fig. 3.2.2: Top: Frequency situation: The same real world bandwidth fB = fs2/5 = fs0/50. Matlab screen copy, top: FIR lowpass impulse response with a length of 3 wavelengths of fB, sampled top: with fs2=5fB (15 taps) and bottom with fs0=50fB.(151 taps).
Fig. 3.2.2 demonstrates the problem of digital oversampling and anti-alias filtering. It shows two FIR lowpasses, both with cut-off frequency fB and an impulse response length of 3/fB in the time-domain, operated at sampling rates fs2 and fs0=10fs2.
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The upper impulse response is designed for a sampling rate of fs2=5fB FB0=0.2. A FIR impulse response comprising 3 wave-lengths requires 3/FB0+1=16 taps. The lower impulse response is designed for a sampling rate of fs0=10fs2=50fB FB=0.02. A FIR impulse response comprising 3 wave-lengths requires 3/FB+1=151 taps. For every output sample the filter has to perform one multiplication and one addition, termed a MAC (multiply and accumulate) operation. With increasing sampling clock speed the number of MAC operations increases also. Consequently, the number of required MAC operations per second, RMAPS, increases quadratic with sampling frequency fs. Consequently, the number of required multipliers increases quadratic with fs also: Nmult = RMAPS/PMAPS, with PMAPS being the possible number of MAC operations per second and multiplier.
ADCs typically require some more power than other ADCs. This is due to the high clock frequency and required antialiasing filters in the digital domain. On the other hand, power consumption and hardware effort must be seen in face of the fact that ADCs need no or significantly relaxed anti-aliasing filters in the analog domain.
Fig. 3.2.2 illustrates the problem for a required decimation factor of 10, but we may need some 100. This is expensive from hardware costs and power consumption point of views. One solution may be to decimate the sampling rate step by step with lowpasses having acceptable relative cut-off frequencies FB. However, taking advantage of sinc filter zeros is cheaper.
3.3 Aliasing at Digital Re-Sampling

(a)
10
(b)
t t
Fig. 3.3.1: (a) Data rate 1/N decimation symbol: N, (b) factor 10 decimation, time domain.
In Fig. 3.3.1 we decimated the data rate by a factor 10 from fs0 to fs2 without prior lowpass filtering. The consequence is aliasing of frequencies > fs2 to |fs0-kfs2| with k being an integral number chosen such, that the result is fs2. Applying the 16-tap lowpass of Fig. 3.2.2 obtains the transfer characteristics illustrated in Fig. 3.3.2. All noise in the pass-bands around F=1x, 2x, 3x, ... aliases to F=x.
Fig. 3.3.2: Lowpass characteristics for F=0-11. Due to symmetry it is enough to plot F=0-.
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3.4
Application of Sinc Filters for Decimation

fs0 sinc filter fs0 10 fs2 lowpass fs2
Fig. 3.4.1: Decimation with sinc filter. Their name is due to their frequency domain shape.
A digital signal processing (DSP) system reduces the data rate by a factor R=10 from fs0=Rfs2 to fs2. Opposite to the situation in the previous subsection this decimation happens after application of a sinc filter as illustrated in Fig. 3.4.1. The sinc filter is particularly easy to build and is designed such, that its zeros fall onto fz,n=nfs2 with n =1,2,3,4... with exception of mR. This is illustrated in the top of Fig. 3.4.2, left with linear and right on logarithmic ordinate. After removing (R-1) out of R data samples the lowpass with characteristics shown in Fig. 3.3.2 is applied. In Fig. 3.4.2 this lowpass is plotted in the second row. The lowpass operated at fs2 outputs a samples with fs2 corresponding to Fs2=1 and a baseband spectrum FB=0...0.5 in Fig. 3.4.2 below. However, all higher frequencies alias into this range. To avoid this, the sinc filter employed as anti-alias filter at the high sampling frequency fs0 suppresses with its zeros the pass-bands of the lowpass around F0=1,2,3,4,... The combination between sinc filter and lowpass is illustrated at the bottom of Fig. 3.4.2. The sinc filter suppresses the periodic maxima of the lowpass for nfs2 with exception of n=mR. Fig. 3.4.2 shows that less than 20dB suppression of aliasing frequencies as can be seen from the logarithmic plot in the right hand side of the figure. The three main possibilities to improve the situation are using a higher order sinc filter, a narrower or more suitable lowpass.
Fig. 3.4.2: Top-down: |Hsinc|, |Hlowpass|, |HsincHlowpass|, left: linear ordinate, right: in dB.
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3.5
3.5.1
(a)
Optimizing Sinc Filters for Decimation

Down-sampling after Decimation
sincL filter f s0 sinc filter 1 fs0 sinc filter 2 sinc filter L f s0 10 f s2 lowpass f s2
(b)
Fig. (a): Decimation with sincL filter 3.5.1 (b): sincL-lowpass optimization. left: Fg0=f/fs1=0.2, right: Fg0=0.125. Top-down: L = 1,2,3,4 for dB(|Hsinc|L|Hlp(Fg0)| ). Black: HsincL, blue: Hlp, red: HsincLHlp
In this subsection we use L sinc filters in series as illustrated in Fig. 3.5.1(a) yielding a sincL filter characteristics in the frequency domain. As a rule of thumb it is recommended to use L=M+1 sinc filters after a modulator of order M. Fig 3.5.1(b) shows 8 subplots with characteristics H(sincL) in black, the lowpass characteristics H(lowpass) in blue and the product H(sincL) H(lowpass) in red for f=0...fs0 F0=0...1.
Variation of Fg=fg/fs0: The column on the left hand side in Fig. 3.5.2 uses the known lowpass with Fg=0.2. The column on the right hand side uses a lowpass with Fg=0.125. Variation of L: The rows in the figure below use from top to down L=1,2,3 and 4.
The goal of optimization is to have the desired baseband without excessive attenuation in the baseband F=0...FB and sufficient attenuation in the range F=(1-2FB)...1. When using Matlabs filter design & analysis (FDA) toolbox [4] a particular lowpass that compensates the passband droop at Fg can be designed using the command d=fdesign.decimator('specification').
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3.5.2
(a) X
f s1
Cascaded-Integrator-Comb (CIC) Filter

L integrators f s0 f s0 f s0 Dsr sincL filter f s2 L differentiators
Y z-1
fs2 = f s0 / Dsr
z-1
fs2 fs2
z-1
z-1
sincL filter
(b) X
f s1
L-1 integrators
1 accumulate & daump f s0 f s2 Dsr
L-1 differentiators
Y z-1
fs2 = fs0 / Dsr
f s0
f s0
z-1
fs2 fs2
z-1
z-1
Fig. 3.5.2: (a) Down-sampling done within the middle of integrators and differentiators. (b) Practically we incorporate one accumulate & dump filter.
Eugene B. Hogenauer [22] demonstrated a very efficient way to implement a sincL filter (which is made up of a L cascaded sinc filters) for the particular case that the decimation filter length equals the down-sampling ratio Dsr. The sincL filter in Fig. 3.5.1(a) is described by the formula. The formula describing the sincL filter
1 z Dsr H sin c L ( z ) = 1 z 1 1 Dsr
L
can be re-written as
1 H sin c L ( z ) = 1 z Dsr 1 z 1
1 Dsr
The realization of (1-z-Dsr) would require Dsr delay elements before down-sampling according to Fig. 3.5.1(a), but only 1 delay element after down-sampling by Dsr, as illustrated by Fig. 3.5.2(a), because the sampling interval after down-sampling is accordingly longer. Practically we save hardware by realizing the last integrator with one additional multiplexer as accumulate & dump filter (see next chapter) and save a differentiator. Problem: The integrators will overflow. This doesnt matter and can be accepted when: We use an arithmetic (e.g. as 2-complement) where smallest number 1 = largest number largest number + 1 = smallest number. The registers bit-width within the total CIC filter is W L log2(Dsr) + WX with WX being the bit-width of filter input X.
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3.6
(a)
Using Sinc Filters for Interpolation

(b)
t 10 increase fs and fill in zeros t
after sinc1 t
(c)
f s2 lowpass f s2 10 f s0 sinc filter 1 f s0 sinc filter 2
sincL filter sinc filter L fs0
Fig. 3.6.1: (a) low sampling rate fs0 is (b) up-sampled by including zero-taps and (c) subsequent interpolation using with a sincL filter or a lowpass.
To increase the sampling frequency from fs0 to fs2=Rfs0 we confine the bandwidth at fs0 with a lowpass, include (R-1) zero-samples between the existing pulses and then apply sinc filters for interpolation at the high sampling frequency fs2. The transfer characteristics obtained and the subsequent considerations are exactly the same as for the decimation case discussed above. Of course, we could use a 'simple' lowpass after inclusion of the (R-1) zero-pulses. In this case the problems with MAC operations increasing quadratic with fs2 is exactly the same as discussed for decimation in subsection 3.2.
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3.7
3.7.1
(a)
xin
Sinc Filter Construction

Sinc Filter as Particular FIR filter
(b)
Z-1 Z-1 Z-1 xin 0 Z-1 1 Z-1 2 Z-1 K
a0
a1
a2
aK
yout
a
yout
(c)
Fig. 3.7.1: (a) General FIR filter, (b) sinc filter, (c) sinc filter impulse response
Fig. 3.7(a) show a general finite impulse response (FIR) filter. If all coefficients are identical, i.e. a1=a2=...=aK =: a, we can factor out a to get the topology shown in Fig. part (b). If a=1/K this is a moving averager and a DC amplification of 1. Typically we do not perform the multiplication with 1/K and say instead that the filter has a DC amplification of K. The impulse response is rectangular and consequently the transfer function as its Fourier transformed is sinc shaped giving this filter its name. It is also called moving averager (typically with a=1/K) or decimation filter due to its application. The particular suitability for decimation are its useful zeros and the realization without multiplier. The factor a at the output is practically realized by simply removing some trailing bits by truncation or rounding. General FIR filter formula for K+1 impulse-response taps corresponding to filter order K:
H general ( z ) = a0 + a1 z 1 + a 2 z 2 + ... + a K z K = ai z i
i =0 K
(3.1)
In case of a sinc filter this reduces to

H sin c ( z ) = a z i
i =0 K
(3.2)
which can be shown to be identical to

H sin c ( z ) = aK 1 z ( K +1) 1 z 1
(3.3)
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3.7.2
Sinc Filter Composed of Combined Comb-Filter

xin 1 Z-1 Z-1 2 Z-1 K yout Z-1
Fig. 3.7.2: K-th order sinc filter constructed from 2 nested comb filters.
Equation (3.3) describes two comb filters, namely a forward comb with (1-z-(K+1)) and a backward comb with (1-z-1), which is the digital integrator. The digital integrator is unstable because it hat a pole at zp=1 on the unit circle. This was unstable if there wasnt a zero zn=1, too, which compensates for zp=1. To make these pole-zero compensation work bit-accurate data processing is absolutely mandatory within the nested loops. Example: If there is a frequency where we accept an error of a half bit per clock cycle due to rounding or truncation, then this error accumulates to 5 million bits per second at a clock frequency of 10MHz.
3.7.3
Sinc Filter for CIC Topology

(a)
X Z-1 fs1 f s0 1 Z-1 2 Z-1 f s0 fs0 Z-1 fs2 = f s0/K X K fs0 f s0 Z-1 f s2 Z-1 fs2 Y fs2 K K Y fs2
Fig. 3.7.3: sinc filter saving hardware: (a) down-sampling after the complete sinc filter, (b) down-sampling between integrator and differentiator.
(b)
Fig. 3.7.3 demonstrates how to build (a) sinc filter with down-sampling following it and (b) with down-sampling incorporated between integrator and differentiator. The requirements for CIC filter constructed on this basis are given in chapter 3.5.2 above.
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3.7.4
(a)
xin reset
Accumulate-and-Dump (ACD) Sinc Filter Before Decimation

yout
(b)
t yout
(b)
xin r
Z-1 t
Fig. 3.7.4: (a), (b) integrator with reset, (c) time domain sinc filter with decimation
In the optimal case where the down-sampling frequency ratio R=fs0/fs2 equals the number of taps in the sinc filters impulse response, then the sum of the last R samples at fs0 is one sample of the lower frequency fs2. Therefore, the last sinc filter in the sincL chain may be an accumulate-and-dump filter. As illustrated in Fig. 3.7.3(a) and (b): Clear the integrator and sums (accumulates) the last R samples. While the sum is passed (dumped) as sample at fs2 the integrator is cleared again. While for the sinc filters explained previously any R-th output sample can be used for sub-sampling, it is important for the ACD-type to dump exactly the last value of the integrator before reset. For synchronous digital design the reset must be realized synchronous without loosing a data sample at the high frequency fs0. Advantages of this of sinc-filter type are the single required delay element, self-adaptation to the frequency ratio R and stability due to the repeated clearance of the integrator. Previous sinc filters should have removed aliasing frequencies prior to decimation. Unfortunately, only the last sinc filter in the sincL-chain can be realized as ACD-sinc filter.
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M. Schubert
3.7.5
Repeated Sampling of the Same Value for Sinc Interpolation

t
(a) Samples a low frequency fs2 (b) Up-sampled by a factor R=10 to fs1, new samples are zero. (c) After the first R-taps sinc filter. Fig. 3.7.5: Up-sampling using one sinc filter:
Fig. 3.7.5 illustrates the up-sampling situation with a sinc filter having R=fs1/fs2 taps impulse response: (a) The data stream at the low frequency fs1. (b) The data stream at the r times higher frequency fs1. Between the samples overtaken from fs2 were (R-1) zero-samples included. (c) After the first sinc filter with R taps impulse response and a DC amplification of R (corresponding to a=1 in Fig. 3.7.1(b)). The same result can be obtained without sinc filter by simply re-sampling the last sample at fs2 with higher frequency fs1. This is nearly no effort, always stable and with self-adapting filter-length to R. Unfortunately, this is possible only for the first sinc filter in the sincL chain. A second and third sinc filter in series with DC amplification of 1 would obtain linear and quadratic interpolation, respectively.
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M. Schubert
4 Tasks on Signal Processing Theory

4.1
4.1.1
Some Basic Skills Using Matlab

Computing Roots
8 1 = 18
z-Plane j j Im(z)
Fig. 4.1.1: Solutions of 1
Re(z) -1 -j 1
Make yourself aware: The solutions of 1
1 = 18
are e
j 2
n 8
for n=0, 1, 2, 3, 4, ...
Check: Is the result of 8 1 non-ambiguous?

..........................................................................
j 2 n 8 j 2 nm 8
Check: Given is zn / 8 = e
. Is the result of ( z n / 8 ) = e
non-ambiguous for any n, m?
..........................................................................
Consequence: Use integer exponents rather than fractional numbers. Line 1. Good
1 2 3 4 5 j = sqrt(-1); F0 = 0 : 1/8 : 7/8; F1 = 0 : 1/64 : 7/64; z0 = exp(j*2*pi*F0); z1 = exp(j*2*pi*F1);
2. Good
j = sqrt(-1); F1 = 0 : 1/64 : 7/64; z1 = exp(j*2*pi*F1); z0 = z1.^8;
3. Bad
j = sqrt(-1); F0 = 0 : 1/8 : 7/8; z0 = exp(j*2*pi*F0); z1 = z0.^8;
In the examples above we want a z0 related to sampling frequency fs1 and a z1 related to sampling frequency fs0=8fs1. Consequently the relative frequencies are F0=f/fs1 and F1=f/fs0. The related phasors are z0=exp(j2F0) and z1=exp(j2F1). As F0=8F1 we have z0=(z1)8 and z1=(z0)1/8. Check with Matlab! (Use figure(1); plot(z0); figure(2); plot(z1)). Why is the bad examples result different from the good ones?
..........................................................................
4.1.2 4.1.3
Computing H(s) Computing H(z)
Matlab> f=10:1:10000; s=j*2*pi*f; Hs = a0+a1*s+...+ak*s.^k;
Matlab> F=0:1e-4:0.5; z=exp(j*2*pi*F); Hz = a0+a1*z+...+ak*z.^k;
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M. Schubert
4.2
4.2.1
(a)
The Significance of Zeros and Poles in Transfer Functions

Significance of Zeros and Poles in the s-Plane
(b) R L Ui L C Uo R Uo C Ui L2 C2 Uo Ii L C Uo (c) L1 C1 (d)
Ui
Fig. 4.2.1: Time-continuous circuits with zeros and poles on the j axis.
Compute poles and zeros for the 4 circuits in the Fig. above. Simulate the circuit and demonstrate with Spice or Matlab: A zero on the j axis is a notch in the zero frequency. A pole on the j axis is an oscillator in the pole frequency. PS: The author had problems with LTspice, most probably due to round-off errors.
4.2.2
(a)
xin
Significance of Zeros and Poles in the z-Plane

(b)
1 Z-1 Z-1 2 Z-1 K yout Uin
fs1 9-level ADC sincL filter
fs2 comb filter R2R DAC

Uout
Fig. 4.2.2: Time-discrete circuits with zeros and poles on the unit circle.
Show analytically: The comb filter in Fig. 4.2.2(a) is described by H(z) = 1 + az-K and can be modeled as H(z) = 1 + z-K | H(z) | = cos(KF) for a= 1 H(z) = 1 - z-K | H(z) | = sin(KF) for a= -1 Show that this two comb filters have both K zeros on the unit circle. These zeros describe the notches of the filters and are equal to the zeros of the sin and cos functions modeling H(z). Confirm the results with Matlab simulations computing H(z) = H(z) = 1 + az-K for a=1.
Optional: Practical test according to Fig. 4.2.2(b): Build a comb filter with VHDL, download it into the DE2 board and confirm the calculated bode diagram by measurements with the Bode100 network analyzer. To increase the number of levels delivered by the 9-level ADC appropriate sincL filter should be used.
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M. Schubert
4.3
Sinc-Filter for Decimation
Explain chapter 3.1 3.3, probably begin of 3.4. Support with Matlab simulations.
4.4
Optimization of the Demodulator with sincL & Lowpass
Explain chapter end of 3.4 3.5. Support with Matlab simulations.
4.5
Sinc-Filter for Up-Sampling
Chapter 3.7.4: Illustrate impulse responses for sincL filters, L=1,2,3,4. Show how interpolation becomes smoother for higher L.
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M. Schubert
5 Module Layer: Laboratory VHDL Project Tasks

5.1
5.1.1
(a) Uadc,in ADC
Module Management
Project Overview
Dadc,out
cAdcOutWidth
Ddac,in
cDacInWidth
DAC
Udac,out
(b) Modulator
U
da2_board
dsadc Demodulator
D dsdemod dsfb fs0 > fs2 D
dsdac Interpolator dsinterp Modulator

dsmod DAC D A
dsmodad
Demodulator
analog lowpass U
A/D D/A
fs2 Digital (DE2 board)
fs1 > fs2 Analog (DA2 board)
Analog (DA2 board)
(c)
cInWidth cDsr cCtrlWidth cOutWidth
(d)
cInWidth cUsr cCtrlWidth cOutWidth
DsAdcIn
cInWidth
DsAdcOut
cOutWidth cInWidth
DsDacIn
DsDacOut
cOutWidth
ctrl
cCtrlWidth
dsadc
ctrl
cCtrlWidth
dsdac
enable1 clock reset
enable0 clock reset
Fig. 5.1.1: (a) Analog-to-Digital-to-Analog Conversion system, (b), resolved into subsystems, (c) Symbol of digital parts of the ADC and (d) of the DAC.
Fig. 5.1.1 gives a finer resolution of the digital components used to resolve the mixed analog/digital A/D and D/A conversion components. For ModelSim simulations behavioral VHDL models are provided for the analog parts, which are physically located on the DA2 board [7].
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M. Schubert
5.1.2
Subproject File Structure

ModelSim tb_de2_counter de2_counter tb_counter counter de2_counter.sof VHDL Quartus II 8.1 de2_counter.qpf de2_counter.qsf
FPGA
Fig. 5.1.2: de2_counter fits into the DE2 board and instantiates module counter.
The testbenches tb_de2_counter and tb_counter are located in the ModelSim directory while the Quartus-project file de2_counter.qpf and respective specification file de2_counter.qsf define the project from the Altera side. Files named de2_<name> fit into the DE2 board. After successful compilation the de2_<name>.sof file can be downloaded into the FPGA using the Quartus II Programmer.
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M. Schubert
5.1.3
Project Directory Structure

counter Matlab filter oscillator f_counter.m + tb_counter.m
optimizations
compile_adac.do ModelSim Testbenches adac_bin ADAC
1.counter 1.de2_counter 2.de2_engen
tb_counter.vhd tb_de2_counter.vhd tb_de2_engen.vhd
behavioral
da2_dsdemod.vhd
de2_counter QuartusII81 de2_engen de2_dsmodad
de2_counter.qpf de2_counter.qpf de2_dsmodad.qpf
+ + +
de2_counter.qsf de2_counter.qsf de2_dsmodad.qsf
counter.vhd entitys engen.vhd
+ +
de2_counter.vhd de2_engen.vhd
rtl_counter.vhd VHDL architectures rtl_engen.vhd
+ +
rtl_de2_counter.vhd rtl_de2_engen.vhd
con_counter.vhd + configurations con_engen.vhd +
con_de2_counter.vhd con_de2_engen.vhd
Fig. 5.1.3: Used file system modeling the addax project.
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M. Schubert
5.1.4
Assignment of Keys and Switches of the DE2 Board
Table 5.1.4: Assignment of switches on the DE2 board switch Function Comments
Hint: key(x)='0' when pressed key(3) key(2) key(1) key(0) key(0:3) are 4 blue, push buttons
global enable global reset

sw(x)='1' when moved toward board sw(0:17) are 18 sliding switches controls quantization in qdem No.(output_levels)=2^sw(17:16) + 1 Simul. Quantiz.-error in Flash ADC sw(15)='0'/'1' : quantiz. error OFF/ON Simul. DAC-nonlinearity in qdem sw(14)='0'/'1' : nonlin-error is OFF/ON controls Dyn. Elem. Mat. in qdem sw(13)='0'/'1' : DEM is OFF/ON inverts Delta-Sigma-Feedback: sw(12)='0' : dsfb<=NOT dsfb switches oscillator to DAC input sw(12)='1': OscillatorOut = DacIn
sw(17:16) sw(15) sw(14) sw(13) sw(12) sw(11) sw(10:3) sw(2:0)
Controls oscillator frequency sets frequency of fs2, flag en2
f(en1) = 10^sw(2:0)
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M. Schubert
5.2
5.2.1
9-Level D/A Converter

Flash-DAC Theory
(a) U0 U1
bin08
(b) G0 G1 G2 G3 G4 G5 G6 G7 DAC2out
(c) Gsum Usrc DAC2out
bits9
U2 U3
8
ctrl
6
dacd
enable clock reset
U4 U5 U6 U7
Figure 5.2.1: (a) 9-level DAC digital part, (b) analog part (c) equivalent analog model
The analog part of the 9-level flash DAC is realized as illustrated in Fig. 5.2.1(b). Fig. part (c) shows its equivalent circuit that can be modeled as
1 Z out = Gsum =
G j
j =0
and
U src =
GsumU j .
j =0
Gj
5.2.2
Binary to Thermometric Conversion & DEM

DE2 Board DA2 Board
demi eff
0 8 1 8
dsmod
dacd (DAC digital part)

thermometric dem bin2therm
DAC2
bits9 q
8
DsOut
bin08
4
qdem 2, 3, 5, 9 level ctrl(5:1)
(9 levels) 1K
Udac2
d e
clock enable reset ctrl(5:0)

6
ck r reset
Usrc2
anal. lowpass
ctrl(0)
Figure 5.2.2: (a) 9-level DAC digital part, (b) analog part (c) equivalent analog model
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M. Schubert
5.3
5.3.1
(a)
Digital-to-Analog Converter
1st Order -D/A Converter
(b)
dsmod
DsIn
cInWidth
cInWidth
cCtrlWidth
cOutWidth cOutWidth
DsOut
cOutWidth
cInWidth
DsIn
ctrl cCtrlWidth
DsOut
quantizer b
cInWidth cOutWidth
enable clock
dsmod
reset
Fig. 5.3.1: dsmod: (a) 1st order modulator topology, (b) symbol.
Realize the quantizer with 9, 5, 3, 2 output levels depending on the ctrl signal. Use ieee package std_logic_unsigned, so that the signal range has positive numbers only.
5.3.2
DsIn
2nd Order -D/A Converter

DsOut DAC quantizer b1 b2 analog lowpass Uanalog
Fig. 5.3.2: dsmod: 2nd order modulator topology with DAC and analog lowpass.
The symbol of modulator is the same as shown in Fig. 5.3.1(b). Use b2=1 and b1=2. In this case average input and output amplitudes will be equal and the first (input) integrator will performs double amplitude (x b1). Realize the quantizer with 9, 5, 3, 2 output levels depending on the ctrl signal. Use ieee package std_logic_unsigned, so that the signal range has positive numbers only. Illustrate, that the output of a second order modulator will perform jumps over two levels. This is impossible for a single-bit output and the modulator is said to be overloaded. Opposite to higher order modulators the second order modulator remains stable in case of overloading.
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M. Schubert
5.3.3
DsIn
3rd Order -D/A Converter

DsOut DAC quantizer b1 b2 b3 analog lowpass Uanalog
Fig. 5.3.3: dsmod: (a) 1st order modulator topology, (b) symbol.
The symbol of modulator is the same as shown in Fig. 5.3.1(b). Use b3=1 and b2=b1=3. In this case average input and output amplitudes will be equal and the first two integrators will performs three times the input amplitude (x b2). Realize the quantizer with 9, 5, 3, 2 output levels depending on the ctrl signal. Use ieee package std_logic_unsigned, so that the signal range has positive numbers only. Illustrate, that the output of a second order modulator will perform jumps over several levels. If this is not impossible due to a lack of output levels the modulator is said to be overloaded and becomes instable.
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M. Schubert
5.4
5.4.1
-A/D Converter
1st Order ADC Using a Capacitor as Integrator
DA2 Board
dsmodad (
from_flash eff d
8
DE2 Board
-mod. ADCdigital part)
bin08 qdem 2, 3, 5, 9 level ctrl(5:1)
Uadc,in
1K
CP_in_P
Flash ADC
(9 levels)
C02 C04 ... C16
q
8
e ck r reset
digit. lowpass
Dadc,out
cAdcOutWidth
bits2bin
dsdemod
5 1 0
DAC3out
Integrator
DAC3
(9 levels) 1K ctrl(5:0)
6
ctrl(0)
C3
Usrc3
8
dsfb
=NOT(bits9) when sq(3)='0' ELSE bits9
Fig. 5.4.1-1: modulator using capacitor C3 as integrator.
Project: Code dsmodad and Assemble the Setup Listing 5.4.1: VHDL ENTITY of the digital part of the -ADC
-------------------------------------------------------------------------------- Module : dsmodad -- Designer : Martin Schubert -- Date last modified: 18.Oct.2010 -- Purpose : Delta-Sigma MODulator's Adc Digital part --- Constants : -- Input-Signals : reset : std_logic, asynchonous, doninant reset -clock : std_logic, clock signal -enable : std_logic, flipflops can toggle if enable='1' -from_flash: std_logic_vector, from Flash-ADC, therm. code -ctrl(5:0) : controls Quantization + Dyn.elem.matching -ctrl(5:4): quantiz. levels = 2^ctrl(5:4) + 1 -ctrl(3) : ='0'/'1': Quantizer-error OFF/ON -ctrl(2) : ='0'/'1': DAC-nonlinearity OFF/ON -ctrl(1) : ='0'/'1': DEM is OFF/ON -ctrl(0) : dsfb=NOT(bits9) WHEN ctrl(0)='0' -- Output-Signals: dsfb(7:0) : std_logic_vector, DS feedback, 9-level therm. -bin_08_out: Natural, 9-level binary coded ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY dsmodad IS PORT(reset,clock,enable:IN std_logic; ctrl :IN std_logic_vector(5 DOWNTO 0); from_flash:IN std_logic_vector(7 DOWNTO 0); dsfb :BUFFER std_logic_vector(7 DOWNTO 0); bin08_out :BUFFER std_logic_vector(3 DOWNTO 0) ); END ENTITY dsmodad;
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M. Schubert
Behavioral Model of the RC-Integrator on the DA2-Board

(a) Fig. 5.4.1-2: modulator using capacitor C3 as integrator. (a) Circuit (b) behavioral model
Rpoti19
(b)
CP_in_P U_C3 U_CPinP
Uadc,in DAC3
(9 levels) Udac3out
1K
Rsrc Usrc
Rdac3out
1K
C3
C3
UC3
The two sources Uadc,in and Udac3out with output impedances Rpoti19 and Rdac3out, respectively, are summarized to form a common resistive source with output Voltage Usrc and output resistance Rsrc. We obtain
U src = G poti19U adc ,in + Gdac 3outU dac 3out G poti19 + Gdac 3out = G poti19U adc ,in + Gdac 3outU dac 3out GCPinP
with Gx=1/Rx and GCPinP=Gpoti19+Gdac3out=1/Rsrc. The current charging C3 in Fig. part (b) is the sources output current through Rsrc:
dU C 3 U src U C 3 = I C 3 = C3 dt Rsrc
Using Rsrc=1/GCPinP and dUC3/dt=(UC3-UC3,last)/TimeStep and a=RsrcC3/TimeStep obtains the actual value of UC3 as U C3 = U src + aU C 3,last 1+ a
Operating the Hard- and Software:
We need sw(12)=ctrl(0)='0' causing the digital word assigned to dac3dout to be inverted. This is because we need a feedback voltage which is negative with respect to UB=VDD/2. The modulator requires a feedback loop with high loop gain. It is best to use one comparator only, i.e. sw(17:16)=ctrl(5:4)=ctrlqd(4:3)="00", or adjust a small quantization step of the flash-ADC, e.g. =delta=VDD/64. Connect the capacitors voltage to the input of the flash-ADC. On the DA2 board you have to set the respective jumper; in the testbench you need to activate the code line that connects UCPinP to UC3:
--U_CPinP <= U_int1; -- Use inverting OpAmp as integrator U_CPinP <= U_C3; -- Use RC-lowpass as integrator
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M. Schubert
5.4.2
ADC Using PSK2- or DS2-Boards OpAmp Integrators

DA2-Board
dsmodad (
from_flash
CP_in_P
DS2-Board
DE2 Board
-mod. ADC digital part)
thermometric qdem 2, 3, 5, 9 level ctrl(5:1)
bits9 bits2bin
bin08
Flash ADC
(9 levels)
C02 C04 ... C16
eff d
8
q
8
e ck r reset
digit. lowpass
Dadc,out
cAdcOutWidth
dsdemod
5 1 0
DAC3out
DAC3
(9 levels) 1K ctrl(5:0)
6
ctrl(0)
k feedback network
Usrc3
8
dsfb
=NOT(bits9) when sq(3)='0' ELSE bits9
Fig. 5.4.2-1: modulator using PSK2-Board to realize a 1st and 2nd order integrator.
Project: Code dsmodad and Assemble the Setup Operating the Hard- and Software: Same component dsmodad as used for the capacitor C2 as integrator. We need sw(12)=ctrl(0)='1' causing the digital word assigned to dac3dout not to be inverted. This is because we already use the OpAmp OA1 inverting with respect to UB=VDD/2. The modulator requires a feedback loop with high loop gain which is delivered by the Integrators for sufficiently low frequencies. Check for different quantization steps delta, Adjust a reasonable i.e. sw(17:16)=ctrl(5:4=ctrlqd(4:3)= "00","01","10","11". quantization step of the flash-ADC, e.g. =delta=VDD/8. Hardware: Connect the integrators output voltage to the input of the flash-ADC. The DA2-board will be used to bridge Uerr1 on the PSK2-board. Simulation with ModelSim: The PSK2 board is integrated in the DA2 board model. In the component DA2_dsmodad you have to activate the code line that connects UCPinP to Uint1:
U_CPinP <= U_int1; -- Use inverting OpAmp as integrator --U_CPinP <= U_C3; -- Use RC-lowpass as integrator
To simulate a 1st order modulator you have to connect the input of the output-stage integrator with index 1, Uinput1, directly to the input voltage:
-- Uinput1 <= U_int2; -- 2nd order integrator Uinput1 <= Uadcin; -- 1st order integrator
To simulate a 2nd order modulator you have to connect the input of the output-stage integrator, Uinput1, directly to the output of the first stage with index 2:
Uinput1 <= U_int2; -- 2nd order integrator -- Uinput1 <= Uadcin; -- 1st order integrator
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M. Schubert
0V
OA2 U'in
(1st order)
0V
OA1
R2 U'in
(2nd order)
C2 OUT2 Rb2 -1
(c) R1 Rb1
C1
DA2-board Flash-ADC
OUT1
DA2-board Udac3out
Fig. 5.4.2-2: modulator part on the PSK2-Board.
Illustrate, that a second order modulator needs to jump over more than one of the flashADC to realize its strong high-frequency amplification by noise-shaping. If it cannot perform at lest 2-jumps the modulator is said to be overloaded. While an overloaded 2nd order modulator remains stable, 3rd and higher order modulators become unstable producing long series of 1s and 0s.
5.5
Lowpass for Demodulation: dsdemod

cInWidth cDsr cOutWidth
Fig. 5.5: dsdemod: lowpass system for demodulation (a) symbol ,
DsDemIn
cInWidth
DsDemOut
cOutWidth
dsdemod
enable0 clock reset
(b) schematics
f s1
dsdemod SincDn
fs1 fs2 cMidWidth f s2
DsDemIn
sincS1 cInWidth
DsDemOut
digital lowpass cOutWidth
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M. Schubert
5.6
Fig. 5.6:
Sinc-based Decimator for Down-Sampling: SincDn

cInWidth cTaps cOutWidth
SincDn: lowpass for decimation (a) symbol ,
SincDnIn
cIn-Width
SincDnOut
cOutWidth
enable1 clock
SincDn
reset
SincDn (sincS1 for down-sampling (decimation))
(b) schematics
fs1 SincDnIn sinc cInWidth

1 cWidth1 2
fs1 sinc
cWidth2
f s1 sinc
S1-1
fs1
fs2 SincDnOut cOutWidth
sinc
acc+dump S1
5.7
Fig. 5.7:
Sinc-based Interpolator for Up-Sampling: SincUp

cInWidth cTaps cOutWidth
SincUp: lowpass for interpolation (c) symbol ,
SincDnIn
cIn-Width
SincDnOut
cOutWidth
enable0 clock
SincUp
reset
SincUp (sincS0 for up-sampling (interpolation))
(d) schematics
f s2 SincUpIn latch cInWidth

1 cinWidth
fs0
f s0
f s0 SincUpOut
sinc
cWidth2 2
sinc
cWidth3 3
sinc cOutWidth
S0
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M. Schubert
5.8
5.8.1
(a)
xin
Sinc Filter
Sinc Filter by Simple Summation: SincSum
rtl_SincSum
Z-1 cInWidth 1 Z-1 2 Z-1 K=cTaps
(b)
cInWidth cInWidth cTaps cOutWidth cOutWidth
SincIn
SincOut
sinc
enable yout cOutWidth clock reset
+ rtl_SincSum
Fig. 5.8.1: SincSum: (a) sinc filter in comb topology. (b) Symbol of entity sinc, which has to be combined with architecture rtl_SincSum.
Computing the required bitwidth. The required bitwidth to represent an integral number 0 xin xmax is ld(xmax+1) with ld(x)= log2(x) being the logarithm dualis, that can be computed from ld(x)=logB(x)/logB(2) with any basis B. Typically we compute ld(x)=ln(x)/ln(2). As a fractional bit-vector width, e.g. 2.7 bits, is difficult to realize, the result has to be rounded up, which is done with the ceil(ing) function below. Try this equations for xin=0...7 and xin = 0...8:
For For
0 xin xmax -xmax xin xmax
we need a BitWidth = ceil(ld(xmax +1)) we need a BitWidth = ceil(ld(xmax +1)) + 1
bits, bits.
In this project we come with 4 bits out of the flash ADC. If we sum the last 100 samples we could theoretically get a maximum output number of 100*15=1500 requiring 11 bits. However, the 8-comparator Flash-ADC on the DA2 board delivers a number range of 0...8, so that 100 of those samples will be 800 and only 10 of the 11 output-bits will be used. Realizing a sinc3 filter in this project, 3 sinc filters have to be used in series. If the next sinc filter sums 100 samples with a number range 0...800 it delivers numbers in the range 0...80 000 requiring 17bits to be represented and the 3rd sinc filter in the queue will have a number range 0...8 000 000 requiring 23 bits. This doesnt make sense when we have an 8bit R2R DAC only to translate that in to an analog signal. Consequently, the output bit-length has to be rounded to a reasonable number of bits. See for chapter Rounding and Truncation in [13].
VHDL: Show a detailed schematics drawn by hand or with any graphics program to your supervisor before coding this component. Theory: (Ask your supervisor before spending too much time on theory!)
The FIR filter z-Domain representation of a is H ( z ) = a0 + a1 z 1 + ... + ak z k = ai z i .

i =1
Demonstrate that the sinc filter in Fig. 5.8.1(a) can be written as H ( z ) = z 1
1 z . 1 z 1
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M. Schubert
5.8.2
(a)
Sinc Filter in Comb Topology: SincComb

(b)
rtl_SincComb
cInWidth
cInWidth
cTaps
cOutWidth cOutWidth
SincIn
SincOut
xin
cInWidth
1 Z-1 Z-1
2 Z-1
yout
Z-1
sinc
enable clock reset
+ rtl_SincComb
Fig. 5.8.2: SincComb: (a) sinc filter in comb topology. (b) Symbol of entity sinc, which has to be combined with architecture rtl_SincComb. VHDL: Show a detailed schematics drawn by hand or with any graphics program to your supervisor before coding this component. Theory: (Ask your supervisor before spending too much time on theory!)
The FIR filter z-Domain representation of the sinc filter in Fig. 5.8.1(a) is H ( z ) = z 1
1 z K . 1 z 1
(i) Demonstrate that this formula leads to the filter shown in Fig. 5.8.2. sin c( KF ) with z=ej2F and F=fT=f/fs. (ii) Demonstrate that this formula leads to H ( F ) = K sin c( F )
Stability: Not that 1/(1-z-1) is an ideal integrator with a pole at zp=1 on the unit circle. Normally this was instable but it is stabilized by a zero zn=1 in the denominator. This pole-zero compensation works if and only if the feedback loop works bit-accurate! Do not round or omit bits within the loop!
What is the required bit-width for the state-vector element (K+1) within the feedback loop?
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M. Schubert
5.8.3
(a)
Accumulate-and-Dump Sinc Filter: SincAcd

fs1 (b) (d)
cInWidth cOutWidth cOutWidth
cInWidth
SincIn
(d) fs2
t xin Z-1 yout
enable1 enable2 clock
SincOut
SincAcd
reset
Fig. 5.8.3: SincAcd: (a) sinc filter in accumulate & dump topology, (b) symbol of required integrator, (c) integrator circuit, (d) symbol of component SincAcd.
The sinc filter forming the interface from the higher clock rate fs0 to the lower clock rate fs1 can perform down-sampling (=decimation) by summarizing R taps coming in with fs0 to a single tap going out with fs1, when R=fs0/fs1. And this is just the optimal situation. In the example above we have R=4. In this case we can reset the integrator to zero, sum R incoming taps and give (or dump) the sum to the output just before the integrator is reset. The design has to respect the synchronous design rules (e.g. no asynchronous reset) while not loosing a tap of the incoming data stream. Note that we have no constant cTaps as for the other sinc filters, because the summation period length adjusts automatically by the ratio fs0/fs1.
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M. Schubert
5.8.4
(a)
Sinc Filter by Repeated Sampling the Same Value

fs2
t
(b)
fs0
(c)
t
(d)
t
Fig. 5.8.4: Up-sampling from fs2 to fs1 = R0fs2 (here R0=4) with sinc-filter interpolation, where the sinc filters have R0 taps each: (a) Signal at sampling rate fs2, (b) sampling rate increased to R0fs2 by introducing zeros, (c) situation after the first and (d) second sinc-filter.
To output a signal with a modulator the speed of the data stream has to be increased from the baseband-rate fs1 to a higher data rate fs2 = R2fs1 as illustrated in Fig. 5.8.4(a). This is normally done by filling the additional taps of the higher speed signal with zeros as shown in Fig. part (b). If the first sinc filter has an impulse response with R2 taps, the situation at the outputs of the first and second sinc filters are illustrated in Figs. 5.8.4 (c) and (d) respectively. The situation shown in Fig. part (c) can also be obtained by repeating sampling last sample of the incoming data rate, fs1, instead of filling new taps with zeros. In conclusion, we can replace the effort for the fist sinc filter by simply re-sampling the values of the low, incoming data rate, fs1, with the higher data rate, fs2. This corresponds to a DC-amplification of R2 this first sinc filter. To see the interpolating effect of the 2nd, 3rd, 4th ... sinc filters in Matlab it is recommended to give them in Matlab a DC amplification of 1. (The DC-amplification of a time-discrete filter is the sum of its impulse-response taps.)
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M. Schubert
5.9
Lowpass Filters
cInWidth
Fig. 5.9: Symbol filter
filter
FilterIn enable clock reset FilterOut
cOutWidth
Fig. 5.9 shows the symbol for the digital filter component. The many constants required are passed to the filter by package pk_filter.
5.9.1
Digital FIR Lowpass in 1st Canonic Direct Structure

FilterIn
cInWidth
FilterCanon1
a K-1
nsK
z-1
sK
s3
ns2
z-1
s2
ns1
z-1
s1
FilterOut
cOutWidth
Fig. 5.9.1: rtl_FilterCanon1: FIR filter in 1st canonical direct structure, K=cTaps.
It is a finite impulse response (FIR) filter because there is no feedback branch. The filter is canonic because the order of the polynomial equals the number of delay elements and it is a direct structure, because the impulse response can be directly adjusted with the coefficients. Show a schematics to your supervisor before coding the filter with Matlab or VHDL.
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M. Schubert
5.9.2
Digital FIR Lowpass in 2nd Canonic Direct Structure

rtl_FilterCanon2
a1 a2 a3
Filterin ns1
z-1
s1 ns2
z-1
s2
ns3
z-1
s3
nsK
z-1
FilterOut sK aK
Fig. 5.9.2: rtl_FilterCanon2: FIR filter in 2nd canonic direct structure, K=cTaps.
It is a finite impulse response (FIR) filter because there is no feedback branch. The filter is canonic because the order of the polynomial equals the number of delay elements and it is a direct structure, because the impulse response can be directly adjusted with the coefficients. Show a schematics to your supervisor before coding the filter with Matlab or VHDL.
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M. Schubert
5.10 Digital Quantization & Dynamic Element Matching (DEM)

5.10.1 Digital Quantization
qdem
Fig. 5.10.1-1: Symbol of the qdem module.
from_flash(7:0)
8
qdem_out(7:0) ctrlqd(4:0)
Listing 5.10.1: VHDL ENTITY qdem located within the digital part of the -ADC
-------------------------------------------------------------------------------- Module : qdem -- Designer : Martin Schubert -- Date last modified: 12.Oct.2010 -- Purpose : further Quantization and Dyn. Elem. Matching (DEM) --- Constants : cAdcFlashWidth: POSITIVE, BitWidth of Flsh ADC/ for DAC -cOutBinWidth: POSITIVE, BitWidth binary coded ouput -- Input-Signals : reset : std_logic, asynchonous, doninant reset -clock : std_logic, clock signal -enable : std_logic, flipflops can toggle if enable='1' -ctrlqd(4:0) : controls Quantization + Dyn.elem.matching -ctrlqd(4:3): quant.levels = 2^ctrl(4:3) + 1 -ctrlqd(2) : ='0'/'1': DAC-nonlinearity OFF/ON -ctrlqd(1) : ='0'/'1': Quantizer-error OFF/ON -ctrlqd(0) : ='0'/'1': DEM is OFF/ON -from_flash : std_logic_vector, from Flash-ADC, therm. code -- Output-Signals: qdem_out : std_logic_vector: input quantized and randomized ------------------------------------------------------------------------------LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY qdem IS PORT(reset,clock,enable:IN std_logic; ctrlqd :IN std_logic_vector(4 DOWNTO 0); from_flash:IN std_logic_vector(7 DOWNTO 0); qdem_out :BUFFER std_logic_vector(7 DOWNTO 0) ); END ENTITY qdem;
The functionalities of component qdem controlled by signal ctrlqd are:
1. ctrlqd(4:3): Quantization: Further quantization is performed as illustrated in Fig. 5.10.1-3 (a)-(d). The number of output levels is 9, 5, 3, 2 computed from 2ctrlqd(4:3)+1. Hint: It is recommended to prefer CASE to IF wherever possible. Here it is possible! 2. ctrlqd(2)='1': ADC non-linearity error by simulated non-linearity of the flash-ADC as illustrated in Fig. 5.10.1-3(e). As the ADC in the forward network of the loop, its nonlinearity is suppressed by the noise-transfer function (NTF). 3. ctrlqd(1)='1': DAC non-linearity error by simulated unbalanced grouping of the output resistors as illustrated in Fig. 5.10.1-3(f). As the DAC in the feedback network of the loop, its non-linearity is a disaster for the accuracy of the total loop. 4. ctrlqd(0)='1': Dynamic Element Matching compensates for non-linearity error of the DAC as detailed in the next subsection.
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M. Schubert
DAC#out 3.3 V 2.8875
#=2,3
VT(CPs) 3.09375 2.68125
2.47 2.26875 2.0625 1.85625 1.65 1.44375 1.2375 1.03125 0.825
Fig. 5.10.1-2: Possible distribution of thresholds (blue) for the Flash-ADC.
0.61875 0.4125 0.20625 0 0 1 2 3 4 5 6 7 8 L
(a) ctrlqd(4:3)="11": 9 level from_flash(7) from_flash(6) from_flash(5) from_flash(4) from_flash(3) from_flash(2) from_flash(1) from_flash(0) DAC#out
(b) ctrlqd(4:1)="1000": 5 level from_flash(7)
(c) ctrlqd(4:3)="01": 3 level
from_flash(5) from_flash(5) from_flash(3) from_flash(2) from_flash(1) DAC#out
(d) ctrlqd(4:3)="00": 2 level
(e) ctrlqd(4:1)="1010": ADC nonlin. from_flash(7)
(f) ctrlqd(4:1)="1001": DAC nonlin. from_flash(7)
from_flash(5) from_flash(4) DAC#out
DAC#out
from_flash(5)
from_flash(2) from_flash(1)
from_flash(3) from_flash(1)
Fig. 5.10.1-3: Expected output combinations as a function of the control signal ctrlqd(4:0).
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M. Schubert
5.10.2 Dynamic Element Matching (DEM)

(a) (b) (c) U0 U1 U2 U3 U4 U5 U6 U7 4 3 2 4 5 6 4 3 2 4 5 6 G0 G1 G2 G3 G4 G5 G6 G7
#=2,3 DAC#out,
Fig. 5.10.2: (a) No DEM, (b) barrel-shifter technique, (c) application points at DAC#, #=2,3.
The accuracy of the DAC within the loops feedback branch is essential for the accuracy of the total A/D conversion process. To overcome the inaccuracies of the resistors used we may employ dynamic element matching (DEM).
Fig. 5.10.2(a) illustrates a thermometric-code sequence with 4, 3, 2, 4, 5, 6 out of 8 bits are set to '1'. Fig. 5.10.2(b) illustrates the same sequence (4, 3, 2, 4, 5, 6 out of 8 bits are set to '1'), but the barrel of bits rotates around the index space of the output-bit vector. This is called barrelshifter technique. The advantage of DEM is that all bits are the same time-span ON an inaccuracies can be removed by averaging. The disadvantage of the barrel-shifter method is that it can generate new, lower-frequency periods. E.g. when a single ON-bit circles. Better was to use a random generator to select the indices of the '1'-bits.
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M. Schubert
5.11 Enable-Flags Generator

Fig. 5.11: Enable-Flags Generator: (a) (b)
(a)
clock count cPeriod
(b)
clock_50MHz
Single counter Enable-flags generator based on cascaded counters.
counter
enable reset maxflg
engen
enable envec(7:0) reset
The enable-flags generator module engen receives a 50MHz clock signal (clock_50MHz), a low-active reset (reset) and an enable signal. It delivers a vector of enable signals (envec(7:0)). Signal envec(i) delivers a 1-clock wide enable signal with frequency f(i)=10iHz. Signal envec(i) comes at the same time as envec(j) for all j<i.
VHDL: Use nested GENETRATE statements to place the 8 counters. Check for glitches on envec and their impact on triggering, e.g. by triggering enabled toggle-Flipflops.
Possible enhancements: (optional) Optimize counter: Try Johnson counter for divide-by-10 counter. Try binary-counter difference of inquiry "=" and ">=" for big and small cPeriod.
Optimize enable-flags generator engen: Use nested VHDL GENERATE statement to place sub-module counter. Try different AND gates for 8 cascaded counters 50MHz...1Hz: maximum fan-in and fanin = 2.
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M. Schubert
5.12 Harmonic Oscillator

(a) (b)
oscillator
cDataWidth
OscIn
cDataWidth
1 z-1
z z-1
OscOut
cDataWidth cDataWidth
OscIn g enable clock
cDataWidth
OscOut
oscillator
reset
Fosc
g
f2g cDataWidth
Fig. 5.12.1: oscillator: (a) topology,
(b) symbol.
First of all show which integrator, Fig. 5.12.2(a) or (b), has which z model, (c) or (d). Compute the oscillation frequency Fosc =f(g) and g=f(Fosc) with (=fosc/fs with fs sampling frequency) for the oscillator in Fig. 5.12.1. Draw a detailed schematics of the oscillator and check it with your supervisor. Model it with Matlab (care about amplitudes of the integrator outputs as a function of g, particularly g0.) After the Matlab model is understood realize the integrator with VHDL and download it into the FPGA.
(a) X Y0 W z-1
Y0 (d) (e) X Y (b) X 1 z-1 Y X z z-1 Y
(c)
z-1 W
Y1
Fig. 5.12.2: integrator: (a), (b) integrator types, (c), (d) respective integrator models in z, (e) integrator symbol common to (a)-(d)
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M. Schubert
Fig. 5.12.4: oscillator: s2: black tabs + green line, s1: blue line; (a) simulation with Fosc =0.1, (b) Fosc = 0.25, (c) Fosc = 0.45.
Considerations on required bit-widths of data. (a) If 0< Fosc <0.25 0<g<2 then |s1|<2 and |s2|<1. (b) If Fosc=0.25 g=2 then s1=-2, 0, 2, 0,-2 and s2=1 -1 -1 1 1 -1. (c) If 0.25< Fosc <0.5 2<g<4 then s1 and s2 become large and AM-effects.
We assume that the data range for g, s1, s2, OscIn, OscOut is 4...4. Assuming 3 binary places before the point we have a data range of 4...+4-, with being the LSB. Using 18 bits due to the 18x18 bit multiplier we have 15 fractions bits.
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M. Schubert
5.13 Other Stuff

5.13.1 Interface for DE2-70 Board
The laboratory is dome with the Altera / Terasic DE2 board [7], [8], [9]. Port it to other boards, e.g. the DE2-70 board [8], which is more powerful but has different signal mapping to the gpio_# (#=1,2) user headers.
5.13.2
Analyze and Display ADC- Output
The DE2-board has eight 7-segment-display digits. The should be used to display the DCvalue of the signal, the AC-Amplitude and its frequency (similar like oscilloscpes do).
6 Conclusions
A complete A/D and D/A conversion system for Altera DE2 board in combination with the DA2 board of the laboratory was subdivided in modules, build and demonstrated.
7 References
1076 IEEE Standard VHDL Language Reference Manual, Revision of IEEE Std. 1076, 2002 Edition. [2] M. Schubert, VHDL Course, Regensburg University of Applied Sciences. Available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories RED VHDL. [3] Lehmann, Wunder, Selz, Schaltungsdesign mit VHDL, Franzis Verlag, Poing 1994. [4] Matlab, available: http://www.mathworks.com/ [5] M. Schubert, Zusammenfassung von MATLAB-Befehlen, Regensburg University of Applied Sciences. Available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories RED Matlab. [6] A. Angermann, M. Beuschel, M. Rau, U. Wohlfarth: Matlab Simulink Stateflow, Grundlagen, Toolboxen, Beispiele, Oldenbourg Verlag, ISBN 3-486-57719-0, 4. Auflage (fr Matlab Version 7.0.1, Release 14 mit Service Pack 1). [7] Available at HSR: K:\SB\Hardware\Altera\DE2\DE2-CD\ [8] Available: http://www.terasic.com.tw/en/ Products FPGA Main Boards Cyclone II Altera DE2 Board / Altera DE2-70 board. [9] Available: http://www.altera.com/ [10] M. Schubert, Getting Started with DE2 and DA2 Boards, Electronic Design Automation Course, Regensburg University of Applied Sciences, available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories RED [11] M. Schubert, FSM Design for DSP Using VHDL, Electronic Design Automation Course, Regensburg University of Applied Sciences, available: http://homepages.fhregensburg.de/~scm39115/ [12] M. Schubert, FSM Design for DSP Using Matlab, Electronic Design Automation Course, Regensburg University of Applied Sciences, available: http://homepages.fhregensburg.de/~scm39115/ Offered Education Courses and Laboratories RED [1]
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M. Schubert
[13] M. Schubert, FSM Design for DSP Using Fixed-Point Numbers, Electronic Design Automation Course, Regensburg University of Applied Sciences, available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories RED [14] ModelSim, Available: http://model.com/ [15] ModelSim Simulator, available at HSR: K:\SB\Software\ [16] Quartus II 8.1, available at HSR: K:\SB\Software\ [17] M. Schubert, Script Systemkonzepte, Regensburg University of Applied Sciences, available: http://homepages.fh-regensburg.de/~scm39115/ Offered Education Courses and Laboratories SK [18] S. R. Norsworthy, R. Schreier, G. C. Temes, Delta-Sigma Data Converters, IEEE Press, 1996, IEE Order Number PC3954, ISBN 0-7803-1045-4. [19] J. C. Candy, G. C. Temes, 1st paper in Oversampling Delta-Sigma Data Converters, Theory, Design and Simulation, IEEE Press, IEEE Order #: PC0274-1, ISBN 0-87942285-8, 1991. [20] C. A. Leme, Oversampling Interfaces for IC Sensors, Physical Electronics Laboratory, ETH Zurich, Diss. ETH Nr. 10416. [21] Lerch, Elektrische Messtechnik, Analoge, digitale und computergettzte Verfahren, 3. Auflage, Springer Verlag, 2006. [22] E. B. Hogenauer, An economical class of digital filters for decimation and interpolation, IEEE Transactions on Acoustics, Speech and Signal Processing, California, USA, 1981.
- 49 -

ADA Conversion Project Oriented Laboratory

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Laboratory on Digital and Mixed-Signal Computer-Aided Design Automation

A / D / A Conversion System Using DE2 and DA2 Boards

Regensburg Univ. of Appl. Sciences

Requirement Analysis System Design

Subsystem Layer design freeze

Subsystem Design Module Design

Regensburg Univ. of Appl. Sciences

2 System and Subsystem Layer

Regensburg Univ. of Appl. Sciences

2.2 System Layer

sel1 3 analog world

Ddac,in DAC mux

Freq clock enable reset

Regensburg Univ. of Appl. Sciences

Regensburg Univ. of Appl. Sciences

2.3 Subsystem Layer

constant k modulator demodulator

Regensburg Univ. of Appl. Sciences

Required Anti-Alias Attenuation for M-Bit A/D Conversion

M 3 SNRdB = 10 log10 ( SNR) = 20 log10 2 2

Regensburg Univ. of Appl. Sciences

Required Order of Anti-Aliasing Filters

Fig. 3.1.2: lowpass asymptotes.

Abbreviating "log10" with "lg" the required filter order is

With function ceil for rounding up minimum filter order is

Example: AdB = -60dB, fB=2KHz, fA = 8 KHz N ceil(4.98) N = 5.

Butterworth lowpass transfer function: | H BW ( jf ) |=

Regensburg Univ. of Appl. Sciences

Matching Analog Anti-Aliasing and Digital Lowpass Filters

lHfilterl / dB analog anti-aliasing filter 0 digital lowpass

Examples: Tailoring Analog Anti-Aliasing Filters

Regensburg Univ. of Appl. Sciences

lHfilterl / dB analog antialiasing filter 0 aliasing fs/2

lHfilterl / dB analog anti-aliasing filter 0 digital lowpass aliasing digital lowpass

Bandwidth of the analog anti-aliasing lowpass:

Attenuation frequency of the lowpass:

Required order of the anti-aliasing lowpass:

Regensburg Univ. of Appl. Sciences

Considerations for Digital Anti-Alias Filtering

Fig. 3.2.1: sampled waveform

Regensburg Univ. of Appl. Sciences

3.3 Aliasing at Digital Re-Sampling

Regensburg Univ. of Appl. Sciences

Application of Sinc Filters for Decimation

Regensburg Univ. of Appl. Sciences

Optimizing Sinc Filters for Decimation

Regensburg Univ. of Appl. Sciences

Cascaded-Integrator-Comb (CIC) Filter

1 accumulate & daump f s0 f s2 Dsr

Regensburg Univ. of Appl. Sciences

Using Sinc Filters for Interpolation

sincL filter sinc filter L fs0

Regensburg Univ. of Appl. Sciences

Sinc Filter Construction

In case of a sinc filter this reduces to

which can be shown to be identical to

Regensburg Univ. of Appl. Sciences

Sinc Filter Composed of Combined Comb-Filter

Sinc Filter for CIC Topology

Regensburg Univ. of Appl. Sciences

Accumulate-and-Dump (ACD) Sinc Filter Before Decimation

Regensburg Univ. of Appl. Sciences

Matlab> f=10:1:10000; s=j2pif; Hs = a0+a1s+...+ak*s.^k;

Matlab> F=0:1e-4:0.5; z=exp(j2piF); Hz = a0+a1z+...+ak*z.^k;