DESIGN OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM

AIM: The main aim of the project is to design and implement DESIGN OF LOW POWER HIGH SPEED VLSI ADDER SUBSYSTEM. ABSTRACT: The design of adder subsystem is the most focused area in VLSI design of processing units. So far there are a variety of such adders like RC ! CS ! CL and "T . "T is the "rror Tolerant dder and is the latest of the adders #hich has better performance #hen compared #ith the other adders in terms of po#er consumption! delay etc. $hereas the designs so far is by front end tools that performs simulations #ith ideal parameters instead of real time conditions. So! here in this paper! the design is approached through backend tool under real time simulation conditions. The results sho#ed that the adder performance in terms of accuracy! delay! si%e and #ith &'( lesser po#er consumption than that of the conventional C)*S adders. Propose !e"#o : In this paper #hile implementing the adder #e need +or gate . actually it re,uires -. transistor/s to implement . #e can implement this +or gate #ith 0 transistors . in this #ay #e reduce the area! delay! po#er consumption

V.Mallikarjuna (Project manager)

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BLOC$ DIAGRAM:

1ig2 "T 3 inaccurate part.Carry free addition block

TOOLS: hspice_vA- !!".!#$ t-spice APPLICATION ADVANTAGES: This logic proves to be more promising and optimal in the field of application specific processing units. These adders are effective to be implemented practically. In future #e are going to implement this logic in multipliers and #ork on its performance improvement #ith different techni,ues in multiplication. REFERENCES:

V.Mallikarjuna (Project manager)

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 45esign of lo#3 po#er high3speed error Tolerant shift and add multiplier4 6ournal of computer science & 7-892 -:0;3-:.<! 8'---ssn -<.;3 0=0= > 8'-- science publications Corresponding author2 - k.n. vijeyakumar! 45esign of lo#3po#er high3speed truncation error3 tolerant adder and its application in digital signal processing4 ning %hu! #ang ling goh! #eija %hang! kiat seng yeo! and %hi hui kong ieee transactions on very large scale integration 7vlsi9 systems! vol. -:! no. :. 45esign and error3tolerance in the presence of massive numbers of defects!4 m. . ?reuer! s. @. Aupta! and t. ) )ak! ieee des. Test Comput.! vol. 8.! no. 0! pp. 8-=388&. 4 novel testing methodology ?ased on error3rate to support error3 . ?reuer! in proc. -nt. Test conj!

tolerance!4 k. 6. Lee! t. B. Csieh! and m. pp. 6l 0=36l ...

S. Chong and a. *rtega! 4Card#are testing for error tolerant multimedia compression based on linear transforms!4 in proc. 5efect and 1ault tolerance in vlsi syst. Symp.! pp. <80'3<0-.

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &