High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics AIM: The main aim of the project

is to design High Speed ASIC Design of Complex Multiplier Using Vedic Mathematics A!S"#AC": Vedic Mathematics is the ancient methodology of Indian mathematics which has a unique technique of calculations based on 16 Sutras ( ormulae!" # high speed comple$ multiplier design (#SI%! using Vedic Mathematics is presented in this paper" The idea for designing the multiplier and adder & subtractor unit is adopted from ancient Indian mathematics 'Vedas'" (n account of those formulas) the partial products and sums are generated in one step which reduces the carry propagation from *S+ to MS+" The implementation of the Vedic mathematics and their application to the comple$ multiplier ensure substantial reduction of propagation delay in comparison with ,# based architecture and parallel adder based implementation which are most commonly used architectures" The functionality of these circuits was chec-ed and performance parameters li-e propagation delay and dynamic power consumption were calculated by spice spectre using standard ./nm %M(S technology" The propagation delay of the resulting (16) 16!$(16) 16! comple$ multiplier is only 0ns and consume 6"1 m2 power" 2e achie3ed almost 415 impro3ement in speed from earlier reported comple$ multipliers) e"g" parallel adder and ,# based architectures"

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

!$%C& DIA'#AM:

ig6 7ardware implementation of 8S9"

"%%$S: :ilin$ ."4IS;) Modelsim6"0c" A(($ICA"I%) ADVA)"A'*S: This no3el architecture combines the ad3antages of the Vedic mathematics for multiplication which encounters the stages and partial product reduction" The proposed comple$ number multiplier offered 4/5 and 1.5 impro3ement in terms of propagation delay and power consumption respecti3ely) in comparison with parallel adder based implementation"
V.Mallikarjuna (Project manager) Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

#*+*#*)C*S: <" =" Saha) #" +anerjee) and #" ,andapat) '7igh Speed *ow <ower %omple$ Multiplier ,esign 9sing <arallel #dders and Subtractors)' International >ournal on ;lectronic and ;lectrical ;ngineering) (&>;;;!) 3ol /?) no" II) pp @AB06" 8" ;" +lahut) ast #lgorithms for ,igital Signal <rocessing) 8eading) M#6 #ddisonB2esley" S" 7e) and M" Tor-elson) '# pipelined bitBserial comple$ multiplier using distributed arithmetic)' in proceedings I;;; International Symposium on %ircuits and Systems) Seattle) 2 #) pp" 4@1@B4@16" >" ;" VoIder) 'The %(8,I% trigonometric computing technique)' I8; Trans" ;lectron" %omput") 3ol" ;%BA) pp" @@/B@@0" 8" =rishnan) C" #" >ullien) and 2" %" Miller) '%omple$ digital signal processing using quadratic residue number systems)' I;;; Trans" #coust") Speech) Signal <rocessing) 3ol" @0"

V.Mallikarjuna (Project manager)

ISO: 9001- 2008 CERTIFIED COMPANY

Na'()r

Mobile No: +91-8297578555. Branch !: "#$ ra%a$ &