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74AC08, 74ACT08 Quad 2-Input AND Gate: Features General Description
74AC08, 74ACT08 Quad 2-Input AND Gate: Features General Description
January 2008
General Description
The AC08/ACT08 contains four, 2-input AND gates.
Ordering Information
Order Number
74AC08SC 74AC08SJ 74AC08MTC 74AC08PC 74ACT08SC 74ACT08MTC 74ACT08PC
Package Number
M14A M14D MTC14 N14A M14A MTC14 N14A
Package Description
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter X to the ordering number. All packages are lead free per JEDEC: J-STD-020B standard.
Connection Diagram
Logic Symbol
IEEE/IEC
Pin Description
Pin Names
An, Bn On
Description
Inputs Outputs
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Symbol
VCC IIK Supply Voltage DC Input Diode Current VI = 0.5V VI = VCC + 0.5 VI IOK DC Input Voltage DC Output Diode Current VO = 0.5V VO = VCC + 0.5V VO IO TSTG TJ DC Output Voltage
Parameter
Rating
0.5V to +7.0V 20mA +20mA 0.5V to VCC + 0.5V 20mA +20mA 0.5V to VCC + 0.5V 50mA 50mA 65C to +150C 140C
Symbol
VCC Supply Voltage AC ACT VI VO TA V / t V / t Input Voltage Output Voltage Operating Temperature
Parameter
Rating
2.0V to 6.0V 4.5V to 5.5V 0V to VCC 0V to VCC 40C to +85C 125mV/ns 125mV/ns
Minimum Input Edge Rate, AC Devices: VIN from 30% to 70% of VCC, VCC @ 3.3V, 4.5V, 5.5V Minimum Input Edge Rate, ACT Devices: VIN from 0.8V to 2.0V, VCC @ 4.5V, 5.5V
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Parameter
Minimum HIGH Level Input Voltage
VCC (V)
3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5 3.0 4.5 5.5
TA = +25C Conditions
VOUT = 0.1V or VCC 0.1V VOUT = 0.1V or VCC 0.1V IOUT = 50A
Typ.
1.5 2.25 2.75 1.5 2.25 2.75 2.99 4.49 5.49 2.1 3.15 3.85 0.9 1.35 1.65 2.9 4.4 5.4 2.56 3.86 4.86 0.002 0.001 0.001 0.1 0.1 0.1 0.36 0.36 0.36 0.1
VIL
VOH
VIN = VIL or VIH, IOH = 12mA VIN = VIL or VIH, IOH = 24mA VIN = VIL or VIH, IOH = 24mA(1) IOUT = 50A
VOL
VIN = VIL or VIH, IOL = 12mA VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL = 24mA(1) VI = VCC, GND VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND
IIN
(3)
Maximum Input Leakage Current Minimum Dynamic Output Current(2) Maximum Quiescent Supply Current
2.0
20.0
Notes: 1. All outputs loaded; thresholds on input associated with output under test. 2. Maximum test duration 2.0ms, one output loaded at a time. 3. IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
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Parameter
Minimum HIGH Level Input Voltage Maximum LOW Level Input Voltage Minimum HIGH Level Output Voltage
VCC (V)
4.5 5.5 4.5 5.5 4.5 5.5 4.5 5.5
TA = +25C Conditions
VOUT = 0.1V or VCC 0.1V VOUT = 0.1V or VCC 0.1V IOUT = 50A VIN = VIL or VIH, IOH = 24mA VIN = VIL or VIH, IOH = 24mA(4) IOUT = 50A VIN = VIL or VIH, IOL = 24mA VIN = VIL or VIH, IOL= 24mA(4) VI = VCC, GND VI = VCC 2.1V VOLD = 1.65V Max. VOHD = 3.85V Min. VIN = VCC or GND 4.0 0.6 0.001 0.001 4.86 0.1 0.1 0.36 0.36 0.1
Typ.
1.5 1.5 1.5 1.5 4.49 5.49 2.0 2.0 0.8 0.8 4.4 5.4 3.86
VOL
Maximum Input Leakage Current Maximum ICC/Input Minimum Dynamic Output Current(5) Maximum Quiescent Supply Current
Notes: 4. All outputs loaded; thresholds on input associated with output under test. 5. Maximum test duration 2.0ms, one output loaded at a time.
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Parameter
Propagation Delay Propagation Delay
VCC (V)(6)
3.3 5.0 3.3 5.0
Min.
1.5 1.5 1.5 1.5
Typ.
7.5 5.5 7.0 5.5
Max.
9.5 7.5 8.5 7.0
Max.
10.0 8.5 9.0 7.5
Units
ns ns
Note: 6. Voltage range 3.3 is 3.3V 0.3V. Voltage range 5.0 is 5.0V 0.5V.
Parameter
Propagation Delay Propagation Delay
VCC (V)(7)
5.0 5.0
Min.
1.0 1.0
Typ.
6.5 6.5
Max.
9.0 9.0
Max.
10.0 10.0
Units
ns ns
Capacitance
Symbol
CIN CPD
Parameter
Input Capacitance Power Dissipation Capacitance
Conditions
VCC = OPEN VCC = 5.0V
Typ.
4.5 20.0
Units
pF pF
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Physical Dimensions
8.75 8.50 7.62
14 8 B A
0.65
1.70
1.27
1.27 (0.33)
0.51 0.35
0.25
M
SEE DETAIL A
0.25 0.19
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AB, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD GAGE PLANE FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X145-14M 0.36 E) DRAWING CONFORMS TO ASME Y14.5M-1994 F) DRAWING FILE NAME: M14AREV13
SEATING PLANE
Figure 1. 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
1988 Fairchild Semiconductor Corporation 74AC08, 74ACT08 Rev. 1.5.1 www.fairchildsemi.com 6
Figure 2. 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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0.43 TYP
0.65
1.65
0.45
6.10
& BOTTOM
A. CONFORMS TO JEDEC REGISTRATION MO-153, VARIATION AB, REF NOTE 6 B. DIMENSIONS ARE IN MILLIMETERS C. DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS D. DIMENSIONING AND TOLERANCES PER ANSI Y14.5M, 1982 E. LANDPATTERN STANDARD: SOP65P640X110-14M F. DRAWING FILE NAME: MTC14REV6
1.00
R0.09min
Figure 3. 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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6.60 6.09 1
(1.74)
3.56 3.30
3.81 3.17
0.58 0.35
2.54
8.82
NOTES: UNLESS OTHERWISE SPECIFIED THIS PACKAGE CONFORMS TO A) JEDEC MS-001 VARIATION BA B) ALL DIMENSIONS ARE IN MILLIMETERS. DIMENSIONS ARE EXCLUSIVE OF BURRS, C) MOLD FLASH, AND TIE BAR EXTRUSIONS. D) DIMENSIONS AND TOLERANCES PER ASME Y14.5-1994 E) DRAWING FILE NAME: MKT-N14AREV7
Figure 4. 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specications do not expand the terms of Fairchilds worldwide terms and conditions, specically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductors online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/
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