HIGH THROUGHPUT AES ENCRYPTION WITH MASKED S-BOX

SUBMITTED BY ASMABI V
APPLIED ELECTRONICS MAHARAJA INSTITUTE OF TECHNOLOGY

ABSTRACT

Increasing need of data protection in computer networks led to the development of several cryptographic algorithms hence sending data securely over a transmission link is critically important in many applications. .The Advanced Encryption Standard (AES) is a specification for the encryption of electronic data established by NIST. The algorithm described by AES is a symmetric-key algorithm, meaning the same key is used for both encrypting and decrypting the data. the AES standard states that the algorithm can only accept a block size of 128 bits and a choice of three keys - 128, 192, 256 bits .Hardware implementation of cryptographic algorithms are physically secure than software implementations since outside attackers cannot modify them. In order to achieve higher performance in todays heavily loaded communication networks, hardware implementation is a wise choice in terms of better speed and reliability. By exploring different granularities of data-level and task-level parallelism, we map 16 implementations of an Advanced Encryption Standard (AES) cipher with both online and offline key expansion on a fine-grained many-core system. AES implementations on a fine-grained many-core system can achieve high performance, throughput per unit of chip area and energy efficiency compared to other software platforms. In order to protect data-at-rest in storage area networks from the risk of differential power analysis attacks without degrading performance, a high-throughput masked advanced encryption standard (AES) engine is proposed.

EXISTING SYSTEM
The AES is a computer security standard from NIST intended for protecting electronic data. The AES cryptography algorithm is capable of encrypting and decrypting 128 bit data using cipher keys of 128, 196 or 256 bits (AES128, AES196 and AES256). AES use Rijndael algorithm Rijndael encryption consist of four operations 1. Substitution 2. Shift Row 3. Mix Column 4. Key Addition The encryption of AES is carried out in blocks with a fixed block size of 128 bits each. The AES cipher calculation is specified as a number of repetitions of transformation rounds that convert the input plaintext into the final output of cipher text. Each round consists of several processing steps, including one that depends on the encryption key. A set of reverse rounds are applied to transform the cipher text back into the original plaintext using the same encryption key. Figure 1 shows the flowchart of the AES-128 algorithm. From this figure, we can see that the AES-128 algorithm is iterative and consists of 10 rounds. The input is a block of data and the initial key. Each round operates on the intermediate result of the previous round and is a sequence of the four transformations, namely Sub Bytes, Shift Rows, Mix Columns and Add Round-Key. The intermediate result of any step is called the state. The final round is slightly different and the output after 10 rounds is the block of encrypted data In the Sub Bytes step, each byte in the state matrix is replaced with a Sub Byte using an 8-bit data from the Rijndael S-Box. The Shift Rows transformation cyclically shifts the bytes in each row by certain offset to the left. In the Mix Column step, the four bytes of each column of the state are combined using an invertible linear transformation .In Add Round Key operation, bitwise exclusive-or (XOR) operation is performed between outputs from Mix Column and Round Key. For AES-128, 128 bit XOR operations are performed.

FIGURE 1: Block

diagram of AES encryption.

PROPOSED SYSTEM
The performance increase of an architecture is roughly proportional to the square root of its increase in complexity. The rule implies that if we double the logic area in a processor, the performance of the core speeds up around 40 percent. On the other hand, a many core architecture has the potential to provide near linear performance improvement with complexity. For instance, instead of building a complicated core twice as large as before, a processor containing two cores (each is identical to the other) could achieve a possible 2x performance improvement if the application can be fully parallelized. Therefore, if the target application has enough inherent parallelism, architecture with thousands of small cores would offer a better performance than one with a few large cores within the same die area.

Implementations of the AES algorithm with different data and task parallelism granularity, and shows that AES implementations on a fine-grained many-core system can achieve high performance, throughput per unit of chip area and energy efficiency compared to other software platforms. The targeted Asynchronous Array of Simple Processors (AsAP) architecture is an example of a fine-grained many-core computation platform, supporting globally-asynchronous locally synchronous on-chip network and dynamic voltage and frequency scaling. Programming the AsAP array follows three basic steps 1. Each task of the application is mapped to one or few processors on the array. 2. The inputs and outputs of different tasks are interconnected using a configuration file or a mapping tool 3. After compiled by compiler and assembler, the programs of tasks are mapped to the 2D mesh AsAP array. We present the eight AES implementations They are 1. One-Task One-Processor (OTOP) 2. Loop-Unrolled Nine Times 3. Loop-Unrolled Three Times 4. Loop-Unrolled Three Times 5. Parallel-Mix Columns 6. Parallel-Sub Bytes-Mix Columns 7. Full-Parallelism 8. No-Merge-Parallelism

MODIFIED SYSTEM

In order to protect data-at-rest in storage area networks from the risk of differential power analysis attacks without degrading performance, a high-throughput masked advanced encryption standard (AES) engine is proposed. In this system a masked S-Box is used during encryption. However, this engine usually adopts the unrolling technique which requires extremely large field programmable gate array (FPGA) resources. In this brief, this aim to optimize the area for a

masked AES with an unrolled structure. This is achieved by mapping its operations from GF( to GF( ) as much as possible. Thus reduce the number of mapping [GF( ) to GF( ) to GF(

and

inverse mapping [GF(

)] operations of the masked SubBytes step from ten to one.

In order to be compatible, the masked Mix- Columns, masked AddRoundKey, and masked ShiftRows including the redundant masking values are carried over GF( ).

TOOLS REQUIRED

Xilinx ISE Modelsim

PLAN OF COMPLETION

Phase1: Implementation of proposed system Phase2: implementation of Modified system

REFERENCES 1. Parallel AES Encryption Engines for Many Core Processor Arrays
Bin Liu, Student Member, IEEE, and Bevan M. Baas, Senior Member, IEEE

IEEE TRANSACTIONS ON COMPUTERS, VOL. 62, NO. 3, MARCH 2013 2 FPGA-Based 40.9-Gbits/s Masked AES With Area Optimization for Storage Area Network Yi Wang and Yajun Ha, Senior Member, IEEE IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMSII: EXPRESS BRIEFS, VOL. 60, NO. 1, JANUARY 2013 3 High Performance Hardware Implementation of AES Using Minimal Resources

Abhijith.P.S, Mallika Srivastava, Aparna Mishra, Dept. of Microelectronics, IIITA, India 2013 International Conference on Intelligent Systems and Signal Processing (ISSP)