A.1 Sketch a schematic of the circuit described by the following HDL code.

Simplify to a minimum number of gates.

-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity EXA1 is
port(a, b, c: in STD_LOGIC;
y, z: out STD_LOGIC);
end;
architecture synth of EXA1 is
begin
y <= (a and b and c) or (a and b and (not c)) or
(a and (not b) and c);
z <= (a and b) or ((not a) and (not b));
end;
-------------------------------------------------------------------------A.2 Sketch a schematic of the circuit described by the following HDL code.
Simplify to a minimum number of gates.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity EXA2 is
port(a: in STD_LOGIC_VECTOR (3 downto 0);
y: out STD_LOGIC_VECTOR (1 downto 0));
end;
architecture synth of EXA2 is
begin
process(a) begin
if a(0) = '1' then y <= "11";
elsif a(1) = '1' then y <= "10";
elsif a(2) = '1' then y <= "01";
elsif a(3) = '1' then y <= "00";
else y <= a(1 downto 0);
end if;
end process;
end;

A.3 Write an HDL module that computes a 4-input XOR function. The input is
A3:0 and the output is Y.
A.4 Write a self-checking testbench for Exercise A.3. Create a test vector
file containing all 16 test cases. Simulate the circuit and show that it
works. Introduce an error in the test vector file and show that it reports
a mismatch.
-------------------------------- VHDL CODE ------------------------------library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity testbench1 is -- no inputs or outputs
end;
architecture sim of testbench1 is
component EXA3
port(a : in STD_LOGIC_VECTOR (3 downto 0);
y: out STD_LOGIC);
end component;
signal a: STD_LOGIC_VECTOR (3 downto 0);
signal y: STD_LOGIC ;
begin
-- instantiate device under test
dut: EXA3 port map(a,y);
-- apply inputs one at a time
process begin
a(0) <= '0'; a(1)<= '0'; a(2) <= '0' ;a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(2) <= '1'; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(1) <= '1'; a(2) <= '0'; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(2) <= '1'; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(0) <= '1'; a(1)<= '0'; a(2) <= '0' ; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(2) <= '1'; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(1) <= '1'; a(2) <= '0'; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
a(2) <= '1'; a(3) <= '0'; wait for 10 ns;
a(3) <= '1'; wait for 10 ns;
wait; -- wait forever
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity EXA3 is
port(a: in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end EXA3;
architecture synth of EXA3 is
begin
y <= a(0) xor a(1) xor a(2) xor a(3);
end synth;

A.5 Write an HDL module called minority. It receives three inputs, A, B,

and C. It produces one output Y that is TRUE if at least two of the inputs
are FALSE.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench2 is -- no inputs or outputs
end;
architecture sim of testbench2 is
component EXA5
port(a, b, c: in STD_LOGIC;
y: out STD_LOGIC);
end component;
signal a, b, c, y: STD_LOGIC;
begin
-- instantiate device under test
dut: EXA5 port map(a, b, c, y);
-- apply inputs one at a time
process begin
a <= '0'; b <= '0'; c <= '0'; wait for 10 ns;
c <= '1'; wait for 10 ns;
b <= '1'; c <= '0'; wait for 10 ns;
c <= '1'; wait for 10 ns;
a <= '1'; b <= '0'; c <= '0'; wait for 10 ns;
c <= '1'; wait for 10 ns;
b <= '1'; c <= '0'; wait for 10 ns;
c <= '1'; wait for 10 ns;
wait; -- wait forever
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity EXA5 is
port(a , b ,c : in STD_LOGIC;
y : out STD_LOGIC);
end EXA5;
architecture synth of EXA5 is
begin
y <= (not a and not b) or (not c and (a xor b));
end synth;

A.6 Write an HDL module for a hexadecimal 7-segment display decoder. The
decodershould handle the digits A, B, C, D, E, and F as well as 09.
A.7 Write a self-checking testbench for Exercise A.6. Create a test vector
file containing all 16 test cases. Simulate the circuit and show that it
works. Introduce an error in the test vector file and show that it reports
a mismatch.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench3 is -- no inputs or outputs
end;
architecture sim of testbench3 is
component EXA6
port(data : in STD_LOGIC_VECTOR (3 downto 0);
segments: out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal data: STD_LOGIC_VECTOR (3 downto 0);
signal segments: STD_LOGIC_VECTOR (6 downto 0) ;
begin
dut: EXA6 port map(data,segments);
process begin
data(0) <= '0'; data(1)<= '0'; data(2) <= '0' ;data(3) <= '0'; wait for 10
ns;
data(3) <= '1'; wait for 10 ns;
data(2) <= '1'; data(3) <= '0'; wait for 10 ns;
data(3) <= '1'; wait for 10 ns;
data(1) <= '1'; data(2) <= '0'; data(3) <= '0'; wait for 10 ns;
data(3) <= '1'; wait for 10 ns;
data(2) <= '1'; data(3) <= '0'; wait for 10 ns;
data(3) <= '1'; wait for 10 ns;
data(0) <= '1'; data(1)<= '0'; data(2) <= '0' ; data(3) <= '0'; wait for
10 ns;
data(3) <= '1'; wait for 10 ns;
data(2) <= '1'; data(3) <= '0'; wait for 10 ns;
data(3) <= '1'; wait for 10 ns;
data(1) <= '1'; data(2) <= '0'; data(3) <= '0'; wait for 10 ns;
data(3) <= '1'; wait for 10 ns;
data(2) <= '1'; data(3) <= '0'; wait for 10 ns;
data(3) <= '1'; wait for 10 ns; wait; -- wait forever
end process;
end;
library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity EXA6 is
port(data: in STD_LOGIC_VECTOR (3 downto 0);
segments: out STD_LOGIC_VECTOR (6 downto 0));
end EXA6;
architecture synth of EXA6 is
begin
process(data) begin
case data is
when "0000" => segments <= "1111110";
when "0001" => segments <= "0110000";
when "0010" => segments <= "1101101";
when "0011" => segments <= "1111001";
when "0100" => segments <= "0110011";
when "0101" => segments <= "1011011";
when "0110" => segments <= "1011111";
when "0111" => segments <= "1110000";

when "1000" => segments <= "1111111";

when "1001" => segments <= "1111011";
when "1010" => segments <= "1110111";
when "1011" => segments <= "1111111";
when "1100" => segments <= "1111000";
when "1101" => segments <= "1111110";
when "1110" => segments <= "1111001";
when "1111" => segments <= "1110001";
when others => segments <= "0000000";
end case;
end process;
end synth ;
-------------------------------------------------------------------------A.8 Write an 8:1 multiplexer module called mux8 with inputs S2:0, D0, D1,
D2, D3, D4,
D5, D6, D7, and output Y.
--------------------------------- VHDL CODE -----------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench4 is -- no inputs or outputs
end;
architecture sim of testbench4 is
component EXA8
PORT(d:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
y:OUT STD_LOGIC);
end component;
signal d: STD_LOGIC_VECTOR (7 DOWNTO 0) :="10110010" ;
signal SEL : STD_LOGIC_VECTOR (2 DOWNTO 0);
signal y: STD_LOGIC;
begin
-- instantiate device under test
dut: EXA8 port map(d, SEL, y);
-- apply inputs one at a time
process begin
SEL(0) <= '0'; SEL(1) <= '0'; SEL(2) <= '0'; wait for 10 ns;
SEL(2) <= '1'; wait for 10 ns;
SEL(1) <= '1'; SEL(2) <= '0'; wait for 10 ns;
SEL(2) <= '1'; wait for 10 ns;
SEL(0) <= '1'; SEL(1) <= '0'; SEL(2) <= '0'; wait for 10 ns;
SEL(2) <= '1'; wait for 10 ns;
SEL(1) <= '1'; SEL(2) <= '0'; wait for 10 ns;
SEL(1) <= '1'; wait for 10 ns;
wait; -- wait forever
end process;
end;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164 .ALL;
ENTITY EXA8 IS
PORT(d:IN STD_LOGIC_VECTOR (7 DOWNTO 0);
SEL:IN STD_LOGIC_VECTOR (2 DOWNTO 0);
y:OUT STD_LOGIC);
END EXA8;
ARCHITECTURE synth OF EXA8 IS
BEGIN
PROCESS(d,SEL)
BEGIN
CASE SEL IS

WHEN "000" =>y<=d(0);

WHEN "001" =>y<=d(1);
WHEN "010" =>y<=d(2);
WHEN "011" =>y<=d(3);
WHEN "100" =>y<=d(4);
WHEN "101" =>y<=d(5);
WHEN "110" =>y<=d(6);
WHEN "111" =>y<=d(7);
WHEN OTHERS =>
y<='Z';
END CASE;
END PROCESS;
END synth;
-------------------------------------------------------------------------A.9 Write a structural module to compute Y = AB + BC + ABC using
multiplexer logic. Use the 8:1 multiplexer from Exercise A.8.
-------------------------------- VHDL CODE ------------------------------library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity EXA9 is
port(
sel : in STD_LOGIC_VECTOR (2 downto 0);
dout : out STD_LOGIC
);
end EXA9;
architecture synth of EXA9 is
signal din : STD_LOGIC_VECTOR (7 downto 0):= "10011100" ;
begin
dout <= din(7) when (sel="000") else
din(6) when (sel="001") else
din(5) when (sel="010") else
din(4) when (sel="011") else
din(3) when (sel="100") else
din(2) when (sel="101") else
din(1) when (sel="110") else
din(0);
end synth;
-------------------------------------------------------------------------A.10 Repeat Exercise A.9 using a 4:1 multiplexer and as many NOT gates as
you need.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench5 is -- no inputs or outputs
end;
architecture sim of testbench5 is
component EXA10
PORT(
z :in STD_LOGIC ;
sel : in STD_LOGIC_VECTOR (1 downto 0);
dout : out STD_LOGIC
);
end component;
signal z: STD_LOGIC :='0' ;
signal sel : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal dout: STD_LOGIC;
--signal din : STD_LOGIC_VECTOR(1 downto 0):= "10" ;
begin

-- instantiate device under test

dut: EXA10 port map(z,sel, dout);
-- apply inputs one at a time
process begin
sel(0) <= '0'; sel(1) <= '0'; wait for 10 ns;
sel(1) <= '1'; wait for 10 ns;
sel(0) <= '1'; sel(1) <= '0'; wait for 10 ns;
sel(1) <= '1'; wait for 10 ns;
wait; -- wait forever
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity EXA10 is
port(
z :in STD_LOGIC ;
sel : in STD_LOGIC_VECTOR (1 downto 0);
dout : out STD_LOGIC
);
end EXA10;
architecture synth of EXA10 is
signal din : STD_LOGIC_VECTOR (1 downto 0):= "10" ;
begin
dout <= not z when (sel="00") else
z when (sel="01") else
din(1) when (sel="10") else
din(0);
end synth;
-------------------------------------------------------------------------A.12 Write an HDL module for an 8-input priority circuit.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench6 is -- no inputs or outputs
end;
architecture sim of testbench6 is
component EXA12
port(a : in STD_LOGIC_vector (7 downto 0);
y : out STD_LOGIC_vector (2 downto 0));
end component;
signal a: STD_LOGIC_vector (7 downto 0);
signal y: STD_LOGIC_vector (2 downto 0);
begin
-- instantiate device under test
dut: EXA12 port map(a, y);
-- apply inputs one at a time
process begin
a(7) <= '1'; a(6) <= '0'; a(5) <= '0'; a(4) <= '0'; a(3) <= '0'; a(2) <=
'0'; a(1) <= '0';a(0)
<= '0'; wait for 10 ns;
a(7) <= '0'; a(6) <= '1'; a(5) <= '0'; a(4) <= '1'; a(3) <= '1'; a(2) <=
'0'; a(1) <= '0';a(0)
<= '1'; wait for 10 ns;
a(7) <= '0'; a(6) <= '0'; a(5) <= '1'; a(4) <= '1'; a(3) <= '0'; a(2) <=
'1'; a(1) <= '0';a(0)
<= '1'; wait for 10 ns;
a(7) <= '0'; a(6) <= '0'; a(5) <= '0'; a(4) <= '1'; a(3) <= '0'; a(2) <=
'1'; a(1) <= '0';a(0)

<= '0'; wait for 10 ns;

a(7) <= '0'; a(6) <= '0'; a(5) <= '0'; a(4) <= '0'; a(3) <= '1'; a(2) <=
'0'; a(1) <= '1';a(0)
<= '0'; wait for 10 ns;
a(7) <= '0'; a(6) <= '0'; a(5) <= '0'; a(4) <= '0'; a(3) <= '0'; a(2) <=
'1'; a(1) <= '1';a(0)
<= '0'; wait for 10 ns;
a(7) <= '0'; a(6) <= '0'; a(5) <= '0'; a(4) <= '0'; a(3) <= '0'; a(2) <=
'0'; a(1) <= '1';a(0)
<= '1'; wait for 10 ns;
a(7) <= '0'; a(6) <= '0'; a(5) <= '0'; a(4) <= '0'; a(3) <= '0'; a(2) <=
'0'; a(1) <= '0';a(0)
<= '1'; wait for 10 ns;
wait; -- wait forever
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity EXA12 is
port(a : in STD_LOGIC_vector (7 downto 0);
y : out STD_LOGIC_vector (2 downto 0));
end EXA12;
architecture synth of EXA12 is
begin
y <= "111" when a(7) = '1' else
"110" when a(6) = '1' else
"101" when a(5) = '1' else
"100" when a(4) = '1' else
"011" when a(3) = '1' else
"010" when a(2) = '1' else
"001" when a(1) = '1' else
"000" when a(0) = '1';
end synth;
Date: November 05, 2013 EXA13.vhd Project: VHDL_EX
A.13 Write an HDL module for a 2:4 decoder.
-------------------------------- VHDL CODE ----------------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench7 is -- no inputs or outputs
end;
architecture sim of testbench7 is
component EXA13
PORT( SEL : in std_logic_vector (1 downto 0);
outp : out std_logic_vector (3 downto 0)
);
end component;
signal SEL : STD_LOGIC_VECTOR (1 DOWNTO 0);
signal outp: std_logic_vector (3 downto 0) ;
begin
-- instantiate device under test
dut: EXA13 port map( SEL, outp);
-- apply inputs one at a time
process begin
SEL(0) <= '0'; SEL(1) <= '0'; wait for 10 ns;
SEL(1) <= '1'; wait for 10 ns;
SEL(0) <= '1'; SEL(1) <= '0'; wait for 10 ns;
SEL(1) <= '1'; wait for 10 ns;

wait; -- wait forever

end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .all;
entity EXA13 is
port ( SEL : in std_logic_vector (1 downto 0);
outp : out std_logic_vector (3 downto 0)
);
end EXA13;
architecture synth of EXA13 is
begin
with SEL select
outp <= "0001" when "00",
"0010" when "01",
"0100" when "10",
"1000" when "11",
"0000" when others;
end synth ;
Date: November 05, 2013 EXA17.vhd Project: VHDL_EX
A.17 Write an HDL module for an SR latch.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench8 is -- no inputs or outputs
end;
architecture sim of testbench8 is
component EXA17
port( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC);
end component;
signal S , R ,Q: STD_LOGIC;
--signal Q: STD_LOGIC:='0';
begin
-- instantiate device under test
dut: EXA17 port map(S , R ,Q);
-- apply inputs one at a time
process begin
S <= '0'; R <= '0'; wait for 10 ns;
R <= '1'; wait for 10 ns;
S <= '1'; R <= '0'; wait for 10 ns;
R <= '1'; wait for 10 ns;
wait; -- wait forever
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
entity EXA17 is
Port ( S : in STD_LOGIC;
R : in STD_LOGIC;
Q : inout STD_LOGIC);
end EXA17;
architecture synth of EXA17 is
signal notQ : STD_LOGIC;
begin
Q <=Rnor notQ;
notQ <= S nor Q;

end synth;
-------------------------------------------------------------------------A.18 Write an HDL module for a JK flip-flop. The flip-flop has inputs clk,
J, and K, and output Q. On the rising edge of the clock, Q keeps its old
value if J = K = 0. It sets Q to 1 if J = 1, resets Q to 0 if K = 1, and
inverts Q if J = K = 1.
-------------------------------- VHDL CODE ------------------------------library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
use IEEE.STD_LOGIC_ARITH .ALL;
use IEEE.STD_LOGIC_UNSIGNED .ALL;
entity EXA18 is
port( J,K: in std_logic;
Reset: in std_logic;
Clock_enable : in std_logic;
Clock: in std_logic;
Output: out std_logic);
end EXA18;
architecture Behavioral of EXA18 is
signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
if Reset='1' then
temp <= '0';
elsif Clock_enable ='1' then
if (J='0' and K='0') then
temp <= temp;
elsif (J='0' and K='1') then
temp <= '0';
elsif (J='1' and K='0') then
temp <= '1';
elsif (J='1' and K='1') then
temp <= not (temp);
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral ;
-------------------------------------------------------------------------A.19 Write a line of HDL code that gates a 32-bit bus called data with
another signal
called sel to produce a 32-bit result. If sel is TRUE, result = data.
Otherwise,
result should be all 0s.
-------------------------------- VHDL CODE -----------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity testbench9 is -- no inputs or outputs
end;
architecture sim of testbench9 is
component EXA19
port( data: in std_logic_vector (31 downto 0);
sel : in std_logic ;
result : out std_logic_vector (31 downto 0) );
end component;

signal data: std_logic_vector (31 downto 0);

signal sel: STD_LOGIC;
signal result: std_logic_vector (31 downto 0);
begin
-- instantiate device under test
dut: EXA19 port map(data , sel ,result);
-- apply inputs one at a time
process begin
sel <= '0'; data <= "00000000000011111111110000000000" ; wait for 10 ns;
sel <= '1'; data <= "00000000000011111111110000000000" ; wait for 10 ns;
wait; -- wait forever
end process;
end;
library IEEE;
use IEEE.STD_LOGIC_1164 .ALL;
entity EXA19 is
port( data: in std_logic_vector (31 downto 0);
sel : in std_logic ;
result : out std_logic_vector (31 downto 0) );
end EXA19 ;
architecture synth of EXA19 is
begin
process (sel)
begin
if sel='1' then
result <= data ;
else
result <= "00000000000000000000000000000000" ;
end if;
end process ;
end synth ;
-------------------------------------------------------------------------A.16 Sketch the state transition diagram for the FSM described by the
following HDL code. An FSM of this nature is used in a branch predictor on
some microprocessors .
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity fsm1 is
port(clk, reset: in STD_LOGIC;
taken, back: in STD_LOGIC;
predicttaken : out STD_LOGIC);
end;
architecture synth of fsm1 is
type statetype is (S0, S1, S2, S3, S4);
signal state, nextstate: statetype;
begin
process(clk, reset) begin
if reset = '1' then state <= S2;
elsif clk'event and clk = '1' then
state <= nextstate;
end if;
end process;
process (state, taken) begin
case state is
when S0 => if taken = '1' then
nextstate <= S1;
else nextstate <= S0;

end if;
when S1 => if taken = '1' then
nextstate <= S2;
else nextstate <= S0;
end if;
when S2 => if taken = '1' then
nextstate <= S3;
else nextstate <= S1;
end if;
when S3 => if taken = '1' then
nextstate <= S4;
else nextstate <= S2;
end if;
when S4 => if taken = '1' then
nextstate <= S4;
else nextstate <= S3;
end if;
when others => nextstate <= S2;
end case;
end process;
-- output logic
predicttaken <= '1' when
((state = S4) or (state = S3) or
(state = S2 and back = '1'))
else '0';
end;
-------------------------------------------------------------------------A.15 Sketch the state transition diagram for the FSM described by the
following HDL code.
-------------------------------- VHDL CODE ------------------------------library IEEE; use IEEE.STD_LOGIC_1164 .all;
entity fsm2 is
port(clk, reset: in STD_LOGIC;
a, b: in STD_LOGIC;
y: out STD_LOGIC);
end;
architecture synth of fsm2 is
type statetype is (S0, S1, S2, S3);
signal state, nextstate: statetype;
begin
process(clk, reset) begin
if reset = '1' then state <= S0;
elsif clk'event and clk = '1' then
state <= nextstate;
end if;
end process;
process (state, a, b) begin
case state is
when S0 => if (a xor b) = '1' then
nextstate <= S1;
else nextstate <= S0;
end if;
when S1 => if (a and b) = '1' then
nextstate <= S2;
else nextstate <= S0;
end if;
when S2 => if (a or b) = '1' then

nextstate <= S3;

else nextstate <= S0;
end if;
when S3 => if (a or b) = '1' then
nextstate <= S3;
else nextstate <= S0;
end if;
end case;
end process;
y <= '1' when ((state = S1) or (state = S2))
else '0';
end