Inverter

Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:02:18 PM
Module:
inverter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
--------------------------------------------------------------(inv.sdc_line_1)
ext delay
+1000
1000 F
in
in port
1 6.1
0
+0
1000 F
g2/A
+0
1000
g2/Y
INVXL
1 3.5
93
+62
1062 R
out
out port
+0
1062 R
(inv.sdc_line_3)
ext delay
+1000
2062 R
--------------------------------------------------------------Timing slack : UNCONSTRAINED
Start-point : in
End-point
: out

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:02:18 PM
Module:
inverter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate Instances Area
Library
---------------------------------INVXL
1 6.653
tsmc18
---------------------------------total
1 6.653

Type

Instances

Area Area %

-------------------------------inverter
1 6.653 100.0
-------------------------------total
1 6.653 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:02:18 PM
Module:
inverter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------inverter
1
7
16

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:02:18 PM
Module:
inverter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'inverter'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------inverter
1
7
16
Design Rule Check
-----------------

Max_transition design rule: no violations.

Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module inverter(out, in);
input in;
output out;
wire in;
wire out;
INVXL g2(.A (in), .Y (out));
endmodule

Cadence Schematics, Copyright 1997-2006

in

A
INVXL

g2

out

Module:inverter, Page:1 of 1, Date:Mon Sep 14 12:02:57 2009

Buffer
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:13:15 PM
Module:
buffer
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-----------------------------------------------------------------(buffer.sdc_line_1)
ext delay
+1000
1000 R
in
in port
1 3.5
0
+0
1000 R
out
out port
+0
1000 R
(buffer.sdc_line_3)
ext delay
+1000
2000 R
-----------------------------------------------------------------Timing slack : UNCONSTRAINED
Start-point : in
End-point
: out

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:13:15 PM
Module:
buffer
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:13:15 PM
Module:
buffer
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells

Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------buffer
0
0
8

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:13:15 PM
Module:
buffer
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'buffer'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------buffer
0
0
8
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module buffer(out, in);
input in;
output out;
wire in;
wire out;
assign out = in;
endmodule

in

out

Module:buffer, Page:1 of 1, Date:Mon Sep 14 12:14:44 2009

Cadence Schematics, Copyright 1997-2006

Transmission Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:34:30 PM
Module:
trangate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-------------------------------------------------------------(tg.sdc_line_2)
ext delay
+1000
1000 R
cntrl1
in port
1 5.6
0
+0
1000 R
g8/AN
+0
1000
g8/Y
NAND2BXL
1 7.7 204 +165
1165 R
out1_tri/OE
+0
1166
out1_tri/Y
TBUFX1
1 6.4 103 +215
1381 F
out
out port
+0
1381 F
(tg.sdc_line_5)
ext delay
+1000
2381 F
-------------------------------------------------------------Timing slack : UNCONSTRAINED
Start-point : cntrl1
End-point
: out

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:34:30 PM
Module:
trangate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
-------------------------------------NAND2BXL
1 13.306
tsmc18
TBUFX1
1 23.285
tsmc18
-------------------------------------total
2 36.590

Type
Instances Area Area %
--------------------------------tristate
1 23.285
63.6
logic
1 13.306
36.4
--------------------------------total
2 36.590 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:34:30 PM
Module:
trangate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------trangate
2
37
41

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:34:30 PM
Module:
trangate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'trangate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
--------------------------------------

trangate

37

41

Design Rule Check

----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module trangate(out, in, cntrl1, cntrl2);
input in, cntrl1, cntrl2;
output out;
wire in, cntrl1, cntrl2;
wire out;
wire n_0;
TBUFX1 out1_tri(.A (in), .OE (n_0), .Y (out));
NAND2BXL g8(.AN (cntrl1), .B (cntrl2), .Y (n_0));
endmodule

cntrl2

Cadence Schematics, Copyright 1997-2006

in

AN

cntrl1
NAND2BXL

g8
Y

TBUFX1

out

Module:trangate, Page:1 of 1, Date:Mon Sep 14 12:34:56 2009

out1_tri
OE

AND Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:41:22 PM
Module:
andgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : y
End-point
: z

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:41:22 PM
Module:
andgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
-----------------------------------AND2X1
1 13.306
tsmc18
-----------------------------------total
1 13.306
Type Instances Area Area %
-----------------------------logic
1 13.306 100.0
-----------------------------total
1 13.306 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:41:22 PM
Module:
andgate
Technology libraries:
tsmc18 1.0

tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------andgate
1
13
25

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:41:22 PM
Module:
andgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'andgate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------andgate
1
13
25
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module andgate(z, x, y);
input x, y;
output z;
wire x, y;
wire z;
AND2X1 g13(.A (x), .B (y), .Y (z));
endmodule

Cadence Schematics, Copyright 1997-2006

x
AND2X1

g13

Module:andgate, Page:1 of 1, Date:Mon Sep 14 13:41:30 2009

NAND Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:55:50 PM
Module:
nandgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : x
End-point
: z

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:55:50 PM
Module:
nandgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances Area
Library
-----------------------------------NAND2XL
1 9.979
tsmc18
-----------------------------------total
1 9.979
Type Instances Area Area %
----------------------------logic
1 9.979 100.0
----------------------------total
1 9.979 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:55:50 PM
Module:
nandgate
Technology libraries:
tsmc18 1.0

tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------nandgate
1
10
25

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:55:50 PM
Module:
nandgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'nandgate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------nandgate
1
10
25
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module nandgate(z, x, y);
input x, y;
output z;
wire x, y;
wire z;
NAND2XL g6(.A (y), .B (x), .Y (z));
endmodule

Cadence Schematics, Copyright 1997-2006

y
Y

Module:nandgate, Page:1 of 1, Date:Mon Sep 14 13:55:59 2009

NAND2XL

g6

OR Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:46:01 PM
Module:
orgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : x
End-point
: z

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:46:01 PM
Module:
orgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate Instances
Area
Library
----------------------------------OR2X1
1 13.306
tsmc18
----------------------------------total
1 13.306
Type Instances Area Area %
-----------------------------logic
1 13.306 100.0
-----------------------------total
1 13.306 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:46:01 PM
Module:
orgate
Technology libraries:
tsmc18 1.0

tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------orgate
1
13
25

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 01:46:01 PM
Module:
orgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'orgate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------orgate
1
13
25
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module orgate(z, x, y);
input x, y;
output z;
wire x, y;
wire z;
OR2X1 g7(.A (y), .B (x), .Y (z));
endmodule

Cadence Schematics, Copyright 1997-2006

y
OR2X1

g7

Module:orgate, Page:1 of 1, Date:Mon Sep 14 13:46:10 2009

NOR Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:02:12 PM
Module:
norgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : y
End-point
: z

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:02:12 PM
Module:
norgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances Area
Library
----------------------------------NOR2XL
1 9.979
tsmc18
----------------------------------total
1 9.979
Type Instances Area Area %
----------------------------logic
1 9.979 100.0
----------------------------total
1 9.979 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:02:12 PM
Module:
norgate
Technology libraries:
tsmc18 1.0

tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------norgate
1
10
25

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:02:12 PM
Module:
norgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'norgate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------norgate
1
10
25
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module norgate(z, x, y);
input x, y;
output z;
wire x, y;
wire z;
NOR2XL g12(.A (x), .B (y), .Y (z));
endmodule

Cadence Schematics, Copyright 1997-2006

x
NOR2XL

g12

Module:norgate, Page:1 of 1, Date:Mon Sep 14 14:02:22 2009

XOR Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:12:26 PM
Module:
xorgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : y
End-point
: z

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:12:26 PM
Module:
xorgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
-----------------------------------XOR2XL
1 26.611
tsmc18
-----------------------------------total
1 26.611
Type Instances Area Area %
-----------------------------logic
1 26.611 100.0
-----------------------------total
1 26.611 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:12:26 PM
Module:
xorgate
Technology libraries:
tsmc18 1.0

tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------xorgate
1
27
25

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:12:26 PM
Module:
xorgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'xorgate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------xorgate
1
27
25
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module xorgate(z, x, y);
input x, y;
output z;
wire x, y;
wire z;
XOR2XL g36(.A (x), .B (y), .Y (z));
endmodule

Cadence Schematics, Copyright 1997-2006

XOR2XL

g36

Module:xorgate, Page:1 of 1, Date:Mon Sep 14 14:12:39 2009

XNOR Gate
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:16:27 PM
Module:
xnorgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : x
End-point
: z

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:16:27 PM
Module:
xnorgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
------------------------------------XNOR2XL
1 26.611
tsmc18
------------------------------------total
1 26.611
Type Instances Area Area %
-----------------------------logic
1 26.611 100.0
-----------------------------total
1 26.611 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:16:27 PM
Module:
xnorgate
Technology libraries:
tsmc18 1.0

tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------xnorgate
1
27
25

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 02:16:27 PM
Module:
xnorgate
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'xnorgate'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------xnorgate
1
27
25
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module xnorgate(z, x, y);
input x, y;
output z;
wire x, y;
wire z;
XNOR2XL g36(.A (y), .B (x), .Y (z));
endmodule

Cadence Schematics, Copyright 1997-2006

A
Y

Module:xnorgate, Page:1 of 1, Date:Mon Sep 14 14:16:35 2009

XNOR2XL

g36

D-Flip Flop
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 12:39:24 PM
Module:
d_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
----------------------------------------------------------------(clock clk)
launch
0 R
(dff.sdc_line_5)
ext delay
+1000
1000 F
din
in port
1 6.6
0
+0
1000 F
q_reg/D
DFFRHQXL
+0
1000
q_reg/CK
setup
100 +246
1246 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
10000 R
uncertainty
-1000
9000 R
----------------------------------------------------------------Cost Group
: 'clk' (path_group 'clk')
Timing slack :
7754ps
Start-point : din
End-point
: q_reg/D

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 12:39:24 PM
Module:
d_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
-------------------------------------DFFRHQXL
1 69.854
tsmc18
-------------------------------------total
1 69.854

Type
Instances Area Area %
----------------------------------sequential
1 69.854 100.0
----------------------------------total
1 69.854 100.0

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 12:39:24 PM
Module:
d_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Slack Endpoint Cost Group
--------------------------------+7754ps q_reg/D clk
Area
---Instance Cells Cell Area Net Area
-------------------------------------d_ff
1
70
16
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module d_ff(q, clk, n_rst, din);
input clk, n_rst, din;
output q;
wire clk, n_rst, din;
wire q;
DFFRHQXL q_reg(.RN (n_rst), .CK (clk), .D (din), .Q (q));
endmodule

Cadence Schematics, Copyright 1997-2006

n_rst

din

clk

RN

CK

Module:d_ff, Page:1 of 1, Date:Mon Sep 7 13:27:58 2009

DFFRHQXL

q_reg

SR-Flip Flop
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 01:30:19 PM
Module:
SR_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-----------------------------------------------------------------(clock clk)
launch
0 R
(srff.sdc_line_5)
ext delay
+1000
1000 F
s
in port
1 5.7
0
+0
1000 F
g98/A1N
+0
1000
g98/Y
AOI2BB1XL
1 5.6 118 +264
1264 F
tq_reg/D
DFFHQX1
+0
1264
tq_reg/CK
setup
100 +331
1595 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
10000 R
uncertainty
-1000
9000 R
-----------------------------------------------------------------Cost Group
: 'clk' (path_group 'clk')
Timing slack :
7405ps
Start-point : s
End-point
: tq_reg/D

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 01:30:19 PM
Module:
SR_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
--------------------------------------AOI2BB1XL
1 16.632
tsmc18
DFFHQX1
1 53.222
tsmc18
INVXL
1
6.653
tsmc18

--------------------------------------total
3 76.507
Type
Instances Area Area %
----------------------------------sequential
1 53.222
69.6
inverter
1 6.653
8.7
logic
1 16.632
21.7
----------------------------------total
3 76.507 100.0

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 01:30:19 PM
Module:
SR_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Slack Endpoint Cost Group
--------------------------------+7405ps tq_reg/D clk
Area
---Instance Cells Cell Area Net Area
-------------------------------------SR_ff
3
77
49
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module SR_ff(q, qbar, s, r, clk);
input s, r, clk;
output q, qbar;
wire s, r, clk;
wire q, qbar;
wire n_1;
DFFHQX1 tq_reg(.CK (clk), .D (n_1), .Q (q));
AOI2BB1XL g98(.A0N (q), .A1N (s), .B0 (r), .Y (n_1));
INVXL g99(.A (q), .Y (qbar));
endmodule

B0

A1N

A0N

Cadence Schematics, Copyright 1997-2006

clk

AOI2BB1XL

g98

CK

DFFHQX1

tq_reg

INVXL

qbar

Module:SR_ff, Page:1 of 1, Date:Mon Sep 7 13:30:35 2009

g99

JK-Flip Flop
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 01:03:56 PM
Module:
jk_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
-----------------------------------------------------------------(clock clk)
launch
0 R
(jkff.sdc_line_5)
ext delay
+1000
1000 F
j
in port
2 11.0
0
+0
1000 F
g91/B
+0
1000
g91/Y
NAND2X1
2 17.1 273 +162
1162 R
g89/S0
+0
1162
g89/Y
MX2X1
1 5.6 102 +260
1422 F
q_reg/SI
SDFFRHQX1
+0
1422
q_reg/CK
setup
100 +779
2201 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
10000 R
uncertainty
-1000
9000 R
-----------------------------------------------------------------Cost Group
: 'clk' (path_group 'clk')
Timing slack :
6799ps
Start-point : j
End-point
: q_reg/SI

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 01:03:56 PM
Module:
jk_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
----------------------------------------

DFFRHQX1
1
69.854
tsmc18
INVXL
1
6.653
tsmc18
MX2X1
1
26.611
tsmc18
NAND2X1
1
9.979
tsmc18
NOR2BXL
1
13.306
tsmc18
SDFFRHQX1
1
83.160
tsmc18
XNOR2X1
1
26.611
tsmc18
---------------------------------------total
7 236.174

Type
Instances
Area Area %
-----------------------------------sequential
2 153.014
64.8
inverter
1
6.653
2.8
logic
4 76.507
32.4
-----------------------------------total
7 236.174 100.0

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 07 2009 01:03:56 PM
Module:
jk_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Slack Endpoint Cost Group
--------------------------------+6799ps q_reg/SI clk
Area
---Instance Cells Cell Area Net Area
-------------------------------------jk_ff
7
236
102
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module jk_ff(q, qbar, clk, rst, j, k);
input clk, rst, j, k;
output q, qbar;
wire clk, rst, j, k;
wire q, qbar;
wire n_1, n_2, n_3, n_4, tq;
SDFFRHQX1 q_reg(.RN (rst), .CK (clk), .D (n_1), .SI (n_4), .SE (k),
.Q (q));
DFFRHQX1 tq_reg(.RN (rst), .CK (clk), .D (n_3), .Q (tq));
MX2X1 g89(.S0 (n_2), .B (q), .A (tq), .Y (n_4));
XNOR2X1 g90(.A (tq), .B (n_2), .Y (n_3));
NAND2X1 g91(.A (k), .B (j), .Y (n_2));
NOR2BXL g92(.AN (j), .B (k), .Y (n_1));
INVXL g93(.A (q), .Y (qbar));
endmodule

g91
Y

g90
Y

CK
tq_reg
Q

Cadence Schematics, Copyright 1997-2006

NAND2X1

XNOR2X1
RN

DFFRHQX1

S0

A
Y

SI

SDFFRHQX1

q_reg
Q

A INVXL

g93
Y

Module:jk_ff, Page:1 of 1, Date:Mon Sep 7 13:26:21 2009

mux2

g89

SE

CK

NOR2BXL

g92

RN

AN

rst

clk

qbar

Master-Slave JK-Flip Flop

Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 25 2009 01:54:24 PM
Module:
ms_jkff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack :
2475ps
Start-point : k
End-point
: ff1/q_reg/K

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 25 2009 01:54:24 PM
Module:
ms_jkff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
-------------------------------------DFFHQXL
1
53.222
tsmc18
INVXL
2
13.306
tsmc18
JKFFX1
1
69.854
tsmc18
-------------------------------------total
4 136.382

Type
Instances
Area Area %
-----------------------------------sequential
2 123.077
90.2
inverter
2 13.306
9.8
-----------------------------------total
4 136.382 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 25 2009 01:54:24 PM
Module:
ms_jkff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------ms_jkff
4
136
45
ff1
1
70
25
ff2
1
53
12

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 25 2009 01:54:24 PM
Module:
ms_jkff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Slack
Endpoint Cost Group
-----------------------------------+2475ps ff1/q_reg/K clk
Area
---Instance Cells Cell Area Net Area
-------------------------------------ms_jkff
4
136
45
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module jk_ff1(q, qbar, clk, j, k);
input clk, j, k;
output q, qbar;
wire clk, j, k;
wire q, qbar;
assign qbar = 1'b0;
JKFFX1 q_reg(.CK (clk), .J (j), .K (k), .Q (q), .QN ());
endmodule
module jk_ff1_11(q, qbar, clk, j, k);
input clk, j, k;
output q, qbar;
wire clk, j, k;
wire q, qbar;
assign qbar = 1'b0;
DFFHQXL q_reg(.CK (clk), .D (j), .Q (q));
endmodule
module ms_jkff(q, qbar, clk, j, k);
input clk, j, k;
output q, qbar;
wire clk, j, k;
wire q, qbar;
wire UNCONNECTED, UNCONNECTED0, n_0, q1;
jk_ff1 ff1(q1, UNCONNECTED, n_0, j, k);
jk_ff1_11 ff2(q, UNCONNECTED0, clk, q1, 1'b0);
INVXL g4(.A (q), .Y (qbar));
INVXL g5(.A (clk), .Y (n_0));
endmodule

A
INVXL

g5

Cadence Schematics, Copyright 1997-2006

clk

clk

ff1

ff1

qbar

clk

qbar

INVXL

Module:ms_jkff, Page:1 of 1, Date:Fri Sep 25 13:54:33 2009

ff2

ff2

g4

qbar

T-Flip Flop
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 10:52:57 AM
Module:
t_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
----------------------------------------------------------------(clock clk)
launch
0 R
(tff.sdc_line_6)
ext delay
+1000
1000 F
tin
in port
2 10.3
0
+0
1000 F
tq_reg/K
JKFFRXL
+0
1000
tq_reg/CK
setup
100 +280
1280 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clk)
capture
10000 R
uncertainty
-1000
9000 R
----------------------------------------------------------------Cost Group
: 'clk' (path_group 'clk')
Timing slack :
7720ps
Start-point : tin
End-point
: tq_reg/K

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 10:52:57 AM
Module:
t_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
------------------------------------JKFFRXL
1 86.486
tsmc18
------------------------------------total
1 86.486

Type
Instances Area Area %
----------------------------------sequential
1 86.486 100.0
----------------------------------total
1 86.486 100.0

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 10:52:57 AM
Module:
t_ff
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Slack Endpoint Cost Group
--------------------------------+7720ps tq_reg/K clk
Area
---Instance Cells Cell Area Net Area
-------------------------------------t_ff
1
86
29
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
module t_ff(q, qbar, clk, tin, rst);
input clk, tin, rst;
output q, qbar;
wire clk, tin, rst;
wire q, qbar;
JKFFRXL tq_reg(.RN (rst), .CK (clk), .J (tin), .K (tin), .Q (q), .QN
(qbar));
endmodule

Cadence Schematics, Copyright 1997-2006

rst

tin

clk

RN

CK

JKFFRXL

tq_reg

QN

qbar

Module:t_ff, Page:1 of 1, Date:Mon Sep 14 10:57:20 2009

Serial Adder
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:50:52 PM
Module:
serial_adder
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Pin

Type

Fanout Load Slew Delay Arrival

(fF) (ps) (ps)
(ps)
---------------------------------------------------------------(clock clock)
launch
0 R
count_reg[0]/CK
100
0 R
count_reg[0]/QN
EDFFTRX1
2 10.9 125 +579
579 F
g298/A
+0
579
g298/Y
NAND2X1
2 14.8 247 +167
746 R
g294/A
+0
746
g294/Y
XNOR2X1
1 5.3
98 +246
992 F
count_reg[2]/D
EDFFTRX1
+0
992
count_reg[2]/CK
setup
100 +764
1756 R
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - (clock clock)
capture
10000 R
uncertainty
-1000
9000 R
---------------------------------------------------------------Cost Group
: 'clock' (path_group 'clock')
Timing slack :
7244ps
Start-point : count_reg[0]/CK
End-point
: count_reg[2]/D

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:50:52 PM
Module:
serial_adder
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
----------------------------------------

DFFHQX1
1
53.222
tsmc18
DFFTRX1
1
56.549
tsmc18
EDFFTRX1
3 249.480
tsmc18
INVX1
1
6.653
tsmc18
NAND2X1
1
9.979
tsmc18
NOR2BX1
1
13.306
tsmc18
OAI21XL
1
13.306
tsmc18
OAI2BB1X1
2
33.264
tsmc18
OR4X2
1
19.958
tsmc18
XNOR2X1
2
53.222
tsmc18
XOR2X1
1
26.611
tsmc18
XOR3X2
1
59.875
tsmc18
---------------------------------------total
16 595.426

Type
Instances
Area Area %
-----------------------------------sequential
5 359.251
60.3
inverter
1
6.653
1.1
unresolved
3
0.000
0.0
logic
10 229.522
38.5
-----------------------------------total
19 595.426 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:50:52 PM
Module:
serial_adder
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance
Cells Cell Area Net Area
-----------------------------------------serial_adder
16
595
468

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 14 2009 12:50:52 PM
Module:
serial_adder
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow

Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'serial_adder'.
Slack
Endpoint
Cost Group
--------------------------------------+7244ps count_reg[2]/D clock
Area
---Instance
Cells Cell Area Net Area
-----------------------------------------serial_adder
16
595
468
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module serial_adder(A, B, reset, clock, sum);
input [7:0] A, B;
input reset, clock;
output [7:0] sum;
wire [7:0] A, B;
wire reset, clock;
wire [7:0] sum;
wire UNCONNECTED, UNCONNECTED0, UNCONNECTED1, UNCONNECTED2,
UNCONNECTED3, UNCONNECTED4, UNCONNECTED5, UNCONNECTED6;
wire \count[0] , \count[1] , \count[2] , \count[3] , n_0, n_1, n_2,
n_3;
wire n_4, n_5, n_6, n_7, n_27, n_28, n_43, n_44;
wire n_45, \qa[0] , \qa[1] , \qa[2] , \qa[3] , \qa[4] , \qa[5] ,
\qa[6] ;
wire \qa[7] , \qb[0] , \qb[1] , \qb[2] , \qb[3] , \qb[4] , \qb[5] ,
\qb[6] ;
wire \qb[7] , run, y;
shiftrne shift_A(A, reset, 1'b1, 1'b0, clock, {\qa[7] , \qa[6] ,
\qa[5] , \qa[4] , \qa[3] , \qa[2] , \qa[1] , \qa[0] });
shiftrne shift_B(B, reset, 1'b1, 1'b0, clock, {\qb[7] , \qb[6] ,
\qb[5] , \qb[4] , \qb[3] , \qb[2] , \qb[1] , \qb[0] });
shiftrne shift_sum(8'b00000000, reset, run, n_27, clock, sum);
XOR3X2 g222(.A (\qb[0] ), .B (\qa[0] ), .C (y), .Y (n_27));

OR4X2 g223(.A (\count[2] ), .B (\count[1] ), .C (\count[0] ), .D

(\count[3] ), .Y (run));
DFFHQX1 \count_reg[3] (.CK (clock), .D (n_45), .Q (\count[3] ));
EDFFTRX1 \count_reg[2] (.CK (clock), .D (n_5), .E (run), .RN (n_0),
.Q (\count[2] ), .QN (n_43));
EDFFTRX1 \count_reg[1] (.CK (clock), .D (n_2), .E (run), .RN (n_0),
.Q (\count[1] ), .QN (n_44));
DFFTRX1 y_reg(.CK (clock), .D (n_6), .RN (n_0), .Q (y), .QN ());
EDFFTRX1 \count_reg[0] (.CK (clock), .D (n_28), .E (run), .RN (n_0),
.Q (\count[0] ), .QN (n_28));
XOR2X1 g292(.A (n_4), .B (\count[3] ), .Y (n_7));
OAI2BB1X1 g293(.A0N (\qa[0] ), .A1N (y), .B0 (n_3), .Y (n_6));
XNOR2X1 g294(.A (n_1), .B (\count[2] ), .Y (n_5));
NOR2BX1 g295(.AN (n_43), .B (n_1), .Y (n_4));
OAI21XL g296(.A0 (y), .A1 (\qa[0] ), .B0 (\qb[0] ), .Y (n_3));
XNOR2X1 g297(.A (\count[0] ), .B (\count[1] ), .Y (n_2));
NAND2X1 g298(.A (n_28), .B (n_44), .Y (n_1));
INVX1 g299(.A (reset), .Y (n_0));
OAI2BB1X1 g3(.A0N (run), .A1N (n_7), .B0 (n_0), .Y (n_45));
endmodule

X4

X2
X5

shift_B X..
[0:7]
X..[0:7]

X2
X5

shift_A X.. [0:7]

X..[0:7]

X3 shift_B

X4

X3 shift_A

g299
.INVX1
.

E
CK
count_reg[0]Q
D
EDFFTRX1
..
..

Cadence Schematics, Copyright 1997-2006

B[7:0] [0:7]

A[7:0] [0:7]

clock
reset
E
CK
count_reg[1]Q
A g297
Y
D
BXNOR2X1
EDFFTRX1
..
..

[0:7]
SPLIT

[0:7]
SPLIT
.. g296
.. OAI21XL
Y
..

.. g295
Y
A g292
BNOR2BX1 XOR2X1
Y
B

..
.. g293
.. OAI2BB1X1
Y
D
..
..

Q
DFFTRX1..

y_reg

..count_reg[3]
.. g3
Q
.. OAI2BB1X1
Y
D DFFHQX1
..

A g222
BXOR3X2
Y
C

[0:7]
SPLIT

[0:7]
SPLIT

[0:7]
SPLIT

[0:7]
SPLIT

A
X2
Bg223
Y X3 shift_sum X5
COR4X2
D
X4 shift_sumX..
[0:7]
[0:7]
SPLIT
X..
[0:7]

[0:7]

Module:serial_adder, Page:1 of 1, Date:Mon Sep 14 12:51:36 2009

E
A g298
..count_reg[2]Q
Y A g294
BNAND2X1 XNOR2X1
Y
D
B
EDFFTRX1
..
..

sum[7:0]

Parallel Adder
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 11:56:44 AM
Module:
adder4
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack : UNCONSTRAINED
Start-point : stage3/X5
End-point
: carryout

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 11:56:44 AM
Module:
adder4
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Type
Instances Area Area %
---------------------------------unresolved
4 0.000
0.0
---------------------------------total
4 0.000
0.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 11:56:44 AM
Module:
adder4
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0

typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance Cells Cell Area Net Area
-------------------------------------adder4
0
0
140

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 11:56:44 AM
Module:
adder4
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'adder4'.
No paths found.
Area
---Instance Cells Cell Area Net Area
-------------------------------------adder4
0
0
140
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module adder4(carryin, x, y, sum, carryout);

input carryin;
input [3:0] x, y;
output [3:0] sum;
output carryout;
wire carryin;
wire [3:0] x, y;
wire [3:0] sum;
wire carryout;
wire c1, c2, c3;
fulladd stage0(carryin, x[0], y[0], sum[0], c1);
fulladd stage1(c1, x[1], y[1], sum[1], c2);
fulladd stage2(c2, x[2], y[2], sum[2], c3);
fulladd stage3(c3, x[3], y[3], sum[3], carryout);
endmodule

X1
stage3
X2

X3
stage3

X4
[0:3][0:3]

X5

BIND

sum[3:0]

carryout
X1
stage2
X2

X3
stage2

X4

X5

X1
stage1
X2

X3
stage1

X4

X5

carryin
X1
stage0
X2

X3
stage0

X4

X5

x[3:0]

[0:3]

y[3:0]

[0:3]

[0:3]
SPLIT

[0:3]
SPLIT

Module:adder4, Page:1 of 1, Date:Thu Sep 24 11:58:23 2009

Cadence Schematics, Copyright 1997-2006

Synchronous Counter
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:10:34 PM
Module:
counter_behav
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack :
7466ps
Start-point : count_reg[1]/CK
End-point
: count_reg[3]/D

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:10:34 PM
Module:
counter_behav
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
-------------------------------------ADDHXL
2
73.181
tsmc18
DFFTRX1
4 226.195
tsmc18
INVX1
1
6.653
tsmc18
XOR2X1
1
26.611
tsmc18
-------------------------------------total
8 332.640

Type
Instances
Area Area %
-----------------------------------sequential
4 226.195
68.0
inverter
1
6.653
2.0
logic
3 99.792
30.0
-----------------------------------total
8 332.640 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:10:34 PM
Module:
counter_behav
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance
Cells Cell Area Net Area
------------------------------------------counter_behav
8
333
127

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:10:34 PM
Module:
counter_behav
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Slack
Endpoint
Cost Group
--------------------------------------+7466ps count_reg[3]/D clk
Area
---Instance
Cells Cell Area Net Area
------------------------------------------counter_behav
8
333
127
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module counter_behav(count, reset, clk);
input reset, clk;
output [3:0] count;
wire reset, clk;
wire [3:0] count;
wire n_1, n_2, n_3, n_4, n_5, n_6, n_12;
DFFTRX1 \count_reg[3] (.CK (clk), .D (n_6), .RN (n_5), .Q (count[3]),
.QN ());
XOR2X1 g70(.A (n_3), .B (count[3]), .Y (n_6));
DFFTRX1 \count_reg[2] (.CK (clk), .D (n_4), .RN (n_5), .Q (count[2]),
.QN ());
ADDHXL g71(.A (n_1), .B (count[2]), .S (n_4), .CO (n_3));
DFFTRX1 \count_reg[1] (.CK (clk), .D (n_2), .RN (n_5), .Q (count[1]),
.QN ());
DFFTRX1 \count_reg[0] (.CK (clk), .D (n_12), .RN (n_5), .Q
(count[0]), .QN (n_12));
ADDHXL g73(.A (count[0]), .B (count[1]), .S (n_2), .CO (n_1));
INVX1 g76(.A (reset), .Y (n_5));
endmodule

RN

A INVX1 Y

RN

CK

g76

CK

DFFTRX1

count_reg[1]

DFFTRX1

count_reg[0]

Cadence Schematics, Copyright 1997-2006

reset

clk

QN

QN

RN

CK

DFFTRX1

count_reg[2]

g73

g73

QN

CO

CO
B

A
Y
XOR2X1

g70

RN

DFFTRX1

count_reg[3]

QN

Q
BIND

[0:3][0:3]

Module:counter_behav, Page:1 of 1, Date:Thu Sep 24 12:10:56 2009

g71

g71

CK

count[3:0]

Ripple Counter
Timing Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:18:14 PM
Module:
ripple_counter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing slack :
7720ps
Start-point : toggle
End-point
: count_reg[0]/K

Gates Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:18:14 PM
Module:
ripple_counter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Gate
Instances
Area
Library
--------------------------------------INVXL
2
13.306
tsmc18
JKFFRXL
1
86.486
tsmc18
SDFFNRX1
3 269.438
tsmc18
--------------------------------------total
6 369.230

Type
Instances
Area Area %
-----------------------------------sequential
4 355.925
96.4
inverter
2 13.306
3.6
-----------------------------------total
6 369.230 100.0

Area Report:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:18:14 PM
Module:
ripple_counter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Instance
Cells Cell Area Net Area
-------------------------------------------ripple_counter
6
369
57

Summary:
============================================================
Generated by:
Encounter(R) RTL Compiler v08.10-s126_1
Generated on:
Sep 24 2009 12:18:14 PM
Module:
ripple_counter
Technology libraries:
tsmc18 1.0
tsmc18_1 1.0
typical 1.13
physical_cells
Operating conditions:
slow
Interconnect mode:
ple
Area mode:
physical library
============================================================
Timing
-----Warning : Possible timing problems have been detected in this design. [TIM-11]
: The design is 'ripple_counter'.
Slack
Endpoint
Cost Group
--------------------------------------+7720ps count_reg[0]/K clock
Area
---Instance
Cells Cell Area Net Area
-------------------------------------------ripple_counter
6
369
57
Design Rule Check
----------------Max_transition design rule: no violations.
Max_capacitance design rule: no violations.

Netlist:
// Generated by Cadence Encounter(R) RTL Compiler v08.10-s126_1
module ripple_counter(clock, toggle, reset, count);
input clock, toggle, reset;
output [3:0] count;
wire clock, toggle, reset;
wire [3:0] count;
wire n_0, n_1;
SDFFNRX1 \count_reg[1] (.RN (n_1), .CKN (count[0]), .D (toggle), .SI
(n_0), .SE (count[1]), .Q (count[1]), .QN ());
SDFFNRX1 \count_reg[2] (.RN (n_1), .CKN (count[1]), .D (toggle), .SI
(n_0), .SE (count[2]), .Q (count[2]), .QN ());
SDFFNRX1 \count_reg[3] (.RN (n_1), .CKN (count[2]), .D (toggle), .SI
(n_0), .SE (count[3]), .Q (count[3]), .QN ());
JKFFRXL \count_reg[0] (.RN (n_1), .CK (clock), .J (toggle), .K
(toggle), .Q (count[0]), .QN ());
INVXL g29(.A (toggle), .Y (n_0));
INVXL g28(.A (reset), .Y (n_1));
endmodule

g29

JKFFRXL

count_reg[0]

A INVXL Y

K
RN

g28

A INVXL Y

CK

Cadence Schematics, Copyright 1997-2006

reset

clock

toggle

QN

SI

SDFFNRX1

count_reg[2]

QN

SI

SE

RN

CKN

SDFFNRX1

count_reg[3]

QN

Q
BIND

[0:3][0:3]

Module:ripple_counter, Page:1 of 1, Date:Thu Sep 24 12:18:55 2009

SE

SI

CKN

SE

QN

RN

SDFFNRX1

count_reg[1]

RN

CKN

count[3:0]