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United States Patent (10) Patent No.: US 8,520,412 B2
United States Patent (10) Patent No.: US 8,520,412 B2
US 8,520,412 B2
Aug. 27, 2013
363/2103, 131, 120 See application ?le for complete search history.
(56) References Cited
6,002; 14 A
6,198,198 B1
2003/0071586 A1
1 2/ 1999 Rjbarich
3/2001 Fujimura et a1.
4/2003 Lin et a1.
ggl?umoto
2009/0243505 A1 100009 Kimura
2011/0012527 A1
JP
JP
JP
10 285942
2002 319499
10/1998
10/2002
Us 2011/0299310 A1
Dec~ 8: 2011
JP _ 2005 5059 H2005 Primary Examzner * Douglas W OWens Assistant Examiner * Jonathan Cooper
(74) Attorney,
Agent,
or
Firm * Oblon,
Spivak,
A synchronous operating system for operating a plurality of discharge tube lighting apparatuses at the same frequency and
same phase includes (1) an oscillator of a triangular Wave
signal Whose inclination for charging a capacitor C2 and
inclination for discharging the same are the same, (2) a signal generation part to generate, in a period shorter than a half
period of the triangular Wave signal, a ?rst drive signal having
Int CL
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(200601)
363/21 02_ 363/21 03_ 363/131_
a pulse Width corresponding to a load current, and (3) a signal generation part of a second drive signal having a pulse Width substantially equal to that of the ?rst drive signal and a phase
difference of about 180 degrees With respect to the same.
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US 8,520,412 B2
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US. Patent
Sheet 10 0f 15
US 8,520,412 B2
FIG. 10
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RESONANT CIRCUIT
DISCHARGE TUBE
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Sheet 11 0115
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US 8,520,412 B2
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US. Patent
Sheet 13 0f 15
US 8,520,412 B2
FIG. 13
CHARGE WITH H DISCHARGE WITH ll INVERTED WAVEFORM 0F FBOUT
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DRVZ
US. Patent
Sheet 14 or 15
US 8,520,412 B2
FIG. I4
CHARGE WITH II
DISCHARGE WITH I1
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US. Patent
Sheet 15 0f 15
US 8,520,412 B2
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US 8,520,412 B2
1
SYNCHRONOUS OPERATING SYSTEM FOR DISCHARGE TUBE LIGHTING
2
determination circuit 11 provides the oscillator 12 With a constant current that is optionally set by the constant current determination resistor R1. According to the constant current from the constant current determination circuit 11, the oscil
This application is a continuation of US. application Ser. No. 12/302,814 ?led Nov. 28, 2008, the entire content of Which is incorporated herein by reference, and Which is the National Stage of PCT/JP07/ 67609 ?led Sep. 10, 2007 and claims the bene?t of priority under 35 U.S.C. 119 to Japanese Application No. 2006-274186 ?led Oct. 5, 2006. The entire contents of Japanese Application No. 2006-274186 are incor
10
R3 and R4, to detect a current passed to the discharge tube 3 and output a voltage proportional to the detected current to an
15 through a feedback terminal FB of the controller 1. The error ampli?er 15 ampli?ers an error voltage FBOUT betWeen the voltage from the tube current detection circuit 5
grated circuit.
BACKGROUND TECHNOLOGY
30
A discharge tube, in particular, a cold cathode ?uorescent lamp (CCFL) causes, When a passing current becomes imbal
anced to bias a mercury distribution in the discharge tube, a
(as depicted by +) of the PWM comparator 16. The PWM comparator 16 generates a pulse signal that is high level if the
error voltage FBOUT from the error ampli?er 15 input to the non-inverting terminal is equal to or higher than the saWtooth Waveform voltage from the terminal CF input to an inverting
brightness gradient, a life reduction of the discharge tube, a change in emission color, and the like. Accordingly, an abso lute requirement for the discharge tube lighting apparatus is to supply a positive-negative symmetrical current to the dis
35
charge tube.
FIG. 1 is a circuit diagram illustrating a con?guration of a
related discharge tube lighting apparatus. FIG. 2 is a timing chart illustrating signals at various parts of the related dis
40
The frequency divider 13 divides the frequency of the pulse signal from the oscillator 12 and provides the NAND gate 1711 With a frequency-divided pulse signal Q and the AND gate 17b With a pulse signal (having a predetermined dead time
FET Qp1 and n-type FET Qn1 and the ground GND, there is
connected a series circuit consisting of a capacitor C3 and a primary Winding P of a transformer T. Both ends of a second ary Winding S of the transformer T are connected to a series circuit having a reactor Lr and a capacitor C4. A source of the p-type FET Qp1 receives the DC poWer source Vin and a gate of the p-type FET Qp1 is connected to a terminal DRV1 of a controller (IC) 1. A gate of the n-type FET Qn1 is connected to a terminal DRV2 of the IC 1.
The controller IC1 has a start circuit 10, a constant current
tion of the inverted frequency-divided pulse signal from the frequency divider 13 and the signal from the PWM compara
tor 16 and outputs a drive signal through the driver 18b and terminal DRV2 to the n-type FET Qn1. From time t1 to t2, for example, the output from the PWM
55
determination circuit 11, an oscillator 12, a frequency divider 13, an error ampli?er 15, a PWM comparator 16, a NAND gate 17a, an AND gate 17b, and drivers 18a and 18b. The constant current determination circuit 11 is connected
through a terminal RF to an end of a constant current deter
60
the output from the PWM comparator 16 is high level, the inverted output from the frequency divider 13 is high level, and the output from the AND gate 17b is high level. As results,
the terminal DRV2 provides a high-level output to turn on the
n-type FET Qn1. Namely, the drive signals are formed by combining the
65
The start circuit 10 receives poWer from the DC poWer source Vin to generate a predetermined voltage REG and supply the same to various internal parts. The constant current
outputs from the frequency divider 13 and the output from the
PWM comparator 16 and are alternately sent to the terminals DRV1 and DRV2 in synchronization With the clock CK With
US 8,520,412 B2
3
a fall period of the sawtooth oscillating Waveform serving as a dead time. Through the above-mentioned operation, the controller 1 alternately turns on/off the p-type FET Qpl and
4
charge tube, and a second signal generation part to generate a
n-type FET Qnl at the frequency of the saWtooth oscillating Waveform. This supplies poWer to the discharge tube 3 and
controls a current passing through the discharge tube 3 at a
predetermined value.
A knoWn related art is, for example, US. Pat. No. 5,615,
093. DISCLOSURE OF INVENTION
plurality of sWitching elements and pass a current through the discharge tube in a direction opposite to the current passed by the ?rst drive signal.
However, for a liquid crystal display unit such as a liquid crystal TV, a uniformity of screen brightness is important. In a liquid crystal display unit employing a panel With a plurality of discharge tubes, screen ?ickering occurs if the discharge
tubes are lighted at different frequencies or different phases. It is necessary to supply a positive-negative symmetrical cur
secondary Windings of a transformer, an output thereof being connected to the discharge tube, a plurality of sWitching ele
ments of bridge con?guration connected to both ends of a DC poWer source, to pass a current through the primary Winding of the transformer and the capacitor, an oscillator to generate a triangular Wave signal Whose inclination for charging an oscillator capacitor and inclination for discharging the same
are the same and Which is used to turn on/ off the plurality of
rent to each discharge tube, and in addition, light the dis charge tubes in the same phase.
20
of sWitching elements and pass a current through the dis charge tube, and a second signal generation part to generate a
30
The present invention provides a synchronous operating system for discharge tube lighting apparatuses, a discharge
tube lighting apparatus, and a semiconductor integrated cir
35
40
plurality of sWitching elements and pass a current through the discharge tube in a direction opposite to the current passed by the ?rst drive signal. The present invention provides a semiconductor integrated circuit for controlling a plurality of sWitching elements of bridge con?guration to supply poWer to a discharge tube, comprising an oscillator to generate a triangular Wave signal Whose inclination for charging an oscillator capacitor and
inclination for discharging the same are the same and Which is
present invention provides a synchronous operating system for a plurality of discharge tube lighting apparatuses each
converting a direct current into a positive-negative symmetri
45
cal alternating current, oscillator capacitors of the plurality of discharge tube lighting apparatuses being commonly con nected, AC poWer from the plurality of discharge tube light ing apparatuses being supplied to a plurality of discharge tubes. Each of the plurality of discharge tube lighting appa
ratuses comprises a resonant circuit including a capacitor connected to at least one of primary and secondary Windings of a transformer, an output thereof being connected to the
used to turn on/ off the plurality of sWitching elements, a ?rst signal generation part to generate, in a period shorter than a half period of the triangular Wave signal, a ?rst drive signal having a pulse Width corresponding to a current passing through the discharge tube, to drive a ?rst group of one or
second signal generation part to generate a second drive sig nal having a pulse Width substantially equal to that of the ?rst drive signal and a phase difference of about 180 degrees With
respect to the ?rst drive signal, to drive a second group of one
55
or more sWitching elements among the plurality of sWitching elements and pass a current through the discharge tube in a
signal.
BRIEF DESCRIPTION OF DRAWINGS
60
US 8,520,412 B2
5
FIG. 4 is a timing chart illustrating signals at various parts
6
circuit 10 is the same as that illustrated in FIG. 15. The constant current determination circuit 11a is connected through a terminal RF to an end of a constant current deter
constant current that is optionally set by the constant current determination resistor R2. The oscillator 12a charges and discharges the capacitor C2 With the constant current from the constant current determination circuit 11a, generates a trian gular Wave signal as illustrated in FIG. 4 (illustrated in FIG. 4 is a charge/discharge voltage of the capacitor C2 at the ter
FIG. 9 is a timing chart illustrating signals at various parts of a discharge tube lighting apparatus according to a modi? cation of Embodiment 3 of the present invention. FIG. 10 is a circuit diagram illustrating a con?guration of a
received from the error ampli?er 15 through the resistor R4 With respect to a reference voltage E2 at a non-inverting
FIG. 13 is a timing chart illustrating signals at various parts of a discharge tube lighting apparatus according to Embodi ment 5 of the present invention. FIG. 14 is a timing chart illustrating signals at various parts of a discharge tube lighting apparatus according to Embodi ment 6 of the present invention.
FIG. 15 is a circuit diagram illustrating a con?guration of a
the triangular Wave signal and thereby the subtraction circuit 19 outputs the inverted voltage representing an inverted
Waveform of the error voltage FBOUT to an inverting termi
reference voltage E2 is expressed as E2:(VL+VH)/2 and is a midpoint potential betWeen the upper limit value VH and loWer limit value VL of the triangular Wave signal CF. The PWM comparator 16a generates a pulse signal that is
high level When the error voltage FBOUT input to the non inverting terminal from the error ampli?er 15 is equal to or
40
inverting terminal from the terminal CF and loW level When the error voltage FBOUT is loWer than the triangular Wave
signal voltage and outputs the pulse signal to the NAND gate
45
Embodiment 1
discharge tube lighting apparatus according to Embodiment 1 of the present invention. The discharge tube lighting appara
tus illustrated in FIG. 3 differs from the discharge tube light
50
170. The PWM comparator 16b generates a pulse signal that is high level When the triangular Wave signal voltage input to the non-inverting terminal from the terminal CF is equal to or higher than the inverted Waveform voltage of the error voltage FBOUT input to the inverting terminal from the subtraction circuit 19 and loW level When the triangular Wave signal voltage is loWer than the inverted Waveform voltage of the error voltage FBOUT and outputs the pulse signal to the logic circuit 17d. The NAND gate 170 operates the NAND function of the clock from the oscillator 12a and the signal from the PWM comparator 16a and outputs a ?rst drive signal through the
driver 18a and a terminal DRV1 to a p-type FET Qpl. The
explained here.
BetWeen a reactor Lr and a discharge tube 3, there is con
nected a capacitor C10. This example employs both a capaci tor C3 and the capacitor C10. For example, only one of the capacitors C3 and C10 may be employed. The controller 111 corresponds to the semiconductor inte
grated circuit of the present invention and has a start circuit
10, a constant current determination circuit 1111, an oscillator
logic circuit 17d operates the AND function of an inverted signal of the clock from the oscillator 12a and the signal from the PWM comparator 16b and outputs a second drive signal through the driver 18b and a terminal DRV2 to an n-type FET
60
Qnl.
The PWM comparator 16a, NAND gate 170, and driver 18a correspond to the ?rst signal generation part of the
present invention that generates, in a period shorter than a half
1211, an error ampli?er 15, a subtraction circuit 19, PWM comparators 16a and 16b, a NAND gate 170, a logic circuit 17d, and drivers 18a and 18b. A con?guration of the start
through the discharge tube 3, to drive the p-type FET Qpl and
pass a current through the discharge tube 3. The subtraction
US 8,520,412 B2
7
circuit 19, PWM comparator 16b, logic circuit 17d, and driver 18b correspond to the second signal generation part of the present invention that generates the second drive signal hav ing a pulse Width substantially equal to that of the ?rst drive signal and a phase difference of about 180 degrees With
respect to the ?rst drive signal, to drive the n-type FET Qnl
and pass a current through the discharge tube 3 in a direction
8
ondary side of the transformer T, a current passes through a
opposite to the current passed by the ?rst drive signal. Operation of the discharge tube lighting apparatus of Embodiment 1 having such a con?guration Will be explained
With reference to the timing chart illustrated in FIG. 4. The constant current I1 optionally set by the constant cur rent determination resistor R2 makes the oscillator 12a
synchronized With the triangular Wave signal and is, for example, high level during a rise period and loW level during
a fall period.
discharge tube lighting apparatus according to Embodiment 2 of the present invention. The discharge tube lighting appara
tus illustrated in FIG. 5 is an example of a discharge tube
Only When the clock CK from the oscillator 12a is high level and the signal from the PWM comparator 16a is high level, the NAND gate 170 outputs a loW-level pulse signal to
the p-type FET Qpl to turn on the same. Namely, Within a rise
25
FET Qp2 and loW-side n-type FET Qn2. BetWeen a connec tion point of a p-type FET Qpl and an n-type FET Qnl and a
35
path extending along Vin, Qpl, C3, P, and GND, and on the
secondary side of the transformer T, a current passes through
40
(as depicted by ) of the PWM comparator 160 With an inverted voltage C2 formed by inverting a triangular Wave
signal CF With respect to a reference voltage E2 to a non
On the other hand, the subtraction circuit 19 provides the inverting terminal of the PWM comparator 16b With an inverted Waveform of the error voltage FBOUT formed by inverting the error voltage FBOUT from the error ampli?er 15 With respect to the midpoint potential betWeen the upper limit value and loWer limit value of the triangular Wave signal. Only When the inverted output of the clock CK (loW level) from the oscillator 12a is high level and the signal from the PWM comparator 16b is high level, the logic circuit 17d outputs a high-level pulse signal to the n-type FET Qnl to turn
on the same.
midpoint potential betWeen the upper limit value VH and loWer limit value VL of the triangular Wave signal. The PWM comparator 160 generates a pulse signal that is
high level When an error voltage FBOUT inputted to a non
15 is equal to or higher than the inverted voltage C2 input to the inverting terminal from the subtraction circuit 19a and loW level When the error voltage FBOUT is loWer than the inverted voltage C2 and outputs the pulse signal to a logic
circuit 17e. The logic circuit 17e operates a NAND of an inversion of a clock CK from an oscillator 12a and the signal
Namely, in a fall period of the triangular Wave signal CF (for example, time t3 to t5, or t7 to t9 With the clock CK being loW level), When the triangular Wave signal CF is equal to or higher than the inverted Waveform voltage of the error voltage FBOUT (a period in Which the signal from the PWM com
55
period of the triangular Wave signal CF, a high-level pulse signal is outputted to the p-type FET Qp2 and n-type FET
Qn2, to turn on the n-type FET Qn2. In this period, a current
path extending along P, C3, Qnl, and GND, and on the sec