Lab Record Format

LMV 108 VLSI Design Lab Va%"a&ulam Experiment No:1 Date: 16 09 2011
Department of Electronics and Communication Engineering Viswa !ot"i College of Engineering and #ec"nolog!$
ADDERS AIM
Design and implement a)Half adder b)Full adder c)Ripple carry adder using Verilog code.
SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog ). *t+,a(e CIRCUIT DIAGRAM a)Half adder
b)Full adder
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LMV 108 VLSI Design Lab Va%"a&ulam
c)Ripple carry adder
TRUTH TABLE a)Half adder
b)Full adder
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c)Ripple carry adder
ROGRAM !i) Half Adder
De"i#$ M%dule module H-(s.cout.a.b)/ input a.b/ output reg s.cout/ al,ays 0(a.b) begin s1a2b/ cout1a3b/ end endmodule Te"& Be$c' 4timescale 1ns51ps
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4include 6H-.(6 module 7a8tb/ reg a.b/ ,ire s.cout/ integer i/ H- H(s.cout.a.b)/ initial begin 9dumpfile (67adump.(cd6)/ 9dump(ars (#.7a8tb.H)/ end initial begin :a.b;1#<b""/ for(i11/i=)/i1i>1) ?1" :a.b;1i/ end initial ?1"" 9finis7/ endmodule
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!ii)
Full Adder
De"i#$ M%dule module F-(s.cout.a.b.cin)/ input a.b.cin/ output reg s.cout/ al,ays 0(a.b.cin) :cout.s;1a>b>cin/ ndmodule Te"& Be$c' 4timescale 1ns51ps 4include 6F-.(6 module fa8tb/ reg a.b.cin/ ,ire s.cout/ integer i/ F- F(s.cout.a.b.cin)/ initial begin 9dumpfile (6fadump.(cd6)/ 9dump(ars (#.fa8tb.F)/ end
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initial begin :a.b.cin;1&<b"""/ for(i11/i=@/i1i>1) ?1" :a.b.cin;1i/ nd initial ?1"" 9finis7/ ndmodule !iii) ( Bi& Ripple Carry Adder De"i#$ M%dule module rca(s.cout.a.b.cin)/ input A&B"Ca.b/ input cin/ output reg A&B"Cs/ output reg cout/ al,ays0(a.b.cin) begin :cout.s;1a>b>cin/ end endmodule
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Te"& Be$c' 4timescale 1ns51ps 4include 6rca.(6 module rca8tb/ reg A"B&Ca.b/ reg cin/ ,ire A"B&Cs/ ,ire cout/ rca r(s.cout.a.b.cin)/ initial begin 9dumpfile (6rcadump.(cd6)/ 9dump(ars (#.rca8tb.r)/ end initial begin a1)<b""1"/ b1)<b"1""/ cin11<b1/ ?#" a1)<b""11/ b1)<b""1"/
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cin11<b"/ ?#" a1)<b"11"/ b1)<b"1""/ cin11<b"/ end initial ?1"" 9finis7/ endmodule OBSER)ATIO* !i)Half Adder
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!ii) Full Adder
!iii)( Bi& Ripple Carry Adder
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RESULT - Half -dder. Full -dder and ) Dit Ripple Earry -dder 7as been Designed and 'mplemented and ,a(eforms 7a(e been obtained.
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LMV 108 VLSI Design Lab LMV 108 VLSI Design Lab Va%"a&ulam
Experiment No: 2 Date: 14 09 2011
Department of Electronics and Communication Engineering Department Electronics Communication Engineering Viswaof !ot"i College and of Engineering and #ec"nolog!$ Viswa !ot"i College of Engineering and #ec"nolog!$ Va%"a&ulam
D FLI FLO
AIM Design and implement D flipflop using Verilog code.
SOFTWARES USED +, ModelSim (Versions) -, Xilin$ (Versions) ., '(erilog (, *t+,a(e CIRCUIT DIAGRAM
TRUTH TABLE
ROGRAM De"i#$ /%dule module dff1(F".F1.d.cl+.reset)/ input d.cl+.reset/

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output reg F".F1/ al,ays 0(posedge cl+) begin if (reset111<b") begin F"1d/ F11(GF")/ end else begin F"11<b"/ F111<b"/ end end endmodule Te"& be$c' 4timescale 1ns51ps 4include 6dff.(6 module dfftb1/ reg d8t/ reg cl+8t/ reg reset8t/ ,ire F"8t.F18t/ integer i/ dff1 d1(F"8t.F18t.d8t.cl+8t.reset8t)/ initial begin 9dumpfile(6dffdump.(cd6)/ 9dump(ars(#.dfftb1.d1)/
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end initial begin reset8t11<b"/ cl+8t11<b1/ d8t11<b1/ ?#" d8t11<b"/ ?#" d8t11<b1/ end al,ays begin ?H cl+8t=1Gcl+8t/ end initial ?1"" 9finis7/ endmodule
OBSER)ATIO*
RESULT D flipflop 7as been designed and implemented and ,a(eforms 7as been obtained.
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01 FLI FLO
AIM Design and implement IJ flipflop using Verilog code.
SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog ). *t+,a(e
CIRCUIT DIAGRAM
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TRUTH TABLE
ROGRAM De"i#$ /%dule module K+ff1(F".F1.K.+.cl+.reset)/ input K.+.cl+.reset/ output reg F"/ output reg F1/ al,ays 0(negedge cl+) begin if (reset111<b") begin case(:K.+;) #<b""BF"1F"/ #<b"1BF"11<b"/ #<b1"BF"11<b1/ defaultBF"1(GF")/ endcase F11GF"/ end else begin
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F"11<b"/ F111<b"/ end end endmodule Te"& be$c' 44timescale 1ns51ps 4include 6dff.(6 module dfftb1/ reg d8t/ reg cl+8t/ reg reset8t/ ,ire F"8t.F18t/ integer i/ dff1 d1(F"8t.F18t.d8t.cl+8t.reset8t)/ initial begin 9dumpfile(6dffdump.(cd6)/ 9dump(ars(#.dfftb1.d1)/ end initial begin reset8t11<b"/ cl+8t11<b1/ d8t11<b1/ ?#" d8t11<b"/ ?#" d8t11<b1/ end al,ays begin
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?H cl+8t=1Gcl+8t/ end initial ?1"" 9finis7/ ndmodule OBSER)ATIO*
RESULT IJ flipflop 7as been designed and implemented and ,a(eforms 7as been obtained.
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Experiment NoB ) Date: 14 09 2011
(2+ MULTI LE3ER A*D +2( DEMULTI LE3ER

AIM Design and implement )L1 multiple$er and 1L) demultiple$er using Verilog code.
SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog ). *t+,a(e CIRCUIT DIAGRA&M a)(2+ /ul&iple4er
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TRUTH TABLE
b)+2( de/ul&iple4er
CIRCUIT DIAGRAM
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TRUTH TABLE
ROGRAM a)/ul&iple4er
De"i#$ /%dule module mu$(d.s.o)/
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input A&B"Cd/ input A1B"Cs/ output reg o/ al,ays 0(s.d) begin if(s11#<b"") o1dA"C/ else if(s11#<b"1) o1dA1C/ else if(s11#<b1") o1dA#C/ else o1dA&C/ end endmodule Te"& be$c' 4timescale 1ns51ps 4include 6mu$b.(6 module mu$1/ reg A&B"Cd8t/ reg A1B"Cs8t/ ,ire o8t/ integer i/ mu$ m1(d8t.s8t.o8t)/ initial begin 9dumpfile(6mu$bdump.(cd6)/ 9dump(ars(#.mu$1.m1)/ end initial
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begin d8t1)<b"1"1/ for(i1"/i=1@/i1i>1) ?H :s8tA1C.s8tA"C;1i/ end initial ?1"" 9finis7/ ndmodule
b)de/ul&iple4er
De"i#$ /%dule module dmu$(y.s.a.reset)/ input a.reset/ input A1B"Cs/ output regA&B"Cy/ al,ays 0(s) begin if (reset111<b") begin case (s) #<b""Bbegin yA"C1a/ yA1C1"/ yA#C=0; yA&C1"/ end #<b"1Bbegin
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yA1C1a/ yA"C1"/ yA#C1"/ yA&C1"/ end #<b1"Bbegin yA"C1"/ yA1C1"/ yA#C1a/ yA&C1"/ end defaultBbegin yA"C1"/ yA1C1"/ yA#C1"/ yA&C1a/ end endcase end else y1&<b"""/ end endmodule Te"& be$c'
4timescale 1ns51ps 4include 6dmu$.(6

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module dmu$1/ reg a8t.reset8t/ reg A1B"Cs8t/ ,ire A&B"Cy8t/ integer i/ dmu$ d1(y8t.s8t.a8t.reset8t)/ initial begin 9dumpfile(6dmu$dump.(cd6)/ 9dump(ars(#.dmu$1.d1)/ end initial begin a8t11<b1/ reset8t11<b1/ ?1" reset8t11<b"/ for(i1"/i=1@/i1i>1) ?H :s8tA1C.s8tA"C;1i/ end initial ?1"" 9finis7/ endmodule OBSER)ATIO* a)/ul&iple4er
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b)de/ul&iple4er
RESULT M7e )L1 multiple$er and 1L) demultiple$er 7as been designed and implemented and ,a(e forms 7as been obtained.
0OH*SO* COU*TER A*D RI*G COU*TER

AIM Design and implement Io7nson counter and Ring counter using Verilog code.
SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog

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). *t+,a(e
CIRCUIT DIAGRAM
a)0%'$"%$ c%u$&er
b)ri$# c%u$&er
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TRUTH TABLE a)0%'$"%$ c%u$&er
b)ri$# c%u$&er
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ROGRAM a)0%'$"%$ c%u$&er De"i#$ /%dule module Ko(cl+.reset.F)/ reg A&B"C$/ input cl+.reset/ output reg A&B"CF/ al,ays0(posedge cl+) if (reset111) :F.$;1%<b1"""1111/ else F1(F11)<b1""")N$==#B(F11)<b11"")N$==1B(F11)<b111")N$B(F11)<b"""")N)<b1"""B FOO1/ endmodule Te"& be$c' 4timescale 1ns51ps 4include 6Ko7.(6 module Ko71/ reg A&B"C$/
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reg cl+.reset/ ,ire A&B"CF/ Ko K(cl+.reset.F)/ initial begin 9dumpfile(6KK.(cd6)/ 9dump(ars(#.Ko71.K)/ end initial begin cl+11<b"/ reset11<b1/ ?#" reset11<b"/ end al,ays ?1" cl+1Gcl+/ initial ?1""" 9finis7/ endmodule b)Ri$# c%u$&er De"i#$ /%dule module ring1(F.cl+.reset)/ input cl+.reset/ output regA&B"CF/ al,ays 0(posedge cl+) if (reset111<b") F1(FA&CPFA#CPFA1C)NFOO1BF==&/ else F1)<b1"""/ endmodule
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Te"& be$c' 4timescale 1ns51ps 4include 6ring.(6 module ringtb1/ reg cl+1.reset1/ ,ire A&B"CF1/ ring1 r1(F1.cl+1.reset1)/ initial begin 9dumpfile (6ringdump.(cd6)/ 9dump(ars (#.ringtb1.r1)/ end initial begin cl+111<b1/ reset111<b1/ ?1" reset111<b"/ end al,ays ?H cl+11Gcl+1/ initial ?1"" 9finis7/ endmodule
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OBSER)ATIO* a)0%'$"%$ c%u$&er
b)ri$# c%u$&er
RESULT M7e Io7nson counter and Ring counter 7as been designed and implemented and ,a(eform 7as been obtained.
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ARALLEL I* SERIAL OUT SHIFT REGISTER

AIM Design and implement parallel in serial out s7ift register using Verilog code.
SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog ). *t+,a(e CIRCUIT DIAGRAM
ROGRAM De"i#$ /%dule module piso(so.r.c.pi.dir)/

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input dir.r.c/ input A&B"Cpi/ output reg so/ reg A&B"Ct/ integer count1"/ al,ays 0(posedge c) begin if(r111) begin so11<b"/ t1)<b"/ end else begin count1count>1/ case(dir) 1<b1Bcase(count) 1Bt1pi/ #Bso1tA"C/ &Bso1tA1C/ )Bso1tA#C/ HBso1tA&C/ !Bcount1"/ endcase 1<b"Bcase(count) 1Bt1pi/ #Bso1tA&C/ &Bso1tA#C/ )Bso1tA1C/ HBso1tA"C/ !Bcount1"/
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endcase endcase end end endmodule Te"& be$c' 4timescale 1ns51ps 4include 6piso.(6 module piso8tb/ reg dir1.r1.c1/ reg A&B"Cpi1/ reg A&B"Ct/ ,ire so1/ piso ps(so1.r1.c1.pi1.dir1)/ initial begin 9dumpfile (6pisodump.(cd6)/ 9dump(ars (#.piso8tb.ps)/ end initial begin c111<b1/ r111<b1/ dir111<b"/ pi11)<b"/ ?1" r111<b"/ dir111<b1/ pi11)<b"111/ ?!" dir111<b"/ pi11)<b11"1/ end
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al,ays begin ?H c11Gc1/ end initial ?H"" 9finis7/ endmodule OBSER)ATIO*
RESULT
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M7e program for parallel in serial out s7ift register ,as e$ecuted and output ,as (erified ,
BARREL SHIFTER
AIM Design and implement barrel s7ifter using Verilog code.
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ROGRAM De"i#$ /%dule

module bs(s.a.b.cl+.reset)/ input cl+.reset/ input A#B"Cs/ input A&B"Ca/ output regA&B"Cb/ al,ays 0(posedge cl+) begin if(reset111<b") b1sA#CN(sA1CN(sA"CNaOO)BaOO&)B(sA"CNaOO#BaOO1))B(sA1CN(sA"CNa==)Ba==&)B(sA"CNa==#Ba==1))/ else b1)<b""""/ end endmodule
Te"& be$c'
4timescale 1ns51ps 4include 6barrl.(6 module barreltb1/ reg cl+1.reset1/ reg A#B"Cs1/ reg A&B"Ca1/ ,ire A&B"Cb1/ integer i/
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barrel bs1(s1.a1.b1.cl+1.reset1)/ initial begin 9dumpfile (6barreldump.(cd6)/ 9dump(ars (#.barreltb1.bs1)/ end initial begin cl+111<b1/ reset111<b1/ a111<b"/ s111<b"/ ?1" reset111<b"/ a11)<b1"1"/ for(i1"/i=1@/i1i>1) ?1" s11i/ end al,ays ?H cl+11Gcl+1/ initial ?1"" 9finis7/ ndmodule
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OBSER)ATIO*
RESULT - barrel s7ifter 7as been designed and implemented and ,a(e forms 7as been obtained.
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U*I)ERSAL SHIFT REGISTER

AIM Design and implement uni(ersal s7ift register using Verilog code.
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ROGRAM De"i#$ /%dule module usr1(cl+.reset.m.d.si.so.pi.po)/ input cl+.reset.si.d/ input A1B"Cm/ input A&B"Cpi/ reg A&B"Ccount/ output reg A&B"Cpo/ output reg so/ reg A&B"Ct/ al,ays 0(posedge cl+) begin if (reset111) begin po1)<b"/ so11<b"/ count1"/ t1)<b"/ end else begin count1count>1/ case(m) #<b""Bbegin if (d11")
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begin case(count) )<b"""1BtA"C1si/ )<b""1"BtA1C1si/ )<b""11BtA#C1si/ )<b"1""BtA&C1si/ )<b"1"1Bso1tA"C/ )<b"11"Bso1tA1C/ )<b"111Bso1tA#C/ )<b1"""Bso1tA&C/ )<b1""1Bcount1)<b""""/ endcase end else begin case(count) )<b"""1BtA"C1si/ )<b""1"BtA1C1si/ )<b""11BtA#C1si/ )<b"1""BtA&C1si/ )<b"1"1Bso1tA&C/ )<b"11"Bso1tA#C/ )<b"111Bso1tA1C/ )<b1"""Bso1tA"C/ )<b1""1Bcount1)<b""""/
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endcase end end #<b"1Bbegin case(count) )<b"""1BtA"C1si/ )<b""1"BtA1C1si/ )<b""11BtA#C1si/ )<b"1""BtA&C1si/ )<b"1"1Bpo1t/ )<b"11"Bcount1)<b"/ endcase end #<b1"Bbegin if (d11") begin case(count) )<b"""1Bt1pi/ )<b""1"Bso1tA"C/ )<b""11Bso1tA1C/ )<b"1""Bso1tA#C/ )<b"1"1Bso1tA&C/ )<b"11"Bcount1)<b"/ endcase end
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else begin case(count) )<b"""1Bt1pi/ )<b""1"Bso1tA&C/ )<b""11Bso1tA#C/ )<b"1""Bso1tA1C/ )<b"1"1Bso1tA"C/ )<b"11"Bcount1)<b"/ endcase end end #<b11Bbegin case(count) )<b"""1Bt1pi/ )<b""1"Bpo1t/ )<b""11Bcount1)<b"/ endcase end endcase end end endmodule Te"& be$c' 4timescale 1ns51ps
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4include 6usr.(6 module usrtb1/ reg cl+1.reset1.si1.d1/ reg A1B"Cm11/ reg A&B"Cpi1/ ,ire so1/ ,ire A&B"Cpo1/ usr1 u1(cl+1.reset1.m11.d1.si1.so1.pi1.po1)/ initial begin 9dumpfile(6usrdump.(cd6)/ 9dump(ars (#.usrtb1.u1)/ end initial begin cl+111<b1/ reset111<b1/ pi11)<b"/ ?1" reset111<b"/ m111#<b""/ d111<b1/ si111<b1/ ?1" si111<b1/ ?1" si111<b"/ ?1" si111<b1/
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?!" m111#<b"1/ si111<b1/ ?1" si111<b1/ ?1" si111<b"/ ?1" si111<b1/ ?)" m111#<b1"/ d111<b"/ pi11)<b1"11/ ?!" m111#<b11/ pi11)<b1"11/ end al,ays ?H cl+11Gcl+1/ initial ?1""" 9finis7/ endmodule OBSER)ATIO*
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RESULT Qni(ersal s7ift register 7as been designed and implemented and ,a(e form 7as been obtained ,
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COM ARATOR
AIM Design and implement comparator using Verilog code.
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TRUTH TABLE
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ROGRAM De"i#$ /%dule module compr(y.a.b)/ input A#B"Ca/ input A#B"Cb/ output A#B"Cy/ assign y1(a11b)N1""B((a=b)N"1"B""1)/ endmodule Te"& be$c'
`timescale 1ns/1ps `include "comp.v" module comp1; e! "2#0$a1;
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e! "2#0$%1; &i e "2#0$'; comp c(')a1)%1*; initial %e!in +dump,ile("compdump.vcd"*; +dumpva s(2)comp1.c*; end initial %e!in a1=3-%001; %1=3-%010; .5 a1=3-%000; %1=3-%000; .5 a1=3-%011; %1=3-%001; end initial .100 +,inis/; endmodule
OBSER)ATIO*
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RESULT M7e comparator circuit 7as been designed and implemented and ,a(e forms 7as been obtained.
U DOW* COU*TER
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AIM Design and implement updo,n counter using Verilog code.
56 5-
5+
789
00 20 1 01 21 1 02 22 1
30
31
32
mode Eloc+
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TRUTH TABLE
C%u$&er "&a&e" re"e$& "&a&e M%de " " " " " " " " 1 1 1 1 1 1 1 1 5- 5+ 56 " " " " 1 1 1 1 1 1 1 1 " " " " " " 1 1 " " 1 1 1 1 " " 1 1 " " " 1 " 1 " 1 " 1 1 " 1 " 1 " 1 " *e4& "&a&e 5- 5+ 56 " " " 1 " 1 1 " 1 1 1 " 1 1 1 " 1 " 1 " 1 " " 1
" " 1 1 1 " 1 " " " " 1
" " 1 1 1 " " 1 " " 1 1
ROGRAM
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De"i#$ bl%c:
module updo&n1(out)m)cl4) eset*; input cl4) eset)m; output e! "3#0$out; al&a5s 6(ne!ed!e cl4* %e!in i, ( eset==1* out=3-%000; else %e!in case(m* 1-%0#out=out71; de,ault#out=out81; endcase end end endmodule
Te"& be$c'
`timescale 1ns/1ps `include "updo&n.v" module updo&nt%1; e! m9t)cl49t) eset9t; &i e "2#0$out9t; updo&n1 ud(out9t)m9t)cl49t) eset9t*; initial
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%e!in +dump,ile("updo&ndump.vcd"*; +dumpva s(2)updo&nt%1.ud*; end initial %e!in cl49t=1-%1; eset9t=1-%1; .10 eset9t=1-%0; m9t=1-%1; .40 m9t=1-%0; end al&a5s .5 cl49t=:cl49t; initial .200 +,inis/; ;ndmodule
OBSER)ATIO*
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RESULT M7e program for updo,n counter ,as e$ecuted and output ,as (erified
DECADE COU*TER
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AIM Design and implement decade counter using Verilog code.
TRUTH TABLE
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Ou&pu&" Cl%c: " 1 # & ) H ! @ % R 5A " " " " " " " " 1 1 5B " " " " 1 1 1 1 " " 5C " " 1 1 " " 1 1 " " 5D " 1 " 1 " 1 " 1 " 1
ROGRAM De"i#$ /%dule module mod1"1(out.cl+.reset)/ input cl+.reset/ output regA&B"Cout/ al,ays 0(posedge cl+) begin if (reset111) out1)<b""""/ else begin if (out=)<b1""1) out1out>1/ else
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out1)<b""""/ end end endmodule Te"& be$c' 4timescale 1ns51ps 4include 6mod1".(6 module mod1"tb1/ reg cl+8t.reset8t/ ,ire A&B"Cout8t/ mod1"1 m1"(out8t.cl+8t.reset8t)/ initial begin 9dumpfile(6mod1"dump.(cd6)/ 9dump(ars(#.mod1"tb1.m1")/ end initial begin cl+8t11<b1/ reset8t11<b1/ ?1" reset8t11<b"/ end al,ays ?H cl+8t1Gcl+8t/ initial ?#"" 9finis7/ endmodule OBSER)ATIO*
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RESULT M7e circuit for decade counter 7as been designed and implemented and ,a(eforms 7as been obtained.
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LMV 108 VLSI Design Lab Va%"a&ulam Date: 21 09 2011
SE5UE*CE DETECTOR
AIM Design and implement seFuence detector ("111") using Verilog code.
SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog ). *t+,a(e
CIRCUIT DIAGRAM
0/0 1/0 0/0
0/0 1/0
>
0/0 0/1 1/0 1 < 1/0 1/0
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TRUTH TABLE
ROGRAM De"i#$ /%dule module seF1($.S.cl+.reset)/ input $.cl+.reset/ output reg S/ reg A#B"Cns/ reg A#B"Cps/ al,ays 0(posedge cl+) begin if (reset111<b") begin if ($111) begin case(ps) &<b"""Bbegin ns1&<b""1/ S11<b"/ ps1&<b""1/
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end &<b""1Bbegin ns1&<b"1"/ S11<b"/ ps1&<b"1"/ end &<b"1"Bbegin ns1&<b"11/ S11<b"/ ps1&<b"11/ end &<b"11Bbegin ns1&<b1""/ S11<b"/ ps1&<b1""/ end &<b1""Bbegin ns1&<b1""/ S11<b"/ ps1&<b1""/ end endcase end else begin case(ps) &<b"""Bbegin ns1&<b"""/ ps1&<b"""/ S11<b"/ end
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&<b""1Bbegin ns1&<b"""/ ps1&<b"""/ S11<b"/ end &<b"1"Bbegin ns1&<b"""/ ps1&<b"""/ S11<b"/ end &<b"11Bbegin ns1&<b"""/ ps1&<b"""/ S11<b1/ end &<b1""Bbegin ns1&<b"""/ ps1&<b"""/ S11<b"/ end endcase end end else begin S11<b"/ ns1&<b"/ ps1&<b"/ end end endmodule
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Te"& be$c' 4timescale 1ns51ps 4include 6seF#.(6 module seF#tb1/ reg cl+1.reset1/ reg $1/ ,ire S1/ seF1 s1($1.S1.cl+1.reset1)/ initial begin 9dumpfile (6seFdump.(cd6)/ 9dump(ars (#.seF#tb1.s1)/ end initial begin cl+111<b1/ reset111<b1/ ?1" reset111<b"/ $111<b"/ ?1" $111<b1/ ?1" $111<b1/ ?1" $111<b1/ ?1" $111<b"/ ?1" $111<b1/ ?1" $111<b1/ ?1" $111<b1/ ?1" $111<b1/ ?1" $111<b"/ ?1" $111<b1/ ?1" $111<b1/
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?1" $111<b1/ ?1" $111<b"/ ?1" $111<b1/ ?1" $111<b"/ end al,ays ?H cl+11Gcl+1/ initial ?#"" 9finis7/ endmodule
OBSER)ATIO*
RESULT M7e circuit for seFuence detector 7as been designed and implemented and ,a(eforms 7as been obtained.
'oll (o)10
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ALU
AIM Design and implement -TQ using Verilog code.
ROGRAM De"i#$ /%dule module alu($.y.m.out1.out#.cl+.reset)/ input A#B"C$/ input A#B"Cy/ input A1B"Cm/
'oll (o)10
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input cl+.reset/ output reg A&B"Cout1/ output reg A&B"Cout#/ al,ays 0(posedge cl+) begin if(reset11") begin case(m) #<b""B:out1.out#;1$>y/ #<b"1B:out1.out#;1$Uy/ #<b1"B:out1.out#;1$Ly/ defaultB:out1.out#;1$5y/ endcase end else :out1.out#;1%<b"/ end endmodule Test bench 4timescale 1ns51ps 4include 6alu.(6 module alu1tb/ reg A#B"C$1/ reg A#B"Cy1/ reg A1B"Cm1/ reg cl+1.reset1/ ,ire A&B"Cout11/ ,ire A&B"Cout#1/ alu a1($1.y1.m1.out11.out#1.cl+1.reset1)/
'oll (o)10
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initial begin 9dumpfile(6aludump.(cd6)/ 9dump(ars(#.alu1tb.a1)/ end initial begin reset111<b1/ cl+111<b1/ m11#<b""/ $11&<b"""/ y11&<b"""/ ?1" reset111<b"/ cl+111<b1/ $11&<b1""/ y11&<b"1"/ m11#<b""/ ?#" m11#<b"1/ ?#" m11#<b1"/ ?#" m11#<b11/ end al,ays ?H cl+11Gcl+1/ initial ?#"" 9finis7/ endmodule
'oll (o)10
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OBSER)ATIO*
RESULT M7e circuit for -TQ 7as been designed and implemented and ,a(eforms 7as been obtained .
'oll (o)10
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Experiment No:14 Date: 23 12 2011
( WA; TRAFFIC LIGHT S;STEM AIM

<esi!n and implement a 4 &a5 t a,,ic li!/t s5stem usin! ?e ilo! code.
'oll (o)10
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ROGRAM De"i#$ /%dule module traffic(p1.p#.p&.p).c.r)/ output reg A#B"Cp1/ output reg A#B"Cp#/ output reg A#B"Cp&/ output reg A#B"Cp)/ input c.r/ integer d1"/ al,ays 0(negedge c) begin if(r111<b1) begin p11&<b1""/ p#1&<b1""/ p&1&<b1""/ p)1&<b1""/ end else begin d1d>1/ case(d) 1B begin p11&<b""1/ p#1&<b1""/ p&1&<b1""/
'oll (o)10
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p)1&<b1""/ end HB begin p11&<b"1"/ p#1&<b1""/ p&1&<b1""/ p)1&<b1""/ end @B begin p11&<b1""/ p#1&<b""1/ p&1&<b1""/ p)1&<b1""/ end 11B begin p11&<b1""/ p#1&<b"1"/ p&1&<b1""/ p)1&<b1""/ end 1&B begin p11&<b1""/ p#1&<b1""/ p&1&<b""1/ p)1&<b1""/
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end 1@B begin p11&<b1""/ p#1&<b1""/ p&1&<b"1"/ p)1&<b1""/ end 1RB begin p11&<b1""/ p#1&<b1""/ p&1&<b1""/ p)1&<b""1/ end #&B begin p11&<b1""/ p#1&<b1""/ p&1&<b1""/ p)1&<b"1"/ end #HB begin p11&<b1""/ p#1&<b1""/ p&1&<b1""/ p)1&<b1""/ end endcase
'oll (o)10
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end end endmodule
Te"& be$c' 4timescale 1ns51ps 4include 6traffic.(6 module traffic8tb/ reg c1.r1/ ,ire A#B"Cp11/ ,ire A#B"Cp#1/ ,ire A#B"Cp&1/ ,ire A#B"Cp)1/ traffic tr(p11.p#1.p&1.p)1.c1.r1)/ initial begin 9dumpfile (6trafficdump.(cd6)/ 9dump(ars (#.traffic8tb.tr)/ end initial begin c111<b"/ r111<b1/ ?H r111<b"/ end al,ays ?H c11Gc1/ initial ?H"" 9finis7/
'oll (o)10
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endmodule
OBSER)ATIO*
RESULT - ) ,ay traffic lig7t controller 7as been designed and implemented ,a(eforms 7a(e been obtained.
'oll (o)10
79
Experiment No:15 Date: 24 12 2011
RAM AIM
<esi!n and implement a @=A usin! ?e ilo! code.
SOFTWARES USED 1. ModelSim (Versions) #. Xilin$ (Versions) &. '(erilog ). *t+,a(e CIRCUITDIAGRAM
TRUTH TABLE
'oll (o)10
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ROGRAM De"i#$ /%dule module ram1(din.dout.r.e.addr.cl+)/ input e.r.cl+/ input A&B"Caddr/ input A@B"Cdin/ output reg A@B"Cdout/ reg A@B"CmemA1HB"C/ al,ays 0(posedge cl+) begin if (e111) begin case(r) 1<b"Bdout1memAaddrC/ 1<b1Bbegin memAaddrC1din/
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dout1%<b"/ end endcase end else begin memA)<b"""1C1%<b"""""111/ memA)<b""1"C1%<b"/ dout1%<b"/ end end endmodule Te"& be$c'
4timescale 1ns51ps 4include 6ram.(6 module ramtb1/ reg cl+1.e1.r1/ reg A&B"Caddr1/ reg A@B"Cdin1/ reg A@B"CmemA1HB"C/ ,ire A@B"Cdout1/ ram1 rr1(din1.dout1.r1.e1.addr1.cl+1)/ initial begin 9dumpfile (6ramdump.(cd6)/
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9dump(ars (#.ramtb1.rr1)/ end initial begin cl+111<b1/ e111<b"/ addr11)<b"/ din111<b"/ r111<b"/ ?1" e111<b1/ r111<b"/ addr11)<b"""1/ din11%<b"/ ?1" r111<b1/ din11%<b""""11""/ addr11)<b"1"1/ ?1" r111<b"/ addr11)<b"1"1/ din11%<b"/ end al,ays ?H cl+11Gcl+1/ initial ?1"" 9finis7/ endmodule
'oll (o)10
83
OBSER)ATIO*
RESULT - R-M 7as been designed and implemented and ,a(eforms 7a(e been obtained.
'oll (o)10
84

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LMV 108 VLSI Design Lab Va%"a&ulam Experiment No:1 Date: 16 09 2011

LMV 108 VLSI Design Lab Va%"a&ulam

c)Ripple carry adder

TRUTH TABLE a)Half adder

LMV 108 VLSI Design Lab Va%"a&ulam

c)Ripple carry adder

ROGRAM !i) Half Adder

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

!ii) Full Adder

!iii)( Bi& Ripple Carry Adder

LMV 108 VLSI Design Lab Va%"a&ulam

ROGRAM De"i#$ /%dule module dff1(F".F1.d.cl+.reset)/ input d.cl+.reset/

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

Experiment No: 3 Date: 14 09 2011

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

?H cl+8t=1Gcl+8t/ end initial ?1"" 9finis7/ ndmodule OBSER)ATIO*

LMV 108 VLSI Design Lab Va%"a&ulam

Experiment NoB ) Date: 14 09 2011

(2+ MULTI LE3ER A*D +2( DEMULTI LE3ER

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

begin d8t1)<b"1"1/ for(i1"/i=1@/i1i>1) ?H :s8tA1C.s8tA"C;1i/ end initial ?1"" 9finis7/ ndmodule

LMV 108 VLSI Design Lab Va%"a&ulam

4timescale 1ns51ps 4include 6dmu$.(6

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

Experiment No: 5 Date: 15 09 2011

0OH*SO* COU*TER A*D RI*G COU*TER

SOFTWARES USED 1. ModelSim (X 111 !."d) #. Xilin$ (%.1i) &. '(erilog

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

TRUTH TABLE a)0%'$"%$ c%u$&er

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

OBSER)ATIO* a)0%'$"%$ c%u$&er

LMV 108 VLSI Design Lab Va%"a&ulam

Experiment No: 6 Date: 15 09 2011

ARALLEL I* SERIAL OUT SHIFT REGISTER

ROGRAM De"i#$ /%dule module piso(so.r.c.pi.dir)/

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

LMV 108 VLSI Design Lab Va%"a&ulam

al,ays begin ?H c11Gc1/ end initial ?H"" 9finis7/ endmodule OBSER)ATIO*

LMV 108 VLSI Design Lab Va%"a&ulam

Experiment No: 7 Date: 16 09 2011

0OHSO COUTER AD RIG COUTER