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Benefits of adding an active clamp to a synchronous fl yback power supply

By J ohn Betten and Brian King, Texas Instruments Incorporated

Flyback converters are a popular choice in applications that require an isolated power
supply to deliver low to medium output power. When efficiency is a primary concern, you
can replace the flyback output diode with a MOSFET, resulting in what is commonly
referred to as a synchronous flyback converter. POE (power-over-Ethernet) applications
are prime candidates for synchronous flyback supplies. Presently, the input power for
POE supplies is limited to 12.95W. Maximizing the efficiency of the power supply allows
the system to deliver more power to the load. You can gain further improvements to the
converters efficiency by using an active-clamp controller to reduce the snubber and
shoot-through losses.

Active-clamp forward converters have been an increasingly popular choice in higher
power applications. Yet few power-supply designers are aware that they can also
employ an active clamp in flyback converters. To investigate the benefits of the active-
clamp control in a flyback topology, we designed, built, and tested two power supplies to
the specification shown in Table 1. Both power supplies use synchronous rectification on
the secondary, but one uses the power transformer to drive the synchronous FET; the
other uses a gate-drive transformer and also implements an active clamp. The POE
input requirements inspired the specifications, but we extended the input range to cover
telecom applications. In the interest of a fair comparison, we kept major components not
affected by the differences in the two approaches identical in both designs. Figure 1
shows photos of each circuit. We also kept component placement and layout common
for both boards. The most noticeable difference between the two circuits is the addition
of a gate-drive transformer in the active-clamp circuit.

Parameter Specifi cation
Input VOLTAGE -36 to -72V
Output voltage 3.3V
Output current 0 to 3.5A
Ripple 1% maximum
Efficiency (max load) 85% minimum

Table 1: Electrical Specifications


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Figure 1 Both power supplies use synchronous rectification on the secondary, but the one on the left uses
the power transformer to drive the synchronous FET; the one on the right uses a gate-drive transformer and
also implements an active clamp.

Figure 2 shows simplified schematics for the two approaches. In each design, the
controllers modulate the on time of FET Q
2
to control the amount of energy that
transformer T
1
stores and to regulate the output voltage. Parasitic leakage inductance in
the primary of the transformer also stores energy, which can lead to excessive voltage
spikes on Q
2
if you do not clamp it. The traditional synchronous flyback design dissipates
this leakage energy in the snubber circuit of D
1
, R
2
, and C
4
. This dissipation can lead to
appreciable losses that lower the efficiency of the supply. The active-clamp design uses
the clamp circuit of C
21
and Q
4
to store the leakage energy in C
21
and return the energy
back to the input source. This nondissipative clamping technique results in virtually
lossless snubbing of the primary MOSFET.

+
+
XFMR-DRIVEN SYNC FLYBACK ACTIVE-CLAMP SYNC FLYBACK


Figure 2In these simplified flyback power supplies, the controllers modulate the on time of FET Q2 to
control the amount of energy that transformer T1 stores and to regulate the output voltage.

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When you turn off Q
2
, the system transfers the energy that the transformer stores to the
output through synchronous MOSFET Q
1
. The synchronous FET requires a gate-drive
signal that is the inverse of the PWM signal controlling the main primary FET Q
2
. The
traditional transformer-driven synchronous flyback generates this signal from an
auxiliary winding on T
1
. Internal switching delays of Q
1
and poor coupling to the auxiliary-
gate-drive winding commonly result in shoot-through current when Q
2
is turned on.
Essentially, there is a finite period of time where both Q
1
and Q
2
are on. It is very difficult
to eliminate this overlap period, but you can decrease it by selecting a fast MOSFET for
Q
1
. This step is essential for minimizing shoot-through losses and achieving acceptable
efficiencies in a traditional synchronous flyback. By contrast, the active-clamp flyback
can make use of the gate-drive signal for the clamp FET Q
4
to reduce shoot-through
losses. This signal, which the control IC generates, includes delays to ensure that both
Q
2
and Q
4
are never on at the same time. In the active-clamp design, this gate-drive
signal is transmitted through a gate-drive transformer to drive the synchronous FET. The
gate-drive transformer is necessary to level shift the gate-to-source drive signal of Q
1

and maintain the input to output voltage isolation.

Figure 3 shows the full schematic for the traditional synchronous flyback design. This
design uses a low-cost, simple, current-mode PWM controller, the UCC2809, to control
the power supply. In addition to the primary snubber, this circuit also requires the zener
clamp circuit of D
3
and D
4
to prevent excessive gate-to-source voltages on Q
1
from
leakage-induced spikes.

+
GND
+
3.3V @ 3.5A
+
+


Figure 3This design uses a low-cost, simple, current-mode PWM controller, the UCC2809, to control the
power supply.

Figure 4 displays the full schematic for the active-clamp design. In this circuit, the
UCC2897 active-clamp controller provides current-mode control of the power supply. As
the schematics show, this more complicated approach requires several additional
components that are not necessary in the traditional synchronous flyback. The most
expensive of these extra parts are the active clamp p-channel FET, Q
4
, and the gate-
drive transformer, T
2
. The p-channel FET can often be a small component, such as a
SOT-23 package. The power dissipation in this part is very low, because it only steers
the leakage and magnetizing currents. Also, additional low-cost discrete components
accompany these two parts to condition the gate drives for Q
4
and Q
1
.
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+
GND
+
3.3V @ 3.5A
+ +


Figure 4In this circuit, the UCC2897 active-clamp controller provides current-mode control of the power
supply.

Examining the drain-to-source voltage of the primary FETs, Q
4
, reveals an interesting
difference in the performances of the two designs (Figure 5). The traditional
synchronous flyback exhibits a voltage spike, peaking at approximately 165V, and the
active-clamp-circuit drain-to-source voltage is limited to around 130V peak. This voltage
spike forces the use of a 200V-rated FET for the traditional synchronous flyback,
whereas the active-clamp flyback uses a 150V-rated FET. In addition, the EMI emissions
of the active-clamp drain waveform are more desirable than that of the traditional
synchronous flyback.




Figure 5 Examining the drain-to-source voltage of the primary FETs, Q4, reveals an interesting difference
in the performances of the two designs.

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You can make more distinctions between the two designs from the transformer
secondary voltages, shown in Figure 6. At first glance, the two waveforms look very
similar. Closer inspection uncovers that the negative ringing of the traditional
synchronous flyback is much worse than that of the active-clamp flyback. This ringing
occurs at the turn-on transition of the primary FET and is caused by the turn-off delay of
the synchronous FET. Note that the gate-to-source turn-off voltage of the synchronous
FET coincides with the reversal of the secondary winding voltage. The synchronous FET
must be completely off at the same time that the transformer secondary voltage
becomes negativea difficult taskotherwise shoot-through occurs. The controller-
driven gate-drive signal of the active-clamp design ensures that the synchronous FET is
off before the primary FET turns on and reduces this voltage ringing. It also impacts the
synchronous FET selection. The active-clamp design was able to use a slower
synchronous FET, with a lower R
dson
than the traditional synchronous flyback. The
reduced ringing still present on the active clamps synchronous FET is due to the
reverse recovery of the FETs body diode.



Figure 6 The negative ringing of the traditional synchronous flyback is much worse than that of the active-
clamp flyback.

All of these slight improvements that the active clamp provides have an appreciable
combined effect on the efficiency. Figure 7 displays the efficiency of both designs,
measured at minimum, nominal, and maximum input voltages. The active-clamp design
improves the efficiency at maximum load by around 2% at all line conditions. The
differences are more dramatic at light load conditions. Efficiency at nominal line and light
loads showed an improvement of greater than 12%, which can be significant in systems
that run idle for extended periods of time. Most of the efficiency gains result from the
recovery of the leakage inductance energy, which is normally dissipated in snubbers and
decreasing the shoot-through losses in synchronous FET Q
1
.

Table 2 lists a summary of key areas of comparison between the two synchronous
flybacks. It shows that the active-clamp flyback holds a performance advantage over the
transformer-driven synchronous flyback. The active-clamp flyback boasts lower FET
voltage stresses and higher efficiency, especially at light loads. The programmable
dead-time feature of the active-clamp controller (UCC2897), which prevents overlapping
conduction of the primary and secondary FETs, helps to minimize secondary-side shoot-
through losses in Q
1
. These losses typically manifest as a large current spike seen in the
primary current sense resistor, often making light load jitter an issue. Low levels of high-
frequency ringing in the active-clamp flyback results in less EMI and an overall less
noisy power supply. Because leakage inductance has less impact on the active clamps
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circuit performance, higher frequency operation is possible than with the synchronous
flyback. The synchronous flyback is not without merits, though. In the two example
circuits, the traditional synchronous flyback requires about 15 to 20% less PWB area,
component count, and cost over the active-clamp flyback. It is also a simpler circuit to
design and (arguably) understand, although as previously mentioned, there are several
performance drawbacks to consider. So, when should you choose an active-clamp
flyback? If the output power is low and the design requires continuous-mode operation at
all times, an active-clamp flyback can achieve high-efficiency and low-EMI operation. It
offers a distinct advantage when light-load efficiency is critical.

50%
55%
60%
65%
70%
75%
80%
85%
90%
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5
Load Current (Amps)
E
f
f
i
c
i
e
n
c
y
-36Vin, Active Clamp -48Vin, Active Clamp
-72Vin, Active Clamp -36Vin, Sync Flyback
-48Vin, Sync Flyback -72Vin, Sync Flyback

Figure 7 The active-clamp design improves the efficiency at maximum load by around 2% at all line
conditions.

Parameter
Sync
Flyback
Active
Clamp
Peak efficiency (%) 85.5 87.7
Max Primary FET stress (V) 162 130
Max Secondary FET stress (V) 17 14
Area (square inches) 2.7 3.2
Component count 55 64
Relative cost 1 1.2
Relative complexity Simple Moderate

Table 2: Comparison chart

Authors biographies
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Brian King is an application engineer with Texas Instruments in Dallas. He specializes in the
design of switching power supplies. Brian holds a BSEE and MSEE from the University of
Arkansas.

J ohn Betten is an application engineer and senior member of the group technical staff at Texas
Instruments in Dallas. Betten has 21 years design experience in the field of ac/dc and dc/dc
power conversion. He has published more than 25 articles and has been awarded one patent.
Betten received his BS degree in electrical engineering from the University of Pittsburgh in 1985
and is a member of the IEEE.