SREEBUDHA COLLEGE OF ENGINEERING-PATTOR

VHDL PROGRAMMING LABORATORY RECORD

SUBMITTED BY ATHIRA SIVANANDHAN MTECH EMBEDDED SYSTEM

DEPARTMENT OF ELECTRONICS AND INSTRUMENTATION2010 TO 2012 BATCH

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EXPERIMENT NO: 1 1.A HALF ADDER

AIM:

ARITHEMATIC CIRCUITS

To write VHDL program to implement half adder using i)With Select Statement ii)When Else Statement iii)If Else Statement iv)Case Statement ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the program. Include the IEEE library and package. Declare the entity of half adder. Declare the input and output ports. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Stimulate the waveform.

1.B FULL ADDER

AIM:

To write VHDL program to implement full adder using i)With Select Statement ii)When Else Statement iii)If Else Statement iv)Case Statement
ALGORITHM

1. 2. 3. 4. 5. 6. 7.

Start the program. Include the IEEE library and package. Declare the entity of full adder. Declare the input and output ports. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Stimulate the waveform.

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EXPERIMENT NO: 2
2A.HALF AIM: To write VHDL program to implement half adder using NAND gates. ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the low level program. Include the IEEE library and package. Declare the entity for the component-NAND gate. Declare the input and output ports of NAND gate. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Start the top level program. 10. Include the IEEE library and package. 1. 11.Declare the entity of half adder. 11. Declare the input and output ports of half adder. 12. End the entity. 13. Declare the architecture. 14. Call component ie,NAND gate in to the top level program. 15. End component. 16. Signal declaration. 17. Define the circuit at the structural level by port mapping. 18. End the architecture. 19. Stimulate the waveform.

ADDER USING NAND GATES

2B.FULL ADDER AIM:

USING NAND GATES

To write VHDL program to implement full adder using NAND gates. ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the low level program. Include the IEEE library and package. Declare the entity for the component-NAND. Declare the input and output ports of NAND gate. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Start the top level program. 10. Include the IEEE library and package. 11. Declare the entity of full adder. 12. Declare the input and output ports of full adder. 13. End the entity. 14. Declare the architecture. 15. Call component ie,NAND gate in to the top level program. 16. End component. 17. Signal declaration. 18. Define the circuit at the structural level by port mapping. 19. End the architecture. 20. Stimulate the waveform.

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EXPERIMENT NO: 3
3A.FULLADDER AIM: To write VHDL program to implement Full adder using NOR gates. ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the low level program. Include the IEEE library and package. Declare the entity for the component ie NOR gate. Declare the input and output ports of NOR gate. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Start the top level program. 10. Include the IEEE library and package. 11. Declare the entity of full adder. 12. Declare the input and output ports of full adder. 13. End the entity. 14. Declare the architecture. 15. Call component ie,NOR gate in to the top level program. 16. End component. 17. Signal declaration. 18. Define the circuit at the structural level by port mapping. 19. End the architecture. 20. Stimulate the waveform.

USING NOR GATES

3.B AIM:

HALFADDER USING NOR GATES

To write VHDL program to implement Half adder using NOR gates. ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the low level program. Include the IEEE library and package. Declare the entity for the component ie NOR gate. Declare the input and output ports of NOR gate. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Start the top level program. 10. Include the IEEE library and package. 11. Declare the entity of half adder. 12. Declare the input and output ports of half adder. 13. End the entity. 14. Declare the architecture. 15. Call component ie,NOR gate in to the top level program. 16. End component. 17. Signal declaration. 18. Define the circuit at the structural level by port mapping. 19. End the architecture. 20. Stimulate the waveform.

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EXPERIMENT NO: 4
4A AIM: To write VHDL program to implement Half Subtractor usingNAND gates. ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the low level program. Include the IEEE library and package. Declare the entity for the component-NAND gate. Declare the input and output ports of NAND gate. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Start the top level program. 10. Include the IEEE library and package. 11. 11.Declare the entity of half subtractor. 12. Declare the input and output ports of half subtractor. 13. End the entity. 14. Declare the architecture. 15. Call component ie,NAND gate in to the top level program. 16. End component. 17. Signal declaration. 18. Define the circuit at the structural level by port mapping. 19. End the architecture. 20. Stimulate the waveform.

HALF SUBTRACTOR USING NAND GATES

4B AIM:

FULL SUBTRACTOR USING NOR GATES

To write VHDL program to implement Full Subtractor using NOR gates. ALGORITHM 1. 2. 3. 4. 5. 6. 7. Start the low level program. Include the IEEE library and package. Declare the entity for the component ie NOR gate. Declare the input and output ports of NOR gate. End the entity. Declare the architecture. Define the functionality of the circuit at the behavioural level using the given statement. 8. End the architecture. 9. Start the top level program. 10. Include the IEEE library and package. 11. Declare the entity of fullsubtractor. 12. Declare the input and output ports of fullsubtractor. 13. End the entity. 14. Declare the architecture. 15. Call component ie,NOR gate in to the top level program. 16. End component. 17. Signal declaration. 18. Define the circuit at the structural level by port mapping. 19. End the architecture. 20. Stimulate the waveform.

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EXPERIMENT NO: 5

8:1 MULTIPLEXER USING 4:1 MULTIPLEXER AND 2:1 MULTIPLEXER

AIM: To write VHDL program to implement 8:1 Multiplexer using 4:1 Multiplexer and 2:1 Multiplexer. ALGORITHM 1. 2. 3. 4. 5. 6. Start the low level program of 2:1 Multiplexer. Include the IEEE library and package. Declare the entity for the 2:1 Multiplexer and declare the input and output ports. End the entity. Declare the architecture of 2:1 Multiplexer. Define the functionality of the circuit at the behavioural level using the given statement. 7. End the architecture. 8. Start the low level program of 4:1 Multiplexer. 9. Include the IEEE library and package. 10. Declare the entity for the 4:1 Multiplexer and declare the input and output ports. 11. End the entity. 12. Declare the architecture of 4:1 Multiplexer. 13. Define the functionality of the circuit at the behavioural level using the given statement. 14. End the architecture. 15. Start the top level program. 16. Include the IEEE library and package. 17. Declare the entity for the 8:1 Multiplexer and declare the input and output ports. 18. End the entity. 19. Declare the architecture. 20. Call component 2:1 Multiplexer in to the top level program. 21. End component. 22. Call component 4:1 Multiplexer in to the top level program. 23. End component. 24. Signal declaration. 25. Define the circuit at the structural level by port mapping. 26. End the architecture. 27. Stimulate the waveform.