Rishi Kumar Jha

1
MOS Transistor Inverter: Dynamic Characteristics

1 The MOS Inverter with Capacitive Loading
A schematic diagram of the simple MOS transistor inverter with a capacitive load is shown below
in Fig. 1. Operation is governed by similar considerations as in the case of the bipolar transistor
inverter. When the transistor is conducting it actively contributes to driving the load, but when it
is off the output conditions become heavily load dependent.
















Fig..1 Circuit of the Capacitively Loaded Simple MOS Inverter

2 Transistor Turn-Off and Inverter Rise-Time
If the switching of the transistor is taken as ideal, then when the transistor is turned off
the capacitor simply charges up exponentially through R
D
. This is the same process for any C-R
charging circuit so that the same expressions will apply for the 10% and 90% points of the output
voltage as in the case of the bipolar transistor inverter. Consequently, an almost identical
expression is obtained for the 10% -to-90% rise time as:
D L R
R 2.2C t =


If C
L
= 10pF and R
D
=100k, then t
R
= 2.2s.
This is much higher than in the case of the bipolar transistor inverter because of the much
higher value of resistor R
D
which is used because of the lower levels of current in MOS
transistors.
3 Transistor Turn-On and Inverter Fall-Time
In this case, the transistor conducts and plays an active role in discharging the
capacitance by drawing charge from it. The waveform of the output voltage is shown in Fig. 2.
Initially the output voltage will be at the supply voltage, V
DD
, with the capacitance fully charged.
If an input voltage of V
i
= V
DD
is applied to the gate of the transistor, then this means that
initially the transistor operates with V
GS
= V
DD
and with V
DS
= V
DD
so that V
DS
> V
GS
V
T
and
therefore the transistor operates in the saturation region as shown in the waveforms. Once the
V
DD

V
O
= V
DS

V
i
=V
GS
R
D

i
D

C
L
i
RD
i
CL
Rishi Kumar Jha
2
output voltage falls below the supply voltage by an amount equal to the threshold voltage, then
V
DS
< V
GS
V
T
and the transistor operates in the non-saturation region. Ultimately, the capacitor
will be discharged to the value of the output logic LO voltage, V
OL
, determined previously. As can
be seen from the waveform, generally the 90% point will be reached while operating in the
saturation region but the 10% point will be reached while operating in the non-saturation region.
This complicates the solution of equations for the fall-time. A further complication is the square
term in the expression for the drain current when operating in the non-saturation region, which
makes it more difficult to obtain a solution. This is cumbersome and the problem can be
simplified if approached in a different manner.


















Fig. 2 A Waveform of the Output Voltage from the Capacitively Loaded MOS Inverter


final logic LO
value is reached
90 t 10 t
90%
10% V
OL

V
DD
- V
T

V
DD

V
O
(t)
transistor operates in
the saturation region
transistor operates in the non-
saturation region
t
Rishi Kumar Jha
3
Things can be simplified if the transistor is treated simply as a current source having an average
value of current i
D AVE
discharging the capacitor as shown in Fig 3. The average current can be
taken as the average of the initial and final values of current during the discharging operation.















Fig. 3 Equivalent Circuit with the MOS Transistor as a Current Source

The initial value of current can be taken as the value for operation in saturation with V
i
= V
DD

as:

( ) ( )
2
T DD n D
V V K 0 t i = =


The final value of current can be taken as the current flowing through the load resistor R
D
when
the capacitor has been discharged to the minimum voltage of V
OL
, which with V
OL
> 0 is:

D
DD
D
OL DD
D
R
V
R
V V
) t ( i ~

=


This then gives the average current as:

( )
2
R / V V V K
i
D DD
2
T DD n
AVE D
+
=

V
DD

V
O
(t)
R
D

i
D AVE

C
L
i
RD
i
CL
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4
From the circuit of Fig. 3.3, using Kirchhoffs Current Law it can be seen that:
L D
C R AVE D
i i i =



dt
dV
C
R
V V
i
O
L
D
O DD
AVE D

=


Dividing across by C
L
and rearranging gives:

L
AVE D
D L
DD
O
D L
O
C
i
R C
V
V
R C
1
dt
dV
= +


Taking the Laplace transform with V
O
(t=0)=V
DD
and reorganising gives:

( )
L
AVE D
D L
DD
DD O
D L
sC
i
R sC
V
V s V
R C
1
s + =
|
|
.
|

\
|
+


( )
|
|
.
|

\
|
+

|
|
.
|

\
|
+
+
|
|
.
|

\
|
+
=
D L
D AVE D
D L
D L
DD
D L
D L
DD
O
R C
1
s s
R i
R C
1
R C
1
s s
V
R C
1
R C
1
s
V
s V


Taking the inverse Laplace transform gives:

( )
|
|
.
|

\
|

|
|
.
|

\
|
+ =
D L D L D L
R C
-t
D AVE D
R C
-t
DD
R C
-t
DD O
e 1 R i e 1 V e V t V

So that finally:
( )
|
|
.
|

\
|
=
D L
R C
-t
D AVE D DD O
e 1 R i V t V

Rishi Kumar Jha
5
As before, we want to identify the 90% and 10% points on the waveform. So at t = t
90
with V
O
=
0.9V
DD
then:

|
|
.
|

\
|
=
D L
90
R C
-t
D AVE D DD DD
e 1 R i V 0.9V


When manipulated this gives:

|
|
.
|

\
|

=
DD D AVE D
D AVE D
D L 90
V 1 . 0 R i
R i
ln R C t


Similarly:
|
|
.
|

\
|

=
DD D AVE D
D AVE D
D L 10
V 9 . 0 R i
R i
ln R C t


So that the fall time is then given as:

|
|
.
|

\
|

= =
DD D AVE D
DD D AVE D
D L 90 10 f
V 9 . 0 R i
V 1 . 0 R i
ln R C t t t


With parameter values K
n
=100AV
-2
, R
D
=100k, V
T
=1V and V
DD
=10V:

( )
4mA
2
10/10 81 x 10
2
/R V V V K
i
5 4
D DD
2
T DD n
AVE D
~
+
=
+
=



|
.
|

\
|
=
|
|
.
|

\
|

=

391
399
ln 10
9 x10 4x10
1 x10 4x10
ln x10 10 t
6
5 3 -
5 -3
5 11 -
f

So that:
20ns t
f
=


This is again a little higher than for the bipolar transistor inverter because of the higher value of
load resistance.