M.

tech Project Abstracts | VLSI

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M.tec h Projec t Abstrac ts
Show 20 | All results per page. 36 results total. # Abhinav Asthana Student Name Design and Synthesis of Asynchronous Circuits Aditya V Low power built in Prof. D. self- test (BIST) architecture for fast multiplier embedded core Aseem Verma G aurav Kaushik Design of a Low power high slew rate OPAMP Prof. Chetan D. Parikh Aseem_verma.doc (34 KB) Nagchoudhuri Aditya.doc (19 KB) Project Title Project Guide Abstract Prof. Hemangee Abhinav.doc (20 KB) Kapoor

Receiver Amplier Prof. D. Design For Nagchoudhuri Receiver Unit of Fast DATA Transfer System

G aurav_ Kaushik.doc (465 KB)

Jay Kumar Patel

Deep Submicron Extractor using probability distribution

Prof. D. Jay_Patel.doc (10 KB) Nagchoudhuri and Mr. Rajendra Pratap, Cadence Design Systems, New Delhi Jitendra.doc (48 KB)

Jitendra A Low Voltage Prof. D. Babu Bensal Low Power High Nagchoudhuri Swing Operational Amplier for High Speed Analog to Digital Converters

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M.tech Project Abstracts | VLSI

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Student Name

Project Title

Project Guide Malav.doc (38 KB)

Abstract

Malav Shah Scan-Based BIST Prof. D. VLSI Testing (DFT) Nagchoudhuri Scheme for Low Heat Dissipation and Reduced Test Application Time Manu Tandon Ronak P. Trivedi Novel architecture Prof. Chetan D. of Pipelined ADC Low Power and High Speed Sample-and-Hold Circuit Swaprakash Design of a low Mohanty power, high speed MAC unit using custom based approach Yogesh Malviya Extremely Low Prof. D. Voltage Rail to Rail Nagchoudhuri Operational Amplier Design Anuradha Ray A Novel Architecture of a CMOS LNA at 2.4GHz Mahavir Jain BIST architecture for Mixed Signal Systems Prof. D. Nagchoudhuri, Prof. Sushanta Kumar Mandal Prof.Chetan D.Parikh Prof.Chetan D.Parikh Prof.Chetan D.Parikh Prof. D. Nagchoudhuri Parikh Prof. D. Nagchoudhuri

Manu_tandon.doc (20 KB) Ronak.doc (47 KB)

Sawprakash_Mohanty.doc (19 KB)

Yogesh_Malviya.doc (1476 KB)

anuradha.doc (25 KB)

Mahavir jain.doc (12 KB)

Neha Khera Design of LASER driver circuit Mangesh Bhalerao Built-In Self-Test for a Flash Analog to Digital Converter A Fault Diagnosis Algorithm for a Flash ADC using

neha.doc (25 KB) mangesh.doc (25 KB)

Divya Aggarwal

Prof.Chetan D.Parikh

divyaagarwal.doc (26 KB)

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M.tech Project Abstracts | VLSI

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Student Name Oscillation Based Testing Technique

Project Title

Project Guide

Abstract

Narayana Rao

Low Power High Slew-Rate Adaptive Biasing Circuit for CMOS Ampliers

Prof.Chetan D.Parikh

narayana.doc (24 KB)

Ram Sahay Singh

Implementation of Prof.Chetan a constant-g m D.Parikh CMOS op-amp input stage using overlapping of transition regions

ramsahay.doc (24 KB)

Marshnil Dave

Comparison of single-bit and multi-bit second order sigma-delta modulators

Prof.Chetan D.Parikh

marshnil.doc (25 KB)

Amit Kumar G upta

An Optimized CM O S Comparator Design for Analog to Digital Converters

Prof.Chetan D.Parikh

amit.doc (24 KB)

Divya Dubey

Design of Low Prof.Chetan Voltage High D.Parikh Performance, Wide Bandwidth Current Feedback Amplier with Complementary Input Pair Area Reduction in 8 Bit Binary DAC using Current Multiplication Prof.Chetan D.Parikh

divyadubey.doc (25 KB)

Maitry Upraity

maitry.doc (24 KB)

Raju Kunde A Frequency Compensation

Prof.Chetan D.Parikh

raju.doc (24 KB)

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M.tech Project Abstracts | VLSI

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Student Name Technique For Low Voltage Three Stage Operational Amplier

Project Title

Project Guide

Abstract

G arima Bajaj

Design of Linear adaptive-biased operational amplier

Prof.Chetan D.Parikh

G arima.doc (10 KB)

Venkata Raghava Sesha Sai

Design of a wideband low-phase-noise low power voltage controlled oscillator

Prof.Chetan D.Parikh

sesha sai.doc (24 KB)

Vivek Verma

Low-Voltage, Low-Power, High-Dynamic Range, High Band-Width VGA

Prof.Chetan D.Parikh

vivek verma.doc (27 KB)

Bhavi Panchal

Curvature Compensated all-CMOS voltage Reference

Prof.Chetan D.Parikh

Bhavi Panchal.doc (27 KB)

Ch. Uday Kumar Akhil Rathore R. Ramesh

Design of a low voltage high linearity mixer

Prof.Chetan D.Parikh

Uday Kumar.doc (28 KB)

Design of a CMOS Prof.Chetan I/O Buer circuit D.Parikh Design of low voltage high performance voltage controlled oscillator Designing of an Ecient Power Clock generation circuit for Complementary Prof. D. Nagchoudhuri ,Prof. Sushanta Mandal Prof. D. Nagchoudhuri , Prof. Sushanta Mandal

Akhil Rathore.doc (27 KB) ramesh.doc (27 KB)

P. Ranjith

Ranjith.doc (27 KB)

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Student Name Pass-transistor Adiabatic Logic Carry Save Multiplier

Project Title

Project Guide

Abstract

Ajay Kumar A High Speed Sinha 512-point FFT Single-Chip Processor Architecture Punam Sen G upta Design of Low Power and high Speed Decoder for 1Mb Memory Navneet G upta, A S IC Implementation of Discrete Fourier Transform Processing Module Vishal Bhatt Low Power Microprocessor Design Vaibhav Agarwal A S IC

Prof. D. Nagchoudhuri , Prof. Sushanta Mandal Prof. D. Nagchoudhuri

Ajay Kumar Sinha_'.doc (26 KB)

Punam Sen G upta.doc (26 KB)

Rahul Dubey,

Vaibhav_Agarwal.doc (27 KB)

Prof.Rahul Dubey

vishal_Bhatt.doc (26 KB)

Prof. Rahul Implementation of Dubey, a Pipelined Bitrapezoidal Architecture For Discrete Covariance Kalman Filter

Vaibhav_Agarwal.doc (27 KB)

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