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[ Team LiB ]

Chapter 1. Overview of Digital Design with Verilog HDL

Section 1.1. Evolution of Computer-Aided Digital Design Section 1. . Emergence of !DLs Section 1.". T#pical Design $lo% Section 1.&. 'mportance of !DLs Section 1.(. )opularit# of *erilog !DL Section 1.+. Trends in !DLs [ Team LiB ] [ Team LiB ]

1.1 Evolution of Computer-Aided Digital Design

Digital circuit design ,as evolved rapidl# over t,e last ( #ears. T,e earliest digital circuits %ere designed %it, vacuum tu-es and transistors. 'ntegrated circuits %ere t,en invented %,ere logic gates %ere placed on a single c,ip. T,e first integrated circuit .'C/ c,ips %ere SS' .Small Scale Integration/ c,ips %,ere t,e gate count %as ver# small. As tec,nologies -ecame sop,isticated0 designers %ere a-le to place circuits %it, ,undreds of gates on a c,ip. T,ese c,ips %ere called 1S' .Medium Scale Integration/ c,ips. 2it, t,e advent of LS' .Large Scale Integration/0 designers could put t,ousands of gates on a single c,ip. At t,is point0 design processes started getting ver# complicated0 and designers felt t,e need to automate t,ese processes. Electronic Design Automation .EDA/[1] tec,ni3ues -egan to evolve. C,ip designers -egan to use circuit and logic simulation tec,ni3ues to verif# t,e functionalit# of -uilding -loc4s of t,e order of a-out 155 transistors. T,e circuits %ere still tested on t,e -read-oard0 and t,e la#out %as done on paper or -# ,and on a grap,ic computer terminal.
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T,e earlier edition of t,e -oo4 used t,e term CAD tools. Tec,nicall#0 t,e term Computer-Aided Design .CAD) tools refers to -ac4-end tools t,at perform functions related to place and route0 and la#out of t,e c,ip . T,e term Computer-Aided Engineering (CAE) tools refers to tools t,at are used for front-end processes suc, !DL simulation0 logic s#nt,esis0 and timing anal#sis. Designers used t,e terms CAD and CAE interc,angea-l#. Toda#0 t,e term Electronic Design Automation is used for -ot, CAD and CAE. $or t,e sa4e of simplicit#0 in t,is -oo40 %e %ill refer to all design tools as EDA tools.

2it, t,e advent of *LS' .Very Large Scale Integration/ tec,nolog#0 designers could design single c,ips %it, more t,an 1550555 transistors. Because of t,e comple6it# of t,ese circuits0 it %as not possi-le to verif# t,ese circuits on a -read-oard. Computer-aided tec,ni3ues -ecame critical for verification and design of *LS' digital circuits. Computer programs to do automatic placement and routing of circuit la#outs also -ecame popular. T,e designers %ere no% -uilding gate-level digital circuits manuall# on grap,ic terminals. T,e# %ould -uild small -uilding -loc4s and t,en derive ,ig,er-level -loc4s from t,em. T,is process %ould continue until t,e# ,ad -uilt t,e top-level -loc4. Logic simulators came into e6istence to verif# t,e functionalit# of t,ese circuits -efore t,e# %ere fa-ricated on c,ip. As designs got larger and more comple60 logic simulation assumed an important role in t,e design

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process. Designers could iron out functional -ugs in t,e arc,itecture -efore t,e c,ip %as designed furt,er. [ Team LiB ] [ Team LiB ]

1.2 Emergence of HDLs

$or a long time0 programming languages suc, as $78T8A90 )ascal0 and C %ere -eing used to descri-e computer programs t,at %ere se3uential in nature. Similarl#0 in t,e digital design field0 designers felt t,e need for a standard language to descri-e digital circuits. T,us0 Hardware Description Languages .!DLs/ came into e6istence. !DLs allo%ed t,e designers to model t,e concurrenc# of processes found in ,ard%are elements. !ard%are description languages suc, as Verilog HDL and *!DL -ecame popular. *erilog !DL originated in 1:;" at <ate%a# Design Automation. Later0 *!DL %as developed under contract from DA8)A. Bot, *erilog= and *!DL simulators to simulate large digital circuits 3uic4l# gained acceptance from designers. Even t,oug, !DLs %ere popular for logic verification0 designers ,ad to manuall# translate t,e !DL-ased design into a sc,ematic circuit %it, interconnections -et%een gates. T,e advent of logic s#nt,esis in t,e late 1:;5s c,anged t,e design met,odolog# radicall#. Digital circuits could -e descri-ed at a register trans er le!el ("#L) -# use of an !DL. T,us0 t,e designer ,ad to specif# ,o% t,e data flo%s -et%een registers and ,o% t,e design processes t,e data. T,e details of gates and t,eir interconnections to implement t,e circuit %ere automaticall# e6tracted -# logic s#nt,esis tools from t,e 8TL description. T,us0 logic s#nt,esis pus,ed t,e !DLs into t,e forefront of digital design. Designers no longer ,ad to manuall# place gates to -uild digital circuits. T,e# could descri-e comple6 circuits at an a-stract level in terms of functionalit# and data flo% -# designing t,ose circuits in !DLs. Logic s#nt,esis tools %ould implement t,e specified functionalit# in terms of gates and gate interconnections. !DLs also -egan to -e used for s#stem-level design. !DLs %ere used for simulation of s#stem -oards0 interconnect -uses0 $)<As .$ield )rogramma-le <ate Arra#s/0 and )ALs .)rogramma-le Arra# Logic/. A common approac, is to design eac, 'C c,ip0 using an !DL0 and t,en verif# s#stem functionalit# via simulation. Toda#0 *erilog !DL is an accepted 'EEE standard. 'n 1::(0 t,e original standard 'EEE 1"+&-1::( %as approved. 'EEE 1"+&- 551 is t,e latest *erilog !DL standard t,at made significant improvements to t,e original standard. [ Team LiB ] [ Team LiB ]

1.3 Typical Design Flow

A t#pical design flo% for designing *LS' 'C circuits is s,o%n in $igure 1-1. >ns,aded -loc4s s,o% t,e level of design representation? s,aded -loc4s s,o% processes in t,e design flo%.

Figure 1-1. Typical Design Flow

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T,e design flo% s,o%n in $igure 1-1 is t#picall# used -# designers %,o use !DLs. 'n an# design0 specifications are %ritten first. Specifications descri-e a-stractl# t,e functionalit#0 interface0 and overall arc,itecture of t,e digital circuit to -e designed. At t,is point0 t,e arc,itects do not need to t,in4 a-out ,o% t,e# %ill implement t,is circuit. A -e,avioral description is t,en created to anal#@e t,e design in terms of functionalit#0 performance0 compliance to standards0 and ot,er ,ig,-level issues. Be,avioral descriptions are often %ritten %it, !DLs.[ ]
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9e% EDA tools ,ave emerged to simulate -e,avioral descriptions of circuits. T,ese tools com-ine t,e po%erful concepts from !DLs and o-Aect oriented languages suc, as CBB. T,ese tools can -e used instead of %riting -e,avioral descriptions in *erilog !DL.

T,e -e,avioral description is manuall# converted to an 8TL description in an !DL. T,e designer ,as to descri-e t,e data flo% t,at %ill implement t,e desired digital circuit. $rom t,is point on%ard0 t,e design process is done %it, t,e assistance of EDA tools.

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Logic s#nt,esis tools convert t,e 8TL description to a gate-level netlist. A gate-level netlist is a description of t,e circuit in terms of gates and connections -et%een t,em. Logic s#nt,esis tools ensure t,at t,e gate-level netlist meets timing0 area0 and po%er specifications. T,e gate-level netlist is input to an Automatic )lace and 8oute tool0 %,ic, creates a la#out. T,e la#out is verified and t,en fa-ricated on a c,ip. T,us0 most digital design activit# is concentrated on manuall# optimi@ing t,e 8TL description of t,e circuit. After t,e 8TL description is fro@en0 EDA tools are availa-le to assist t,e designer in furt,er processes. Designing at t,e 8TL level ,as s,run4 t,e design c#cle times from #ears to a fe% mont,s. 't is also possi-le to do man# design iterations in a s,ort period of time. Be,avioral s#nt,esis tools ,ave -egun to emerge recentl#. T,ese tools can create 8TL descriptions from a -e,avioral or algorit,mic description of t,e circuit. As t,ese tools mature0 digital circuit design %ill -ecome similar to ,ig,-level computer programming. Designers %ill simpl# implement t,e algorit,m in an !DL at a ver# a-stract level. EDA tools %ill ,elp t,e designer convert t,e -e,avioral description to a final 'C c,ip. 't is important to note t,at0 alt,oug, EDA tools are availa-le to automate t,e processes and cut design c#cle times0 t,e designer is still t,e person %,o controls ,o% t,e tool %ill perform. EDA tools are also suscepti-le to t,e C$I$% & $ar'age In $ar'age %utC p,enomenon. 'f used improperl#0 EDA tools %ill lead to inefficient designs. T,us0 t,e designer still needs to understand t,e nuances of design met,odologies0 using EDA tools to o-tain an optimi@ed design.

[ Team LiB ] [ Team LiB ]

1.4 Importance of HDLs

!DLs ,ave man# advantages compared to traditional sc,ematic--ased design. Designs can -e descri-ed at a ver# a-stract level -# use of !DLs. Designers can %rite t,eir 8TL description %it,out c,oosing a specific fa-rication tec,nolog#. Logic s#nt,esis tools can automaticall# convert t,e design to an# fa-rication tec,nolog#. 'f a ne% tec,nolog# emerges0 designers do not need to redesign t,eir circuit. T,e# simpl# input t,e 8TL description to t,e logic s#nt,esis tool and create a ne% gate-level netlist0 using t,e ne% fa-rication tec,nolog#. T,e logic s#nt,esis tool %ill optimi@e t,e circuit in area and timing for t,e ne% tec,nolog#. B# descri-ing designs in !DLs0 functional verification of t,e design can -e done earl# in t,e design c#cle. Since designers %or4 at t,e 8TL level0 t,e# can optimi@e and modif# t,e 8TL description until it meets t,e desired functionalit#. 1ost design -ugs are eliminated at t,is point. T,is cuts do%n design c#cle time significantl# -ecause t,e pro-a-ilit# of ,itting a functional -ug at a later time in t,e gate-level netlist or p,#sical la#out is minimi@ed. Designing %it, !DLs is analogous to computer programming. A te6tual description %it, comments is an easier %a# to develop and de-ug circuits. T,is also provides a concise representation of t,e design0 compared to gate-level sc,ematics. <ate-level sc,ematics are almost incompre,ensi-le for ver# comple6 designs. !DL--ased design is ,ere to sta#.["] 2it, rapidl# increasing comple6ities of digital circuits and increasingl# sop,isticated EDA tools0 !DLs are no% t,e dominant met,od for large digital designs. 9o digital circuit designer can afford to ignore !DL--ased design.

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["]

9e% tools and languages focused on verification ,ave emerged in t,e past fe% #ears. T,ese languages are -etter suited for functional verification. !o%ever0 for logic design0 !DLs continue as t,e preferred c,oice.

[ Team LiB ] [ Team LiB ]

1.5 Popularity of Verilog HDL

*erilog !DL ,as evolved as a standard ,ard%are description language. *erilog !DL offers man# useful features *erilog !DL is a general-purpose ,ard%are description language t,at is eas# to learn and eas# to use. 't is similar in s#nta6 to t,e C programming language. Designers %it, C programming e6perience %ill find it eas# to learn *erilog !DL. *erilog !DL allo%s different levels of a-straction to -e mi6ed in t,e same model. T,us0 a designer can define a ,ard%are model in terms of s%itc,es0 gates0 8TL0 or -e,avioral code. Also0 a designer needs to learn onl# one language for stimulus and ,ierarc,ical design. 1ost popular logic s#nt,esis tools support *erilog !DL. T,is ma4es it t,e language of c,oice for designers. All fa-rication vendors provide *erilog !DL li-raries for postlogic s#nt,esis simulation. T,us0 designing a c,ip in *erilog !DL allo%s t,e %idest c,oice of vendors. T,e )rogramming Language 'nterface .)L'/ is a po%erful feature t,at allo%s t,e user to %rite custom C code to interact %it, t,e internal data structures of *erilog. Designers can customi@e a *erilog !DL simulator to t,eir needs %it, t,e )L'. [ Team LiB ] [ Team LiB ]

1.6 Trends in HDLs

T,e speed and comple6it# of digital circuits ,ave increased rapidl#. Designers ,ave responded -# designing at ,ig,er levels of a-straction. Designers ,ave to t,in4 onl# in terms of functionalit#. EDA tools ta4e care of t,e implementation details. 2it, designer assistance0 EDA tools ,ave -ecome sop,isticated enoug, to ac,ieve a close-to-optimum implementation. T,e most popular trend currentl# is to design in !DL at an 8TL level0 -ecause logic s#nt,esis tools can create gate-level netlists from 8TL level design. Be,avioral s#nt,esis allo%ed engineers to design directl# in terms of algorit,ms and t,e -e,avior of t,e circuit0 and t,en use EDA tools to do t,e translation and optimi@ation in eac, p,ase of t,e design. !o%ever0 -e,avioral s#nt,esis did not gain %idespread acceptance. Toda#0 8TL design continues to -e ver# popular. *erilog !DL is also -eing constantl# en,anced to meet t,e needs of ne% verification met,odologies. (ormal !eri ication and assertion c)ec*ing tec,ni3ues ,ave emerged. $ormal verification applies formal mat,ematical tec,ni3ues to verif# t,e correctness of *erilog !DL descriptions and to esta-lis, e3uivalenc# -et%een 8TL and gate-level netlists. !o%ever0 t,e need to descri-e a design in *erilog !DL %ill not go a%a#. Assertion c,ec4ers allo% c,ec4ing to -e em-edded in t,e 8TL code. T,is is a convenient %a# to do c,ec4ing in t,e most important parts of a design.

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New verification languages have also gained rapid acceptance. These languages combine the parallelism and hardware constructs from HDLs with the object oriented nature of C++. These languages also provide support for automatic stimulus creation, chec ing, and coverage. However, these languages do not replace !erilog HDL. The" simpl" boost the productivit" of the verification process. !erilog HDL is still needed to describe the design. #or ver" high$speed and timing$critical circuits li e microprocessors, the gate$level netlist provided b" logic s"nthesis tools is not optimal. %n such cases, designers often mi& gate$level description directl" into the 'TL description to achieve optimum results. This practice is opposite to the high$ level design paradigm, "et it is fre(uentl" used for high$speed designs because designers need to s(uee)e the last bit of timing out of circuits, and *D+ tools sometimes prove to be insufficient to achieve the desired results. +nother techni(ue that is used for s"stem$level design is a mi&ed bottom$up methodolog" where the designers use either e&isting !erilog HDL modules, basic building bloc s, or vendor$supplied core bloc s to (uic l" bring up their s"stem simulation. This is done to reduce development costs and compress design schedules. #or e&ample, consider a s"stem that has a C,-, graphics chip, %./ chip, and a s"stem bus. The C,- designers would build the ne&t$generation C,- themselves at an 'TL level, but the" would use behavioral models for the graphics chip and the %./ chip and would bu" a vendor$supplied model for the s"stem bus. Thus, the s"stem$level simulation for the C,could be up and running ver" (uic l" and long before the 'TL descriptions for the graphics chip and the %./ chip are completed. 0 Team Li1 2

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