Modeling Structure

Structural architecture
implements the module as a composition of subsystems contains
signal declarations, for internal interconnections
the entity ports are also treated as signals

component instances
instances of previously declared entity/architecture pairs

port maps in component instances

connect signals to component ports

wait statements

Structure Example
d bit d_latch d $ clk bit! d_latch d $ clk bit" d_latch d $ clk bit# d_latch d $ gate and" a y b clk int_clk $

d!

$!

d"

$"

d#

$#

en clk

Structure Example
%irst declare &'latch and and'gate entities and architectures
entity d_latch is port ( d, clk ) in bit* $ ) out bit +* end entity d_latch* architecture basic of d_latch is begin latch_behavior ) process is begin if clk , -!. then $ /, d after " ns* end if* wait on clk, d* end process latch_behavior* end architecture basic* entity and" is port ( a, b ) in bit* y ) out bit +* end entity and"* architecture basic of and" is begin and"_behavior ) process is begin y /, a and b after " ns* wait on a, b* end process and"_behavior* end architecture basic*

Structure Example
0o1 use them to implement a register
architecture struct of reg2 is signal int_clk ) bit* begin bit ) entity 1ork3d_latch(basic+ port map ( d , int_clk, $ +* bit! ) entity 1ork3d_latch(basic+ port map ( d!, int_clk, $! +* bit" ) entity 1ork3d_latch(basic+ port map ( d", int_clk, $" +* bit# ) entity 1ork3d_latch(basic+ port map ( d#, int_clk, $# +* gate ) entity 1ork3and"(basic+ port map ( en, clk, int_clk +* end architecture struct*

 4an.t directly instantiate entity/architecture pair 5nstead include component declarations in structural architecture body
templates for entity declarations

instantiate components 1rite a configuration declaration

binds entity/architecture pair to each instantiated component

Structure Example
%irst declare &'latch and and'gate entities and architectures
entity d_latch is port ( d, clk ) in bit* $ ) out bit +* end d_latch* architecture basic of d_latch is begin latch_behavior ) process begin if clk , -!. then $ /, d after " ns* end if* wait on clk, d* end process latch_behavior* end basic* entity and" is port ( a, b ) in bit* y ) out bit +* end and"* architecture basic of and" is begin and"_behavior ) process begin y /, a and b after " ns* wait on a, b* end process and"_behavior* end basic*

Structure Example
&eclare corresponding components in register architecture body
architecture struct of reg2 is component d_latch port ( d, clk ) in bit* $ ) out bit +* end component* component and" port ( a, b ) in bit* y ) out bit +* end component* signal int_clk ) bit* 333

Structure Example
0o1 use them to implement the register
333 begin bit ) d_latch port map ( d , int_clk, $ +* bit! ) d_latch port map ( d!, int_clk, $! +* bit" ) d_latch port map ( d", int_clk, $" +* bit# ) d_latch port map ( d#, int_clk, $# +* gate ) and" port map ( en, clk, int_clk +* end struct*

Structure Example
4onfigure the register model
configuration basic_level of reg2 is for struct for all ) d_latch use entity 1ork3d_latch(basic+* end for* for all ) and" use entity 1ork3and"(basic+ end for* end for* end basic_level*

Component Declarations
6n architecture body can also make use of other entities described separately and placed in design libraries3 5n order to do this, the architecture must declare a component, 1hich can be thought of as a template defining a virtual design entity, to be instantiated 1ithin the architecture3 7ater, a configuration specification can be used to specify a matching library entity to use3 8he syntax of a component declaration is) component_declaration )), component identifier 9 local_generic_clause : 9 local_port_clause : end component *

Some examples of component declarations) component nand# generic (8pd ) 8ime ), ! ns+* port (a, b, c ) in logic_level* y ) out logic_level+* end component* component read_only_memory generic (data_bits, addr_bits ) positive+* port (en ) in bit* addr ) in bit_vector(depth! downto +* data ) out bit_vector(1idth! downto + +* end component*

8he first example declares a three'input gate 1ith a generic parameter specifying its propagation delay3 &ifferent instances can later be used 1ith possibly different propagation delays3 8he second example declares a readonly memory component 1ith address depth and data 1idth dependent on generic constants3

Component Instantiation
A component defined in an architecture may be instantiated using the syntax: component_instantiation_statement ::= instantiation_label : component_name [ generic_map_aspect ] [ port_map_aspect ] ; This indicates that the architecture contains an instance of the named component, ith actual !alues specified for generic constants, and ith the component ports connected to actual signals or entity ports" The example components declared in the pre!ious section might be instantiated as:

enable_gate) nand# port map (a ,; en!, b ,; en", c ,; int_re$, y ,; interrupt+* parameter_rom) read_only_memory generic map (data_bits ,; !<, addr_bits ,; =+* port map (en ,; rom_sel, data ,; param, addr ,; a(> downto +* 5n the first instance, no generic map specification is given, so the default value for the generic constant 8pd is used3 5n the second instance, values are specified for the address and data port si?es3 0ote that the actual signal associated 1ith the port addr is a slice of an array signal3 8his illustrates that a port 1hich is an array can be connected to part of a signal 1hich is a larger array, a very common practice 1ith bus signals3

4omponent &eclaration
entity FULLADDER is port (A ! CARR"#I$% in bit& 'U( CARR"% out bit)& end FULLADDER& architecture '*RUC* of FULLADDER is signal +#'U( +#CARR", +#CARR"- % bit& component .ALFADDER port (A ! % in bit& 'U( CARR" % out bit)& end component& component /R0A*E port (A ! % in bit& RE' % out bit)& end component& begin 111

4omponent 5nstantiation
architecture S8@A48 of %A776&&E@ is component B67%6&&E@ port (6, C ) in bit* SAM, 46@@D ) out bit+* end component* component E@F68E port (6, C ) in bit* @ES ) out bit+* end component* signal G_SAM, G_46@@D!, G_46@@D") bit*

 begin ME&A7E!) B67%6&&E@ port map( 6, C, G_SAM, G_46@@D! )& ME&A7E") B67%6&&E@ port map ( G_SAM, 46@@D_50, SAM, G_46@@D" )& ME&A7E#) E@F68E port map ( G_46@@D", G_46@@D!, 46@@D )& end S8@A48*

4omponent 5nstantiation) 0amed Signal 6sscociation

entity %A776&&E@ is port (6,C, 46@@D_50) in bit* SAM, 46@@D) out bit+* end %A776&&E@* architecture S8@A48 of %A776&&E@ is component B67%6&&E@ port (6, C ) in bit* SAM, 46@@D ) out bit+* end component* 333 signal G_SAM, G_46@@D!, G_46@@D" ) bit* begin

ME&A7E!) B67%6&&E@ port map ( A 23 A 'U( 23 +#'U( ! 23 ! CARR" 23 +#CARR", +* 333 end S8@A48* left side% 4formals4 (port names from component declaration) right side% 4actuals4 (architecture signals)

$amed association%

Independent of order in component declaration

Ase of generics in constructing parameteri?ed models

architecture generic_delay of halfadder is component xor" is generic (gate_delay) 8ime+* '' new value may be specified here instead of using a generic map() construct port (x, y ) in std_logic* H ) out std_logic+* end component xor"*

component and" is generic (gate_delay) 8ime+* port (x, y ) in std_logic* ? ) out std_logic+* end component and" * begin EI!) xor" generic map (gate_delay ,; < ns+ port map (x ,; x, y ,; y, H ,; sum+* 6 !) and" generic map (gate_delay ,; # ns+ port map(x,; x, y,; y, ?,; carry+* end architecture generic_delay*

1ithin a structural model there are at least t1o 1ays in 1hich the values of generic constants of lo1er'level components can be specified) (i+ in the component declaration, and (ii+ in the component instantiation statement using the generic map( + construct3 5f both are specified, then the value provided by the generic map( + takes precedence3 5f neither is specified, then the default value defined in the model is used3

Jassing generic values through multiple levels of hierarchy

library 5EEE* use 5EEE3std_logic_!!<23all* entity halfadder is generic (gate_delay)8ime), # os+* port (a, b ) in std_logic* sum, carry) out std_logic+* end entity halfadder* architecture generic_delay" of halfadder is component xor" is generic (gate_delay) 8ime+* port (x,y ) in std_logic* ? ) out std_logic+* end component xor"*

component and" is generic (gate_delay) 8ime+* port (x, y ) in std_logic* ? ) out std_logic+* end component and"* begin EI!) xor" generic map (gate_delay ,; gate_delay+ port map(x ,; x, y ,; y, H ,; sum+* 6 !) and" generic map (gate_delay ,; gate_delay+ port map(x,; x, y,; y, ?,; carry+* end architecture generic_delay"*

Summary for generics

8hey are more a means of conveying information through the design hierarchy, thereby enabling component designs to be parameteri?ed3 Fenerics are constant obKects3 8herefore, they cannot be 1ritten, but only read3 8he values of generic parameters must be computable at the time the simulator is loaded 1ith the LB&7 model3 8herefore, 1e may include expressions in the value of a generic parameter3 Bo1ever, the value of this expression must be computable at the time the simulator is loaded3 %inally, 1e must be careful about the precedence of the values of generic obKects, as described in the preced'ing sections3 8he use of generics is not limited to the specification of delays3 5n fact the most po1erful uses of generics deal 1ith physical attributes other than delays3

0' input E@ gate

library 5EEE* use 5EEE3std_logic_!!<23all* entity generic_or is generic (n) positive),"+* port (in! ) in std_logic_vector ((n'!+ do1nto +* ? ) out std_logic+* end entity generic_or* architecture behavioral of generic_or is begin process (in!+ is

variable sum) std_logic), M M* begin sum ), M M* '' on an input signal transition sum must be reset to 0 for i in to (n'! + loop sum ), sum or in! (i+* end loop* ? /, sum* end process* end architecture behavioral*

5f 1e 1ere using several E@ gates in a structural model, 1e 1ould have one instantiation statement for each model3

Each instantiation statement could include the follo1ing statement for different values of n) generic map (n,;#+3 5n this statement the value 1ould be replaced by the number of inputs for that particular gate3 0ote that there is one LB&7 model but 1e can use it to instantiate multiple gates of different input 1idth3

parameteri?ed model of an 0'bit registster

library 5EEE* use 5EEE3std_logic_!!<23all* entity generic_reg is generic (n) positive),"+* port ( clk, reset, enable) in std_logic* d ) in std_logic_vector (n'! do1nto +* $ ) out std_logic_vector (n'! do1nto ++* end entity generic_reg* architecture behavioral of generic_reg is begin

reg_process) process (clk, reset+ is begin if reset , -!. then $ /, (others ,; M M+* elsif (rising_edge(clk++ then if enable , -!. then $/,d* end if* end if* end process reg_process* end architecture behavioral*

4onfigurations
LB&7 language provides configurations for explicitly associating an architecture description 1ith each component in a structural model 8his process of association is referred to as binding an instance of the component to an architecture3

configuration specification
8he configuration specification defines 1here the entity is to be found, 1hat it is called, and ho1 the component ports relate to the entity ports3 the configuration specification is itself optional and can be omitted completely to get all the default options3 8he configuration specification has three parts3 8he first part specifies the components that the configuration applies to3 5n this case, the components are selected by the key1ord all, so all the components called dtype are configured by this specification3 5t 1ould have been possible to have separate configuration specifications for each component separately

8he second part of the configuration selects the entity to use for the component3 8his is kno1n as the entity binding. 8he entity binding must specify 1hich library the entity is in as 1ell as its name3 5n this case the entity is specified as being in the same library as the target circuit, so is referred to by the reserved library name 1ork3 8he entity binding also specifies an architecture to use for the component3 Multiple architectures are rarely used in @87 design, so this aspect is rarely needed3 8he default architecture is, strangely, the most recently compiled architectureN %or single'architecture entities, though, this means that the only architecture present is automatically selected3

8he third part of the configuration specification defines the port bindings3 8hat is, it associates the entity ports 1ith the component ports3 8his allo1s port names to be different in the entity and the component, 8he port binding is optional, and if omitted the component ports are bound to entity ports of the same name3 5f present, then the port binding, enclosed in parentheses, is a list of entity ports associated 1ith their corresponding component ports3

5f the configuration specification is missing completely, then the component is bound to an entity of the same name as the component, in the current 1ork library, and to the architecture most recently analysed, and the ports are bound to the entity ports 1ith the same names3

library 5EEE* library JEGE@* '' a ne1 library use 5EEE3std_logic_!!<23all* entity full_adder is port (5n!, 5n", c_in ) in std_logic* sum, c_out ) out std_logic+* end entity full_adder* architecture structural of full_adder is component halfadder is port (x, y ) in std_logic* sum, carry) out std_logic+* end component halfadder*

component or_" is generic (gate_delay) 8ime), " ns+* port (x, y ) in std_logic* ? ) out std_logic+* end component or_"* signal s!, s", s# ) std_logic* / '' configuration specification for B!) halfadder use entity GE@O3halfadder (behavioral+* for B") halfadder use entity GE@O3halfadder (structural+* for !) or_" use entity JEGE@3lpo" (behavioral+ generic map(gate_delay ,; gate_delay+ port map (!! ,; x, !" ,; y, H,;?+*

begin

'' component instantiation statements

B!) halfadder port map (x ,;ln!, y ,; 5n", sum ,; s!, carry,; s"+* B") halfadder port map (x ,; s!, D ,; c_in, sum ,; sum, carry ,; s"+* o!) or_" port map(x ,; s", y ,; s#, H ,; c_out+* End architecture structural*

5f 1e keep the same names for the entities and the components that are bound to them, then 1e can rely on default rules for configuring the simulation models and no port map clause is re$uired in the configuration statement 8here is some economy of expression that 1e can employ if all of the halfadder components in the circuit use the same entity*architecture pair3 5n this case the t1o component instantiation statements corresponding to B ! and B" can be replaced by a single component instantiation statement as follo1s) %or all) halfadder use entity GE@O3halfadder (behavioral+*

6 configuration declaration
6 configuration declaration is a design unit that allo1s bindings of architecture bodies to entity declarations, as 1ell as bindings of components to design entities, to be specified3 Since a configuration declaration is a separate design unit, these bindings are specified outside of the architecture body3

syntax
configuration_declaration )), configuration identifier of entity_name is for architecture_name P for component_specification binding_Kndication * end for&5 end for& end 6 configuration ! 9 configuration_simple_name : *

8he simplest use of a configuration declaration is to specify the binding of an archi'tecture to a design entity 1hen the architecture is not structural (does not contain any components+3

6 component configuration inside of a component declaration allo1 us to configure the internal structure of the architecture of an entity to 1hich a component is bound* a configuration specification does not allo1 this3

configuration config" of comb ckt is for structural " '' block configuration for ul ) and_" '' component configuration use entity 1ork3and_"(dataflo1+* end for* for u" ) and_" '' component configuration use entity 1ork3and_"(behavioral+* end for* for u# ) or " '' component configuration use entity 1ork3or " (dataflo1+ * end for* end for* end config"*