A project report on

VLSI Design of a
QDR SRAM Controller
By
Amrita Banerjee
Smitha C. Suresh
Titu K. Zaman
Ushasree Boppudi
For the Partial Fulfillment of requirements of the course ECE-758,
VLSI DESIGN-II

Table of Contents
1) Abstract.....3
2) Introduction..4
3) Block Diagram of the QDR SRAM Controller. ...5
4) Hardware Architecture of the QDR SRAM Controller...6
5) VHDL Code..8
6) Synthesis.19
7) Critical path delay..........................................................................20
8) Test Bench ..................................21
9) Simulation...24
10) Schematic Generation38
11) Layout. 44
12) DRC and Overflows45
13) LVS...46
14) IC extraction47
15) Chip Area.48
16) Symbol of the QDR SRAM Controller..49
17) I/O pad bonding...50
18) GDS file.51
19) Summary...52
20) Reference..53

Abstract:
This document describes the interior operation of a QDR SRAM Controller
design that is used to interface between the Host and the QDR SRAM. This document
does attempt to describe rigorously every little detail. It gives an overview of the QDR
SRAM Controller modules inner working by taking examples and going through the
block diagram, timing diagram, schematic circuit description, simulation results, critical
path delay, and physical description including floor plan. All the results are attached to
this document to fulfill the reader demand. The objective of this project is to design a
QDR SRAM Controller that will interface between the Host and the QDR SRAM to read,
write or simultaneous read- write operations from and to QDR SRAM respectively. The
controller is optimized to operate at a frequency of 200MHz (but not lower than
167MHz) using TSMC 0.35m technology. It should have a minimum power
consumption, minimum chip area, minimum pin count and low noise.

Introduction:
Explosive growth of Internet is boosting the demand for high-speed data
communication. SRAMS are widely used in data communication systems, due to their
fast, low latency access to the CPU. The QDR SRAM Controller serves as the interface
between the Host and the QDR SRAM device. And it can be operated at 200MHz speed,
while now a days 167MHz is the working speed.
QDR SRAM controller features the HSTL I/O standards on QDR SRAM side and
LVTTL on Host side. HSTL eliminates the need for external level translators to interface
with high-speed memories. It reduces the over all system design complexity and cost is a
process and technology independent I/O standard. The HSTL nominal logic switching
rang is 0.0V to 1.5V hence faster outputs with reduced power dissipation and minimized
EMI radiation. It provides enhanced flexibility in optimizing system performance with
adjustable trip point (VREF) and output power supply voltage, also improves over all
system performances and hence is ideal for driving address busses to multiple memory
banks.
QDR SRAM stands for Quad Data Rate SRAM. It has separate input and output
ports for both read and write operations so that it can read, write, or simultaneous read
and write operations. Four words can be transferred from and to the QDR SRAM on
every clock cycle, two in the rising edge of the clock and two in the falling edge of the
clock.
There are different types of SRAMs:
a. Asynchronous SRAM.
b. PBSRAM.
c. NoBL SRAM.
d. ZBT SRAM.
Most existing SRAM solutions are relics from the PC time, with interfaces
designed to transfer data efficiently for PC-type single input/output (I/O) applications.
Continuous data transfer between the SRAM and the memory controller is a necessity in
most networking applications. In such applications, there are continuous transitions
between read and write cycles through the memory. Single I/O devices like standard
synchronous Pipelined SRAMs (PBSRAMs) do not perform well in these applications.
The No Bus Latency (NoBL)/Zero Bus Turnaround (ZBT) family of SRAMs have
optimized the synchronous SRAM architecture to allow nolatency in the read/write
transitions and have a 100% utilization of the I/O bus.

For most networking applications, the improvement in throughput provided by the

NoBL/ZBT SRAMs is not enough. With the introduction of QDR SRAM devices,
networking applications such as ATM switches and routers benefit from the simultaneous
Read and Write capabilities. With the absence of latency and the increase in data
throughput provided in the QDR SRAM, simultaneous access to the same address
location is guaranteed.
This was designed particularly for high performance networking systems by the
QDR Consortium, which comprises of Cypress Semiconductor, Integrated Device
Technology, Inc. and Micron Technology. Hitachi, NEC and Samsung became involved
after that.
The separate input and output ports of the QDR memory remove the possibility of
bus contention and simplify the design. Simultaneous reads and writes from both ports
double the throughput over standard DDR SRAMS. With its separate I/O, the QDR
SRAM permits a constant data flow. QDR SRAMs permit operations in frequency
ranges, which previously could not be reached with earlier generations of SRAMs.
QDR SRAM Memory controller finds applications in network equipment like
routers and switches, communications infrastructure equipment such as base stations and
switches, cache memory for things like high-end office equipment and measurement
equipment.

Block Diagram of the QDR SRAM Controller

Hardware Architecture of QDR SRAM Controller

The QDR SRAM controller generates four output clock K, Kn, C, Cn and also
some internal clocks for read and write operations. In the first clock cycle, QDR_R and
QDR_W are both asserted active low. The address for the read (A) is latched on the
rising edge of the K clock and the address for the write (B) is latched on the rising edge
of the Kn clock. The data for the write to address B is also latched on the rising edges of
K clock (D[B]) and Kn clock.
Read access to the QDR is conducted in two cycles (two-stage pipeline). During
the first cycle the address is latched on the rising edge of K clock. The address is then
presented to the memory. The next rising edge of C clock out the first 18-bit data word
(Q[A]). The next rising edge of Cn clocks out the second 18-bit data word (Q[A+1]).
As seen from the timing diagram, the QDR read and write can start to the same
address on the same cycle. When such an operation occurs, the QDR forwards the write
operation to the write port and ensures that valid data is driven out on the data bus. This
operation guarantees data coherency.
Figure shows the performance comparison of the QDR against other SRAMs.
The comparison was done assuming that all the interfaces operate at 166 MHz. The
figure shows that the QDR performance is far ahead of all other SRAMs and the
performance four times the closest device in a networking application.

State Machine of the QDR SRAM Controller

Cmd=00
Latch R
address

Decode CMD
/R address
(20, 19)

Latch W
address/
W data

Cmd =
01

/RPS(x)
On K

Wait

Cmd=1
0

/RPS(x)
On K

Cmd = 11
Write

Read
A(0:17)=Raddr
ess(0:17) On K

Decode
CMD /W
address (20,
19)

Read/Wr
ite

A(0:17)=W
address(0:17)
On K

R data (0:17)= data

(0:17)
on C

Data (0:17) =W data

(0:17)
on C

R data(33:18)=
data (0:17) on / C

Data (33:18) =W
data (0:17) on / C

Read Write Timing Diagram of QDR SRAM Controller

Functional Description of QDR SRAM Controller

QDR SRAM devices support two-word data transfers on all write and read
transactions. When Host sends a Cmd[01], Cmd[10], and Cmd[11] the QDR SRAM
Controller does read, write, and simultaneous read-write operations from and to QDR
SRAM respectively.
Write Cycle: On the rising edge of the Kn clock, the device latches the write
address and control signals QDR_W and the next rising edge of the K clock, it writes
the lower word to QDR SRAM and the rising edge of the Kn clock it writes the upper
word to QDR SRAM, thus completing a write cycle.
Read Cycle: on the rising edge of K clock, the device latches the control
signal read address A and control signal QDR_R and the next rising edge of the C
clock, it reads the lower word from QDR SRAM and the rising edge of the Cn clock
it reads the upper word from QDR SRAM, thus completing a read cycle.
Read/Write Cycle: When a read request and write request occurs
simultaneously at the read address and write, the data is read from QDR SRAM and
write to the QDR SRAM through the independent read write ports.

10

VHDL Code:
Top level QDR SRAM Controller:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity QDR_TOP is
Port (HOST_CLK: in std_logic;
HOST_DWL: in std_logic_vector(17 downto 0);
HOST_DWH: in std_logic_vector(17 downto 0);
HOST_DRL: out std_logic_vector(17 downto 0);
HOST_DRH: out std_logic_vector(17 downto 0);
HOST_A_R: in std_logic_vector(17 downto 0);
HOST_A_W: in std_logic_vector(17 downto 0);
CMD_RW: in std_logic_vector(1 downto 0);
RST: in std_logic;
QDR_K_CLK: out std_logic;
QDR_Kn_CLK: out std_logic;
QDR_C_CLK: out std_logic;
QDR_Cn_CLK: out std_logic;
QDR_A_RD: out std_logic_vector(17 downto 0);
QDR_A_WR: out std_logic_vector(17 downto 0);
QDR_WD_BW0: out std_logic_vector(17 downto 0);
QDR_WD_BW1: out std_logic_vector(17 downto 0);
QDR_D_R: in std_logic_vector(17 downto 0);
QDR_W: out std_logic;
QDR_R: out std_logic);
end QDR_TOP;
architecture RTL of QDR_TOP is
--***********************************************
--* Components declaration
--***********************************************
component ADD_GEN
Port (CLK90: in std_logic;
ADD_R: in std_logic_vector(17 downto 0);
ADD_W: in std_logic_vector(17 downto 0);
CMD_R: in std_logic;
CMD_W: in std_logic;
RST: in std_logic;
LOCK_PLL: in std_logic;
QDR_RD_A: out std_logic_vector(17 downto 0);
QDR_WR_A: out std_logic_vector(17 downto 0));
end component;

11

component CLK_GENERATE
Port (CLKIN: in std_logic;
RST: in std_logic;
CLK0: out std_logic;
CLK90: out std_logic;
K_CLK: out std_logic;
Kn_CLK: out std_logic;
C_CLK: out std_logic;
Cn_CLK: out std_logic;
CLK_LOCKED: out std_logic);
end component;
component WRITE_BURST
Port (CLK90: in std_logic;
D0: in std_logic_vector(17 downto
D1: in std_logic_vector(17 downto
CMD_W: in std_logic;
RST: in std_logic;
LOCK_PLL: in std_logic;
Q_WD_BW0: out std_logic_vector(17
Q_WD_BW1: out std_logic_vector(17
end component;

0);
0);

downto 0);
downto 0));

component READ_BURST
Port (C_CLK: in std_logic;
CLK90: in std_logic;
D: in std_logic_vector(17 downto 0);
CMD_R: in std_logic;
RST: in std_logic;
Q0: out std_logic_vector(17 downto 0);
Q1: out std_logic_vector(17 downto 0));
end component;
component CTRL_RW
Port (CMD_W: in std_logic;
CMD_R: in std_logic;
RST: in std_logic;
W_CYCLE_GEN: out std_logic;
R_CYCLE_GEN: out std_logic);
end component;
--***********************************************
--* Signals declaration
--***********************************************
signal CLK0: std_logic;
signal CLK90: std_logic;
signal K_C_LOCK: std_logic;
begin
ADD_W_R: ADD_GEN port map (CLK90 => CLK90,
ADD_W => HOST_A_W,
ADD_R => HOST_A_R,
CMD_W => CMD_RW(1),
CMD_R => CMD_RW(0),

12

RST => RST,

LOCK_PLL => K_C_LOCK,
QDR_RD_A => QDR_A_RD,
QDR_WR_A => QDR_A_WR);
IN_OUT_CLK: CLK_GENERATE port map (CLKIN => HOST_CLK,
RST => RST,
CLK0 => CLK0,
CLK90 => CLK90,
K_CLK => QDR_K_CLK,
Kn_CLK => QDR_Kn_CLK,
C_CLK => QDR_C_CLK,
Cn_CLK => QDR_Cn_CLK,
CLK_LOCKED => K_C_LOCK);
WRITE_D_H_L: WRITE_BURST port map (CLK90 => CLK90,
D0 => HOST_DWL,
D1 => HOST_DWH,
CMD_W => CMD_RW(1),
RST => RST,
LOCK_PLL => K_C_LOCK,
Q_WD_BW0 => QDR_WD_BW0,
Q_WD_BW1 => QDR_WD_BW1);
READ_D_H_L: READ_BURST port map (C_CLK => CLK0,
CLK90 => CLK90,
D => QDR_D_R,
CMD_R => CMD_RW(0),
RST => RST,
Q0 => HOST_DRL,
Q1 => HOST_DRH);
CTRL_W_R_OP: CTRL_RW port map (CMD_W => CMD_RW(1),
CMD_R => CMD_RW(0),
RST => RST,
W_CYCLE_GEN => QDR_W,
R_CYCLE_GEN => QDR_R);
end RTL;

13

Lower level components:

Address Generator:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ADD_GEN is
Port (CLK90: in std_logic;
ADD_W: in std_logic_vector(17 downto 0);
ADD_R: in std_logic_vector(17 downto 0);
CMD_W: in std_logic;
CMD_R: in std_logic;
RST: in std_logic;
LOCK_PLL: in std_logic;
QDR_RD_A: out std_logic_vector(17 downto 0);
QDR_WR_A: out std_logic_vector(17 downto 0));
end ADD_GEN;
architecture RTL of ADD_GEN is
--***********************************************
--* Components declaration
--***********************************************
component ASYNR_DFF
port(CLK: in std_logic;
D: in std_logic;
RST: in std_logic;
Q : out std_logic);
end component;
component ASYNR_DFF18
port(CLK: in std_logic;
D: in std_logic_vector(17 downto 0);
RST: in std_logic;
Q : out std_logic_vector(17 downto 0));
end component;
component SDR_MUX18
port(CLK: in std_logic;
D: in std_logic_vector(17 downto 0);
CE: in std_logic;
RST: in std_logic;
Q: out std_logic_vector(17 downto 0));
end component;
--***********************************************
--* Signals declaration
--***********************************************
signal CLK270: std_logic;
signal A_W_DELAY: std_logic_vector(17 downto 0);

14

signal
signal
signal
signal
signal
begin

C_W_DELAY: std_logic;
A_R_LATCH: std_logic_vector(17 downto 0);
A_W_LATCH: std_logic_vector(17 downto 0);
QDR_A_R: std_logic_vector(17 downto 0);
QDR_A_W: std_logic_vector(17 downto 0);

CLK270 <= not CLK90;

QDR_RD_A <= QDR_A_R;
QDR_WR_A <= QDR_A_W;
W_A_DELAY: ASYNR_DFF18 port map(CLK => CLK90,
D => ADD_W,
RST => RST,
Q => A_W_DELAY);
W_C_DELAY: ASYNR_DFF port map(CLK => CLK90,
D => CMD_W,
RST => RST,
Q => C_W_DELAY);
R_A_LATCH: SDR_MUX18 port map(CLK => CLK90,
D => ADD_R,
CE => LOCK_PLL,
RST => RST,
Q => A_R_LATCH);
W_A_LATCH: SDR_MUX18 port map(CLK => CLK270,
D => A_W_DELAY,
CE => LOCK_PLL,
RST => RST,
Q => A_W_LATCH);
R_A_BUFFER: SDR_MUX18 port map(CLK => CLK90,
D => A_R_LATCH,
CE => CMD_R,
RST => RST,
Q => QDR_A_R);

W_A_BUFFER: SDR_MUX18 port map(CLK => CLK270,

D => A_W_LATCH,
CE => C_W_DELAY,
RST => RST,
Q => QDR_A_W);
end RTL;

15

Clock Generator:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CLK_GENERATE is
Port (CLKIN: in std_logic;
RST: in std_logic;
CLK0: out std_logic;
CLK90: out std_logic;
K_CLK: out std_logic;
Kn_CLK: out std_logic;
C_CLK: out std_logic;
Cn_CLK: out std_logic;
CLK_LOCKED: out std_logic);
end CLK_GENERATE;
architecture RTL of CLK_GENERATE is
--***********************************************
--* Signals and constants declaration
--***********************************************
signal
signal
signal
signal
signal
signal
signal
begin

CLK_0: std_logic := '0';

CLK_90: std_logic := '0';
CLK_1X: std_logic := '0';
LOCKED_DLL: std_logic := '0';
clk_buf: std_logic := '0';
clk_fbbuf: std_logic := '0';
clk_100: std_logic := '0';

clk_buf <= CLKIN;

clk_fbbuf <= CLK_1X;
process (RST,clk_buf,clk_100)
begin
if(RST = '0')then
CLK_0 <= '0';
CLK_90 <= '0';
CLK_1X <= '0';
else
clk_100 <= clk_buf after 2.5 ns;
CLK_0 <= clk_buf xor clk_100;
CLK_90 <= (clk_buf xor clk_100) after 1.25 ns;
CLK_1X <= clk_buf;
end if;
end process;
process (RST,clk_buf,clk_fbbuf)
begin
if(RST = '0')then

16

else

LOCKED_DLL <= '0';

if(clk_buf = clk_fbbuf)then
LOCKED_DLL <= '1';
end if;
end if;
end process;
CLK0 <= CLK_0;
CLK90 <= CLK_90;
K_CLK <= CLK_90;
Kn_CLK <= not (CLK_90);
C_CLK <= CLK_0;
Cn_CLK <= not (CLK_0);
CLK_LOCKED <= LOCKED_DLL;
end RTL;

17

Control Write:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_RW is
Port (CMD_W: in std_logic;
CMD_R: in std_logic;
RST: in std_logic;
W_CYCLE_GEN: out std_logic;
R_CYCLE_GEN: out std_logic);
end CTRL_RW;
architecture RTL of CTRL_RW is
--***********************************************
--* Signals and constants declaration
--***********************************************
signal w_cycle: std_logic;
signal r_cycle: std_logic;
begin
r_cycle <= '1'
w_cycle <= '1'
W_CYCLE_GEN <=
R_CYCLE_GEN <=
end RTL;

when (RST = '1' and CMD_R = '1') else '0';

when (RST = '1' and CMD_W = '1') else '0';
not w_cycle;
not r_cycle;

18

Read Burst:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity READ_BURST is
Port (C_CLK: in std_logic;
CLK90: in std_logic;
D: in std_logic_vector(17 downto 0);
CMD_R: in std_logic;
RST: in std_logic;
Q0: out std_logic_vector(17 downto 0);
Q1: out std_logic_vector(17 downto 0));
end READ_BURST;
architecture RTL of READ_BURST is
--***********************************************
--* Components declaration
--***********************************************
component ASYNR_DFF
port(CLK: in std_logic;
D: in std_logic;
RST: in std_logic;
Q : out std_logic);
end component;
component ASYNR_DFF18
port(CLK: in std_logic;
D: in std_logic_vector(17 downto 0);
RST: in std_logic;
Q : out std_logic_vector(17 downto 0));
end component;
--***********************************************
--* Signals and constants declaration
--***********************************************
signal C_CLK_BAR : std_logic;
signal CLK270: std_logic;
signal C_RD: STD_LOGIC;
begin

CLK270 <= not CLK90;

C_CLK_BAR <= not(C_CLK);
C_DELAY1: ASYNR_DFF port map(CLK => CLK270,
D => CMD_R,
RST => RST,
Q => C_RD);

19

RD_FDC_D0_C: ASYNR_DFF18 port map(CLK => C_CLK,

D => D,
RST => C_RD,
Q => Q0);
RD_FDC_D1_C: ASYNR_DFF18 port map(CLK => C_CLK_BAR,
D => D,
RST => C_RD,
Q => Q1);
end RTL;

20

Write Burst:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity WRITE_BURST is
Port (CLK90: in std_logic;
D0: in std_logic_vector(17 downto
D1: in std_logic_vector(17 downto
CMD_W: in std_logic;
RST: in std_logic;
LOCK_PLL: in std_logic;
Q_WD_BW0: out std_logic_vector(17
Q_WD_BW1: out std_logic_vector(17
end WRITE_BURST;

0);
0);

downto 0);
downto 0));

architecture RTL of WRITE_BURST is

--***********************************************
--* Components declaration
--***********************************************
component ASYNR_DFF
port(CLK: in std_logic;
D: in std_logic;
RST: in std_logic;
Q : out std_logic);
end component;
component SDR_MUX18
port (CLK: in std_logic;
D: in std_logic_vector(17 downto 0);
CE: in std_logic;
RST: in std_logic;
Q: out std_logic_vector(17 downto 0));
end component;

21

Asynchronous D flip-flop:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ASYNR_DFF is
Port (CLK: in std_logic;
D: in std_logic;
RST: in std_logic;
Q: out std_logic);
end ASYNR_DFF;
architecture RTL of ASYNR_DFF is
begin
process (CLK,RST)
begin
if(RST = '0')then
Q <= '0';
elsif(CLK'event and CLK = '1')then
Q <= D;
end if;
end process;
end RTL;

22

18- bit Asynchronous D flip- flop:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ASYNR_DFF18 is
Port (CLK: in std_logic;
D: in std_logic_vector(17 downto 0);
RST: in std_logic;
Q: out std_logic_vector(17 downto 0));
end ASYNR_DFF18;
architecture RTL of ASYNR_DFF18 is
begin
process (CLK,RST)
begin
if(RST = '0')then
Q <= "000000000000000000";
elsif(CLK'event and CLK = '1')then
Q <= D;
end if;
end process;
end RTL;

23

18- bit SDR- multiplexer:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SDR_MUX18 is
Port (CLK: in std_logic;
D: in std_logic_vector(17 downto 0);
CE: in std_logic;
RST: in std_logic;
Q: out std_logic_vector(17 downto 0));
end SDR_MUX18;
architecture RTL of SDR_MUX18 is
begin
process (CLK)
begin
if(CLK'event and CLK = '1')then
if(RST = '0')then
Q <= "000000000000000000";
elsif(CE = '1')then
Q <= D;
end if;
end if;
end process;
end RTL;

24

Synthesis:

25

Critical path:

26

Critical path report:

27

VHDL Test- Bench:

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
entity QDR_TB is
end QDR_TB;
architecture RTL of QDR_TB is
component QDR_TOP
Port(
HOST_CLK : in std_logic;
HOST_DWL : in std_logic_vector(17 downto 0);
HOST_DWH : in std_logic_vector(17 downto 0);
HOST_A_R : in std_logic_vector(17 downto 0);
HOST_A_W : in std_logic_vector(17 downto 0);
CMD_RW : in std_logic_vector(1 downto 0);
RST : in std_logic;
QDR_D_R : in std_logic_vector(17 downto 0);
HOST_DRL : OUT std_logic_vector(17 downto 0);
HOST_DRH : OUT std_logic_vector(17 downto 0);
QDR_K_CLK : OUT std_logic;
QDR_Kn_CLK : OUT std_logic;
QDR_C_CLK : OUT std_logic;
QDR_Cn_CLK : OUT std_logic;
QDR_A_RD : OUT std_logic_vector(17 downto 0);
QDR_A_WR : OUT std_logic_vector(17 downto 0);
QDR_WD_BW0 : OUT std_logic_vector(17 downto 0);
QDR_WD_BW1 : OUT std_logic_vector(17 downto 0);
QDR_W : OUT std_logic;
QDR_R : OUT std_logic
);
end component;
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal
signal

HOST_CLK : std_logic;
HOST_DWL : std_logic_vector(17 downto 0);
HOST_DWH : std_logic_vector(17 downto 0);
HOST_DRL : std_logic_vector(17 downto 0);
HOST_DRH : std_logic_vector(17 downto 0);
HOST_A_R : std_logic_vector(17 downto 0);
HOST_A_W : std_logic_vector(17 downto 0);
CMD_RW : std_logic_vector(1 downto 0);
RST : std_logic;
QDR_K_CLK : std_logic;
QDR_Kn_CLK : std_logic;
QDR_C_CLK : std_logic;
QDR_Cn_CLK : std_logic;
QDR_A_RD : std_logic_vector(17 downto 0);
QDR_A_WR : std_logic_vector(17 downto 0);
QDR_WD_BW0 : std_logic_vector(17 downto 0);
QDR_WD_BW1 : std_logic_vector(17 downto 0);
QDR_D_R : std_logic_vector(17 downto 0);

28

signal QDR_W :
signal QDR_R :

std_logic;
std_logic;

begin
DUT: QDR_TOP Port map(
HOST_CLK => HOST_CLK,
HOST_DWL => HOST_DWL,
HOST_DWH => HOST_DWH,
HOST_DRL => HOST_DRL,
HOST_DRH => HOST_DRH,
HOST_A_R => HOST_A_R,
HOST_A_W => HOST_A_W,
CMD_RW => CMD_RW,
RST => RST,
QDR_K_CLK => QDR_K_CLK,
QDR_Kn_CLK => QDR_Kn_CLK,
QDR_C_CLK => QDR_C_CLK,
QDR_Cn_CLK => QDR_Cn_CLK,
QDR_A_RD => QDR_A_RD,
QDR_A_WR => QDR_A_WR,
QDR_WD_BW0 => QDR_WD_BW0,
QDR_WD_BW1 => QDR_WD_BW1,
QDR_D_R => QDR_D_R,
QDR_W => QDR_W,
QDR_R => QDR_R
);
--***********************************************
-- Generate clock for the simulation
--***********************************************
process
begin
HOST_CLK <= '1';
wait for 5 ns;
HOST_CLK <= '0';
wait for 5 ns;
end process;
--***********************************************
-- Initialization
--***********************************************
process
begin
HOST_DWL <= "000000000000000000";
HOST_DWH <= "000000000000000000";
HOST_A_R <= "000000000000000000";
HOST_A_W <= "000000000000000000";
CMD_RW <= "00";
RST <= '0';
QDR_D_R <= "000000000000000000";
wait for 200 ns;

29

RST <= '1';

wait for 200 ns;
--***********************************************
-- Generate test vectors
--***********************************************
HOST_DWL <= "000000000000001111";
HOST_DWH <= "111100000000000000";
HOST_A_R <= "000000000000000011";
HOST_A_W <= "000000000000001100";
QDR_D_R <= "000011110000111100";
wait for 200 ns;
CMD_RW <= "01";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
HOST_DWL <= "000000000000001111";
HOST_DWH <= "111100000000000000";
HOST_A_R <= "000000000000010011";
HOST_A_W <= "000000000000001100";
QDR_D_R <= "111100001111000000";
wait for 200 ns;
CMD_RW <= "01";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
HOST_DWL <= "000000000000001111";
HOST_DWH <= "111100000000000000";
HOST_A_R <= "000000000000100011";
HOST_A_W <= "000000000000001100";
QDR_D_R <= "110000001100000000";
wait for 200 ns;
CMD_RW <= "01";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
CMD_RW <= "10";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
HOST_DWL
HOST_DWH
HOST_A_R
HOST_A_W

<=
<=
<=
<=

"000000000011001111";
"111100110000000000";
"000000000000100011";
"000000000011001100";

30

QDR_D_R <= "110000001100000000";

wait for 200 ns;
CMD_RW <= "10";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
HOST_DWL <= "100000000000000001";
HOST_DWH <= "011111111111111110";
HOST_A_R <= "000000000000100011";
HOST_A_W <= "000000001100001100";
QDR_D_R <= "110000001100000000";
wait for 200 ns;
CMD_RW <= "10";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
HOST_DWL <= "000000000000001111";
HOST_DWH <= "111100000000000000";
HOST_A_R <= "000000000000000011";
HOST_A_W <= "000000000000001100";
QDR_D_R <= "000011110000111100";
wait for 200 ns;
CMD_RW <= "11";
wait for 200 ns;
CMD_RW <= "00";
wait for 200 ns;
HOST_DWL <= "000000000011001111";
HOST_DWH <= "111100000000110000";
HOST_A_R <= "000000000000110011";
HOST_A_W <= "000000000011001100";
QDR_D_R <= "000000001100001100";
wait for 200 ns;
CMD_RW <= "11";
wait for 200 ns;
CMD_RW <= "00";
wait for 500 ns;
end process;
end RTL;

31

Simulation:
Clock Generator:

32

Read operation:

33

Write operation:

34

Read/ Write operation:

35

Idle or no operation:

36

VLSI Design
Schematic Generation
This is the schematic of the QDR top level design. The schematics of the subblocks of the QDR SRAM controller are in the following pages.

37

Address Generator:

38

Clock Generator:

Control Read/Write:
39

Read Burst:

40

Write Burst:
41

42

Layout of the QDR SRAM Memory Controller:

The layout of the QDR SRAM Controller is shown below.

43

DRC Errors and Overflows:

The layout has no DRC errors and overflows.

44

LVS:
Below is our present LVS report.

45

IC extraction:
IC extraction is an IC Station tool that obtains information from an IC layout
about parasitic resistance and parasitic capacitances.
Since the IC extraction depends entirely on the LVS, IC extraction could not be finished.
The following steps are followed for IC extraction:

Choose IC EXTRACT (M) from the IC window.

Choose Lumped capacitances in the window.
Select Write Netlist, input name for filename with .sp extension.
Then type GND.
The Lumped capacitances will be extracted from the layout.
The resulting netlist can be used to simulate in Hspice and AWAVES with
some modifications.

The IC Extraction work is in progress

46

Chip Area
The area of the chip is calculated by measuring length and height:
Length of the chip: 3338m
Height of the chip: 2764m
AREA of the chip = 9256192 m-sq

47

Symbol of the Top Level QDR SRAM Controller

The symbol of the QDR SRAM Controller is shown below. The input and output
pins are shown in the following symbol.

48

I/O pad bonding

One implementation issue that is worthy of consideration is the use of
standardized structures on the VLSI chip to ease interface with the outside world. The
most common standard structures are the bonding pads, which are provided for each
design environment. Use of such pads does more than relieve the designer from bonding
considerations such as pad layers and spacing. These standard pads often have necessary
circuitry for static protection, TTL driving, and all the analog considerations that are not
needed elsewhere on the chip. Thus the digital designer can view VLSI systems in a
purely logical sense by using standard parts for the non-digital interface.

49

Steps Required for I/O bonding

1. Go to ADK library.
2. Click on Inst.
3. The Schematic will pop- up in a new window. All parts of the schematic have to
be selected. Then the layout will be highlighted.
4. Now go the ADK. Click on generate pad frame and then TSMC 0.35.
5. Then to view the entire cell click Shift- F8.
6. The layout will be obtained with the bonding.
7. Then the connections have to be made.

50

GDS File:
After the DRC, LVS, I/O pad bonding is finished, GDS file is obtained.
Following steps are required to get GDS file:
1. Go to Translate.
2. Click on write GDS II.
3. Give the name of the cell.
4. Give path and a name for output GDS file.
5. Give the path name of the log file which will be same as the
layout name but with .gds extension.
6. At the place of cell name, give the path of the map file.
7. After the above steps are followed, the gds file is obtained.

51

Summary:
- The design operates at 200 MHz.
- VHDL code is simulated using Modelsim and synthesized successfully
using Leonardo spectrum.
- Schematic Generation is done for QDR top level design and for all the sub-blocks
using mentor graphics tools.
- Place and Route is finished successfully using Mentor Graphics tools to use
TSMC .35um technology.
- The chip area and critical path delay is calculated.
- There are no overflows and DRC errors in the QDR top level design.
- LVS and IC extraction is in progress.

52

Reference:

QDR Consortium: http://www.qdrsram.com

QDR II SRAM Memory Device Vendors
1. Cypress Semiconductor: http://www.cypress.com/
2. Renesas Technology: http://www.renesas.com/
3. IDT, Inc.: http://www.idt.com/
4. Samsung Semiconductor: http://www.samsung.com/
5. NEC Corporation: http://www.ic.nec.co.jp/memory/index_e.html/

53