DIT/SMDP-II Required/Essential/Necessary Books VLSI Fabrication Technology 1. S. K. and!

i" VLSI Fabrication Principles : Silicon and Gallium Arsenide" Second Edition"#iley" 1$$%. &. . S. May and S. M. S'e" Fundamentals of Semiconductor Fabrication"#iley" &((%. ). *. D. Plu++er" M. D. Deal and P. B. ri,-n" Silicon VLSI Technology : Fundamentals, Practice and odeling" Pearson/P." &((1. %. P. /an 0ant" icrochip Fabrication : A Practical Guide to Semicondutor Processing" 1i,t! Edition" Mc ra2-.ill" &((%. 34!ea5 Edition6 Semiconductor Devices, Device Modeling and Simulation, SPICE 7. B. 8. 9nderson and R. 8. 9nderson" Fundamentals of Semiconductor !e"ices" Mc ra2.ill" &((%. :. D. 1oty" #SF$T odeling %ith SPI&$ : Principles and Practices" Prentice-.all" 1$$;. ;. #. 8iu" #SF$T odels for SPI&$ Simulation Including 'SI ("( and 'SI )" #iley" &((1. <. R. S. Muller" T. I. Ka+ins and M. 4!an" !e"ice $lectronics for Integrated &ircuits" T!ird Edition"#iley" &((). 34!ea5 Edition6 $. . #. Ro=erts and 9. S. Sedra" SPI&$" Second Edition" >?P" 1$$:. 34!ea5 Edition6 1(. 9. S. Sedra and K. 4. S+it!" icroelectronic &ircuits" 1i,t! Edition" >?P" &((). 34!ea5 Edition6 11. B. . Street+an and S. Baner@ee" Solid State $lectronic !e"ices" SiAt! Edition" P.I" &((7. 34!ea5 Edition6 1&. 9. /ladi+irescu" The SPI&$ 'oo*" #iley" 1$$%. VLSI Design, VLSI Subsystem Design 1). R. *. Baker" & #S : &icuit !esign, Layout and Simulation" Second Edition" #iley" &((%. 34!ea5 Edition B6 1%. *-P. Desc!a+5s" . *. 9. Bioul and . D. Sutter" Synthesis of Arithmetic &ircuits : FPGA, ASI& and $mbedded Systems" #iley" &((:. 17. S-M. KanC and D. 8e=le=ici" & #S !igital Integrated &ircuits : Analysis and !esign" T!ird Edition" Mc ra2-.ill" &((&. 34!ea5 Edition6 1:. 4. Mead and 8. 4on2ay" Introduction to VLSI Systems" 9ddison-#esley" 1$<(. 3>ut o, Print6 May" &((: c 4EERI" Pilani 1 DIT/SMDP-II Required/Essential/Necessary Books 1;. *. M. Ra=aey" 9. 4!andrakasan and B. Nikolic" !igital Integrated &ircuits : A !esign Perspecti"e" Second Edition" Pearson/P." &((). 34!ea5 Edition6 1<. *. P. ?ye+ura" Introduction to VLSI &ircuits and Systems" #iley" &((1. 1$. *. P. ?ye+ura" & #S Logic &ircuit !esign" Second Edition" Klu2er" 1$$$. 34!ea5 Edition6 &(. 8. #an!a++ar" !SP Integrated &ircuits" 9P" 1$$$. &1. N. #este" D. .arris and S. Baner@ee" & #S VLSI !esign : A &ircuits and Systems

Perspecti"e" T!ird Edition" Pearson/9#" &((7. 34!ea5 Edition6 &&. #.#ol," odern VLSI !esign : Systems+on+&hip !esign" T!ird Edition" Pearson/P." &((&. 34!ea5 Edition6 SIC Design, FP! Design, "econ#gurable Com$uting &). ?. Meyer-Baese" !igital Signal Processing %ith Field Programmable Gate Arrays" S5rinCer" &((1. &%. *. /. >ld-eld and R. 4. Dor," FPGAs : ,econ-gurable Logic for ,apid Prototyping and Implementation of !igital Systems" #iley" 1$$7. &7. M. *. S. S+it!" Application Speci-c Integrated &ircuits" Pearson/9#" 1$$;. 34!ea5 Edition6 &:. #. #ol," FPGA+based System !esign" P./Pearson" &((%. 34!ea5 Edition6 nalog IC Design, Mi%ed Signal Design, "F IC Design &;. 9. 9Car2al and *. 8anC" Foundations of Analog and !igital $lectronic &ircuits" ElseEier/ MK" &((7. &<. P. E. 9llen and D. R. .ol=erC" & #S Analog &ircuit !esign" Second Edition" >?P" &((&. &$. 4. En' and E. /itto'" &harge+'ased #S Transistor odeling : The $.V odel for Lo%+Po%er and ,F I& !esign" #iley" &((:. )(. P. ray" P. *. .urst" S. .. 8e2is and R. Meyer" Analysis and !esign of Analog Integrated &ircuits" 1ourt! Edition"#iley" &((1. 34!ea5 Edition6 )1. R. reCorian and . 4. Te+es" Analog #S Integrated &ircuits for Signal Processing" #iley" 1$<:/&((&. 34!ea5 Edition6 )&. 9. .astinCs" The Art of Analog Layout" Second Edition" Prentice-.all" &((:. )). D. 9. *o!ns and K. Martin" Analog Integrated &ircuit !esign" #iley" 1$$;. May" &((: c 4EERI" Pilani & DIT/SMDP-II Required/Essential/Necessary Books )%. K. R. 8aker and #. M. 4. Sansen" !esign of Analog Integrated &ircuits and Systems" Mc ra2-.ill" 1$$%. 34!ea5 Edition6 )7. T. .. 8ee" !esign of & #S ,adio Fre/uency Integrated &ircuits" Second Edition" 4?P" &((%. 34!ea5 Edition B6 ):. B. Ra'aEi" !esign of Analog & #S Integrated &ircuits" Mc ra2-.ill" &(((. );. R. *. Ean de Plassc!e" Integrated A+! and !+A &on"erters" Second Edition" S5rinCer/Klu2er" &((). 34!ea5 Edition6 VLSI Systems rchitecture, Com$uter rchitecture, DSP rchitecture )<. . 9. Blaau2 and 1. P. Brooks" &omputer Architecture : &oncepts and $"olution" Pearson/9#" 1$$;. )$. /. P. .eurinC and .. 1. *ordan" &omputer Systems !esign and Architecture" Second Edition" P.I" &((%. 34!ea5 Edition6 %(. D. 9. Patterson and *. 8. .ennessy" &omputer Architecture : A 0uantitati"e Approach" 1ourt! Edition" ElseEier/MK" &((:. 3To 955ear6

%1. D. 9. Patterson and *. 8. .ennessy" &omputer Architecture : A 0uantitati"e Approach" T!ird Edition" ElseEier/MK" &((&. 34!ea5 Edition6 %&. D. 9. Patterson and *. 8. .ennessy" &omputer #rgani1ation and !esign : 2ard%are3 Soft%are Interface" T!ird Edition" ElseEier/MK" &((%. 34!ea5 Edition6 %). #. StallinCs" &omputer #rgani1ation and Architecture : !esigning for Performance" SeEent! Edition" Pearson/P." &((:. 34!ea5 Edition6 %%. 9. S. Tanen=au+" Structured &omputer #rgani1ation" 1i,t! Edition" Pearson/P." &((:. 34!ea5 Edition6 %7. #.#ol," odern VLSI !esign : Systems+on+&hip !esign" T!ird Edition" Pearson/P." &((&. 34!ea5 Edition6 %:. S. M. Kuo and #-S. S. an" !igital Signal Processors : Architectures, Implementations, and Applications" Prentice-.all" &((%. %;. P. 8a5sley" *. Bier" 9. S!o!a+ and E. 8ee" !SP Processor Fundamentals : Architectures and Features" IEEE Press" 1$$;. %<. K. K. Par!i" VLSI !igital Signal Processing Systems : !esign and Implementation" #iley" 1$$$. %$. P. Pirsc!" Architectures for !igital Signal Processing"#iley" 1$$<. 7(. 9. SinC! and S. SriniEasan" !igital Signal Processing Implementations" T!o+son" &((%. May" &((: c 4EERI" Pilani ) DIT/SMDP-II Required/Essential/Necessary Books V&DL, Verilog and &DL'(ased Design 71. *. 9r+stronC and 1. . ray" V2!L !esign ,epresentation and Synthesis" Second Edition" Prentice-.all" &(((. 7&. P. *. 9s!enden" The !esigner4s Guide to V2!L" Second Edition" ElseEier/MK" &((1. 34!ea5 Edition6 7). *. B!asker" A V2!L Primer" T!ird Edition" Prentice-.all" 1$$$. 34!ea5 Edition6 7%. *. B!asker" A V2!L Synthesis Primer" Second Edition" Star alaAy" 1$$<. 34!ea5 Edition6 77. S. !os!" 2ard%are !escription Languages : &oncepts and Principles" P.I" &(((. 34!ea5 Edition6 7:. S. S@o!ol+ and 8. 8ind!" V2!L for !esigners" Prentice-.all" 1$$;. 7;. S. Dala+anc!ili" Introductory V2!L : From Simulation to Synthesis" Prentice-.all" &(((. 34!ea5 Edition6 7<. S. Dala+anc!ili" V2!L : A Starter4s Guide" Second Edition" Prentice-.all" &((%. 34!ea5 Edition B6 7$. M. . 9rnold" Verilog !igital &omputer !esign : Algorithms to 2ard%are" Prentice.all" 1$$$. :(. *. B!asker" A Verilog 2!L Primer" T!ird Edition" Star alaAy" &((7. 34!ea5 Edition6 :1. *. B!asker" Verilog 2!L Synthesis : A Practical Primer" Star alaAy" 1$$<. 34!ea5 Edition6 :&. D. *. 8il@a and S. S. Sa5atnekar" !esigning !igital &omputer Systems %ith Verilog"

4?P" &((%. :). S. Palnitkar" Verilog 2!L : A Guide to !igital !esign and Synthesis" Second Edition" Prentice-.all" &((). 34!ea5 Edition6 :%. D. E. T!o+as and P. R. Moor=y" The Verilog 2ard%are !escription Language" 1ourt! Edition" Klu2er" 1$$<. :7. R. M. 0eid+an" Verilog !esigner4s Library" Prentice-.all" 1$$$. ::. *. B!asker" A System& Primer" Second Edition" Star alaAy" &((%. :;. S. Sut!erland" S. DaEid+ann and P. 1lake" SystemVerilog for !esign : A Guide to 5sing SystemVerilog for 2ard%are !esign and odeling" Second Edition" S5rinCer" &((:. VLSI)IC C D and lgorithms, &igh'Level Synthesis May" &((: c 4EERI" Pilani % DIT/SMDP-II Required/Essential/Necessary Books :<. M. D. Birn=au+" $ssential $lectronic !esign Automation 6$!A7" Prentice-.all" &((). :$. . De Mic!eli" Synthesis and #ptimi1ation of !igital &ircuits" Mc ra2-.ill" 1$$%. 34!ea5 Edition6 ;(. S. .. ere'" Algorithms for VLSI !esign Automation"#iley" 1$$<. ;1. S. M. Sait and .. Dousse," VLSI Physical !esign Automation : Theory and Practice" #SP" 1$$$. 34!ea5 Edition6 ;&. S. M. Sait and .. Dousse," Iterati"e &omputer Algorithms %ith Applications in $ngineering : Sol"ing &ombinatorial #ptimi1ation Problems"#iley/IEEE" &(((. ;). N. S!er2ani" Algorithms for VLSI Physical Automation" T!ird Edition" Klu2er" 1$$<. 34!ea5 Edition6 ;%. ProceedinCs o, t!e IEEE 3S5ecial Issue on /8SI 49D Tools6" 1e=ruary" 1$$(. &ard*are)So+t*are Codesign, Embedded Systems ;7. D. D. a@ski" 1. /a!id" S. Narayan and *. onC" Speci-cation and !esign of $mbedded Systems" Prentice-.all" 1$$%. ;:. P. Mar2edel" $mbedded System !esign" S5rinCer" &((:. ;;. 1. Mayer-8inden=erC" !edicated !igital Processors : ethods in 2ard%are3Soft%are &o+!esign" #iley" &((%. ;<. T. NoerCaard" $mbedded Systems Architecture : A &omprehensi"e Guide for $ngineers and Programmers" ElseEier/Ne2nes" &((7. ;$. M. SriEastaEa" and /. RaC!unat!an" $mbedded &omputing : A Systems Approach" S5rinCer" &((;. 3To 955ear in *une" &((;6 <(. *. Staunstru5 and #. #ol," 2ard%are3Soft%are &o+!esign : Principles and Practices" Klu2er" 1$$;. <1. 1. /a!id and T. iEarCis" $mbedded System !esign : A 5ni-ed 2ard%are3Soft%are Introduction"#iley" &((&. 34!ea5 Edition6

<&. #. #ol," &omputers as &omponents : Principles of $mbedded &omputer System !esign" Second Edition" ElseEier/MK" &((7. 34!ea5 Edition6 <). ProceedinCs o, t!e IEEE 3S5ecial Issue on .#/S# 4odesiCn6" Marc!" 1$$;. VLSI Testing, Testability and Formal Veri#cation <%. M. 9=ra+oEici" M. 9. Breuer and 9. D. 1ried+an" !igital Systems Testing and Testable !esign" ReEised Edition" IEEE Press" 1$$<. 34!ea5 Edition6 May" &((: c 4EERI" Pilani 7 DIT/SMDP-II Required/Essential/Necessary Books <7. M. 8. Bus!nell and /. D. 9Cra2al" $ssentials of $lectronic Testing for !igital, emory and i8ed Signal VLSI &ircuits" S5rinCer/Klu2er" &(((. <:. N. K. *!a and S. u5ta" Testing of !igital Systems" 4?P" &((). <;. 9. Mic'o" !igital Logic Testing and Simulation" Second Edition" #iley" &((). <<. 8-T. #anC" 4-#. #u and F. #en" VLSI Test Principles and Architectures" ElseEier/ MK" &((:. 3To 955ear6 <$. . D. .ac!tel and 1. So+en'i" Logic Synthesis and Veri-cation Algorithms" S5rinCer" &((:. Lo*'Po*er Design Techni,ues $(. D. Binkley" #ptimi1ing Analog & #S !esign" #iley" &((:. $1. 9. P. 4!andrakasan and R. #. Broderson" Lo% Po%er & #S !esign" IEEE Press" 1$$<. $&. 4. En' and E. /itto'" &harge+'ased #S Transistor odeling : The $.V odel for Lo%+Po%er and ,F I& !esign" #iley" &((:. $). *. B. Kuo and *-.. 8ou" Lo% Voltage & #S VLSI &ircuits" #iley" 1$$<. $%. B. #onC" 9. Mittal" D. 4ao" . #. Starr" 9ano+& #S &ircuit and Physical !esign" #iley" &((%. $7. K-S. Deo and K. Roy" Lo% Voltage, Lo% Po%er VLSI Subsystems" Mc ra2-.ill" &((%. VLSI Interconnects and nalysis $:. .. B. BakoClu" &ircuits, Interconnections and Pac*aging for VLSI" 9ddison-#esley" 1$$(. 3>ut o, Print6 $;. 4-K. 4!enC" *. 8illis" S. 8in and N. 4!anC" Interconnect Analysis and Synthesis"#iley" 1$$$. $<. 9. oel" 2igh Speed VLSI Interconnections : odeling, Analysis and Simulation" #iley" 1$$%. $$. S. .. .all" .#. .all and *. 9. Mc4all" 2igh+Speed !igital System !esign : A 2andboo* of Interconnect Theory and !esign Practices" #iley/IEEE" &(((. 1((. R. P. SinC!" Signal Integrity $ffects in &ustom I& and ASI& !esigns" #iley/IEEE" &((1. 1(1. M. 4elik" 8. PileCCi and 9. >da=asioClu" I& Interconnect Analysis" Klu2er" &((&. System Design, System rchitecture May" &((: c 4EERI" Pilani :

DIT/SMDP-II Required/Essential/Necessary Books 1(&. #. *. Dally and *. #. Poulton" !igital Systems $ngineering" 4?P" 1$$<. 1(). #. *. Dally and B. P. To2les" Principles and Practices of Interconnection 9et%or*s" ElseEier/MK" &((). 1(%. *. Di iaco+o" !igital 'us 2andboo*" Mc ra2-.ill" 1$$(. 3>ut o, Print6 1(7. .. #. *o!nson and M. ra!a+" 2igh Speed !igital !esign : A 2andboo* of 'lac* agic" Prentice-.all" 1$$). 1(:. D. N. Patt and S. *. Patel" Introduction to &omputing Systems : From 'its and Gates to & and 'eyond" Second Edition" Mc ra2-.ill" &((%. 1(;. R. *. Tocci" N. S. #id+er and . 8. Moss" !igital Systems : Principles and Applications" Tent! Edition" Prentice-.all" &((:. 34!ea5 Edition6 Digital Logic Design 1(<. D. D. a@ski" Principles of !igital !esign" Prentice-.all" 1$$;. 1($. E. *. Mc4luskey" Logic !esign Principles : :ith $mphasis on Testable Semicustom &ircuits" Prentice-.all" 1$<:. 3>ut o, Print6 11(. S. .. ?nCer" $ssence of Logic &ircuits" Second Edition"#iley/IEEE" 1$$<. 111. 1. /a!id" !igital !esign" #iley" &((:. 11&. *. 1. #akerly" !igital !esign Principles and Practices" 1ourt! Edition" Prentice.all" &((7. 34!ea5 Edition B6 Linu%)-ni% System dministration 1. M. Bis!o5" Introduction to &omputer Security" 9ddison-#esley" &((%. &. #. R. 4!es2ick" S. M. BelloEin and 9. D. Ru=in" Fire%alls and Internet Security : ,epelling the :ily 2ac*er" Second Edition" 9ddison-#esley" &((). ). 9. 1risc!" $ssential System Administration" T!ird Edition" >R9" &((&. 34!ea5 Edition6 %. B.#. KerniC!an and R. Pike" The 5ni8 Programming $n"ironment" P.I" 1$<&. 34!ea5 Edition6 7. T. 9. 8i+oncelli and 4. .oCan" The Practice of System and 9et%or* Administration" Pearson/9#" &((&. 34!ea5 Edition6 :. E. Ne+et!" . Snyder and T. .ein" Linu8 Administration 2andboo*" P.I" &((&. 34!ea5 Edition6 ;. M. . So=ell" A Practical Guide to Linu8 &ommands, $ditors, and Shell Programming" Pearson/P." &((7. 34!ea5 Edition B6 <. S. ar-nkel" . S5a,,ord and 9. Sc!2art'" Practical 59I; and Internet Security" T!ird Edition" >R9" &((). May" &((: c 4EERI" Pilani ; DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books VLSI Fabrication Technology 1. 9. R. 9lEare'" 'i& #S Technology and Applications" Second Edition" Klu2er" 1$$). &. S. 9. 4a+5=ell" The Science and $ngineering of icroelectronic Fabrication" Second Edition" >?P" &((1.

). B. . Eynon and B. #u" Photomas* Fabrication Technology" Mc ra2-.ill" &((7. %. S. 1ranssila" Introduction to icrofabrication"#iley" &((%. 7. .. enC" Semiconductor anufacturing 2andboo*" Mc ra2-.ill" &((7. :. R. 4. *aeCer" Introduction to icroelectronics Fabrication" Second Edition" Pearson/ 9#/P." &((&. ;. . S. May and 4. *. S5anos" Fundamentals of Semiconductor anufacturing and Process &ontrol"#iley" &((:. <. D. NaCc!oud!uri" Principles of icroelectronics Technology" #!eeler 3India6" 1$$<. 34!ea5 Edition6 $. S. M. S'e" VLSI Technology" Second Edition" Mc ra2-.ill" 1$<<. 34!ea5 Edition6 1(. S. M. S'e" Semiconductor !e"ices : Physics and Technology" Second Edition" #iley" &((&. 11. D. P. TsiEidis" i8ed Analog+!igital VLSI !e"ices and Technology : An Introduction" Mc ra2-.ill" 1$$:. Semiconductor Devices, Device Modeling and Simulation, SPICE 1&. N. 9rora" #SF$T odels for VLSI &ircuit Simulation" S5rinCer" 1$$). 1). D. Bell" $lectronic !e"ices and &ircuits" 1ourt! Edition" P.I" 1$$$. 34!ea5 Edition6 1%. T. 1. BoCart" *. S. Beasley and . Rico" $lectronic !e"ices and &ircuits" SiAt! Edition" Pearson/P." &((%. 17. K. 1. Brennan" Introduction to Semiconductor !e"ices" 4?P" &((7. 1:. K. 1. Brennan and 9. S. Bro2n" Theory of odern $lectronic Semiconductor !e"ices" #iley" &((&. 1;. *. 4at!ey" Schaum4s #utline of $lectronic !e"ices and &ircuits" Second Edition" Mc ra2.ill" &((&. 1<. D. 4!enC and 4. .u" #SF$T odeling and 'SI ( 5ser4s Guide" Klu2er" 1$$$. 1$. S. Di+itri@eE" 5nderstanding Semiconductor !e"ices" >?P" &(((. &(. N. DasCu5ta and 9. DasCu5ta" Semiconductor !e"ices : odelling and Technology" P.I" &((A. 34!ea5 Edition6 May" &((: c 4EERI" Pilani < DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books &1. T. 9. 1@eldly" T. Dtterdal and M. S!ur" Introduction to !e"ice odeling and &ircuit Simulation"#iley" 1$$;. &&. 4. . 1onstad" icroelectronic !e"ices and &ircuits" Mc ra2-.ill" 1$$%. 34!ea5 Edition6 &). 9. S. roEe" Physics and Technology of Semiconductor !e"ices" #iley" 1$:;. 34!ea5 Edition6 &%. K. Kano" Semiconductor !e"ices" P.I" &((A. 34!ea5 Edition6 &7. R. Kielko2ski" Inside SPI&$" Second Edition" Mc ra2-.ill" 1$$<. &:. K. 8ee" M. S!ur" T. 9. 1@eldly and T. Dtterdal" Semiconductor !e"ice odeling for VLSI" Prentice-.all" 1$$).

&;. . Masso=rio and P. 9ntoCnetti" Semiconductor !e"ice odeling %ith SPI&$" Second Edition" Mc ra2-.ill" 1$$<. &<. D. NaCc!oud!uri" icroelectronic !e"ices" Pearson" &((1. 34!ea5 Edition6 &$. K. K. NC" &omplete Guide to Semiconductor !e"ices" Second Edition" #iley/IEEE" &((&. 34!ea5 Edition B6 )(. E. .. Nicollian and *. R. Bre2s" #S Physics and Technology" #iley" 1$<&/&((&. 34!ea5 Edition6 )1. D. *. Roulston" An Introduction to the Physics of Semiconductor !e"ices" >?P" 1$$<. )&. #. R. Runyan and T. *. S!a,,ner" Semiconductor easurements and Instrumentation" Second Edition" Mc ra2-.ill" 1$$<. )). M. Satya+ and K. Ra+ku+ar" Fundamentals of $lectronic !e"ices" #iley" 1$$(. 34!ea5 Edition6 )%. D. K. Sc!roder" Semiconductor aterial and !e"ice &haracteri1ation" Second Edition" #iley" 1$$<. )7. M. S!ur" Introduction to $lectronic !e"ices" #iley" 1$$7. ):. M. S!ur" Physics of Semiconductor !e"ices" Prentice-.all" 1$$(. 34!ea5 Edition6 );. S. M. S'e" odern Semiconductor !e"ice Physics" #iley" 1$$<. )<. S. M. S'e" Semiconductor !e"ices : Physics and Technology" Second Edition" #iley" &((&. 34!ea5 Edition6 )$. S. M. S'e and K. K. NC" Physics of Semiconductor !e"ices" T!ird Edition" #iley" &((:. %(. D. Taur and T. .. NinC" Fundamentals of odern VLSI !e"ices" 4?P" 1$$<. %1. D. P. TsiEidis" #peration and odeling of the #S Transistor" Mc ra2-.ill" 1$<;. May" &((: c 4EERI" Pilani $ DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books %&. P. #. TuinenCa" SPI&$ : A Guide to &ircuit Simulation and Analysis 5sing P+ SPI&$" T!ird Edition" Prentice-.all" 1$$7. 34!ea5 Edition6 %). R. K. #atts" Submicron Integrated &ircuits" #iley" 1$<$. %%. *. S. Duan and *. *. 8iou" Semiconductor !e"ice Physics and Simulation" Plenu+" 1$$<. VLSI Design, VLSI Subsystem Design %7. *. E. 9yers" !igital Integrated &ircuits : Analysis and !esign" 4R4 Press" &((). %:. S. .. K. E+=a=i" 9. Bellaouar and M. I. El+asry" !igital 'i& #S Integerated &ircuit !esign" Klu2er" 1$$). %;. K. Bernstein" K. M. 4arriC" 4. M. Dur!a+" P. R. .ansen" D. .oCen+iller" E. *. No2ak and N. *. Ro!rer" 2igh Speed & #S !esign Styles" Klu2er" 1$$<. %<. K. Es!raC!ian" D. 9. Pucknell and S. Es!raC!ian" $ssentials of VLSI &ircuits and Systems" P.I" &((7. 34!ea5 Edition6 %$. 8. 9. lasser and D. #. Do==er5u!l" The !esign and Analysis of VLSI &ircuits" 9ddison-#esley" 1$<7. 3>ut o, Print6 7(. *. .andy" The &ache emory 'oo*" Second Edition" ElseEier/MK" 1$$<.

71. D. .arris" S*e%+Tolerant &ircuit !esign" ElseEier/MK" &(((. 7&. D. 9. .odCes" Analysis and !esign of !igital Integrated &ircuits" T!ird Edition" Mc ra2-.ill" &((). 7). K. Ito!" VLSI emory &hip !esign" S5rinCer" &((1. 34!ea5 Edition6 7%. B. Keet! and R. *. Baker" !,A &ircuit !esign : A Tutorial"#iley/IEEE" &(((. 77. K. Martin" !igital Integrated &ircuit !esign" >?P" 1$$$. 7:. B. Prince" Semiconductor emories : A 2andboo* of !esign, anufacture and Application" Second Edition"#iley" 1$$:. 7;. D. 9. Pucknell and K. Es!raC!ian" 'asic VLSI !esign : Systems and &ircuits" T!ird Edition" Prentice-.all" 1$$%. 34!ea5 Edition6 7<. 4. Saint and *. Saint" I& Layout 'asics : A Practical Guide" Mc ra2-.ill" &((&. 7$. 4. Saint and *. Saint" I& as* !esign : $ssential Layout Techni/ues" Mc ra2-.ill" &((&. :(. 9. K. S!ar+a" Semiconductor emories : Technology, Testing and ,eliability" #iley/ IEEE" &((&. 34!ea5 Edition6 :1. 9. K. S!ar+a" Ad"anced Semiconductor emories : Architectures, !esigns, and Applications" #iley/IEEE" &((&. 34!ea5 Edition B6 May" &((: c 4EERI" Pilani 1( DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books :&. I. Sut!erland" B. S5roull and D. .arris" Logical $ffort : !esigning Fast & #S &ircuits" ElseEier/MK" 1$$$. :). *. P. ?ye+ura" &hip !esign for Submicron VLSI : & #S Layout and Simulation" T!o+son" &((7. :%. *. P. ?ye+ura" Physical !esign of & #S Integrated &ircuits 5sing L+$dit" T!o+son" 1$$7. :7. *. P. ?ye+ura" Fundamentals of #S !igital Integrated &ircuits" 9ddison-#esley" 1$<<. 3>ut o, Print6 ::. M. M. /ai" VLSI !esign" 4R4 Press" &(((. :;. .. *. M. /eendrick" !eep+Submicron & #S I&s : From 'asics to ASI&s" Klu2er" &(((. :<. N. #este and K. Es!raC!ian" Principles of & #S VLSI !esign : A Systems Perspecti"e" ReEised Second Edition" Pearson/9#" 1$$$. 34!ea5 Edition6 SIC Design, FP! Design, "econ#gurable Com$uting :$. /. Bet'" *. Rose and 9. Marquardt" Architecture and &A! for !eep+Submicron FPGAs" Klu2er" 1$$$. ;(. N. . Eins5ruc! and *. 8. .il=ert" ASI& Technology" 9cade+ic Press" 1$$1. ;1. /. eorCe and *. M. Ra=aey" Lo%+$nergy FPGAs : Architecture and !esign" Klu2er" &((1.

;&. M. ok!ale" and P. S. ra!a+" ,econ-gurable &omputing : Accelerating &omputation %ith Field+Programmable Gate Arrays" S5rinCer" &((7. ;). R. Munden" ASI& and FPGA Veri-cation : A Guide to &omponent odeling" ElseEier/ MK" &((%. ;%. 0. NaEa=i" !igital !esign and Implementation %ith Field Programmable !e"ices" S5rinCer" &((7. ;7. 1. NekooCar" Timing Veri-cation of ASI&s" Prentice-.all" &(((. ;:. 1. NekooCar and 1. NekooCar" From ASI&s to So&s : A Practical Approach" Prentice.all" &((). ;;. D. Pellerin and S. T!i=ault" Practical FPGA Programming in &" Pearson/P." &((7. ;<. M. 9. Ric!ards" 9. *. adient and . 9. 1rank" ,apid Prototyping of Application Speci-c Signal Processors" Klu2er" 1$$;. ;$. 0. Salcic" V2!L and FPL!s in !igital System !esign, Prototyping and &ustomi1ation" Klu2er" 1$$<. May" &((: c 4EERI" Pilani 11 DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books <(. R. 4. Seals and . 1. #!a5s!ott" Programmable Logic : PL!s and FPGAs" Mc ra2.ill" 1$$;. <1. 9. K. S!ar+a" Programmable Logic 2andboo* : PL!s, &PL!s and FPGAs" Mc ra2.ill" 1$$<. <&. S. M. Tri+=erCer" FPGA Technology" Klu2er" 1$$%. nalog IC Design, Mi%ed Signal Design, "F IC Design <). 9naloC DeEices Inc." !ata &on"ersion 2andboo*" ElseEier/Ne2nes" &((%. <%. R. *. Baker" ..#. 8i and D. E. Boyce" & #S : &icuit !esign, Layout and Simulation" IEEE Press" 1$$<. 34!ea5 Edition6 <7. *. *. Becerra and E. . 1ried+an" Analog !esign Issues in !igital VLSI &ircuits and Systems" Klu2er" 1$$;. <:. E. N. 1araC and M. I. El+asry" i8ed Signal VLSI :ireless !esign : &ircuits and Systems" S5rinCer/Klu2er" 1$$$. <;. *. E. 1ranca and D. TsiEidis" !esign of Analog+!igital VLSI &ircuits for Telecommunications and Signal Processing" Second Edition" Prentice-.all" 1$$). <<. R. reCorian" Introduction to & #S #p+Amps and &omparators"#iley" 1$$$. <$. S. 8. .urst" VLSI &ustom icroelectronics : !igital, Analog and i8ed Signal" Second Edition" Marcel Dekker" 1$$<. $(. P. . 9. *es5ers" Integrated &on"erters : !+A and A+! Architectures, Analysis and Simulation" >?P" &((1. $1. B. .. 8eunC" VLSI for :ireless &ommunication" Pearson/P." &((&. $&. M. 8iu" !emystifying S%itched &apacitor &ircuits" ElseEier/Ne2nes" &((:.

$). R. 8ud2iC and P. Bretc!ko" ,F &ircuit !esign : Theory and Applications" Prentice.all" &(((. 34!ea5 Edition6 $%. E. Sanc!e'-Sinencio and 9. . 9ndreou" Lo%+Voltage3Lo%+Po%er Integrated &ircuits and Systems : Lo%+Voltage i8ed+Signal &ircuits" IEEE Press" 1$$$. $7. *. R. S+it!" odern &ommunications &ircuits" Mc ra2-.ill" 1$$;. 34!ea5 Edition6 $:. 9. 9. Stocker" Analog VLSI &ircuits for the Perception of Visual otion"#iley" &((:. $;. M. T!o+5son" Intuiti"e Analog &ircuit !esign" ElseEier/Ne2nes" &((:. $<. S. #inder" Analog and !igital Filter !esign" Second Edition" ElseEier/Ne2nes" &((&. $$. T. Dtterdal" D. 4!enC and T. 9. 1@eldly" !e"ice odeling for Analog and ,F & #S &ircuit !esign" #iley" &((). May" &((: c 4EERI" Pilani 1& DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books VLSI Systems rchitecture, Com$uter rchitecture, DSP rchitecture 1((. *. D. 4ar5inelli" &omputer Systems #rgani1ation and Architecture" 9ddison#esley" &((1. 1(1. 9. 4le+ents" Principles of &omputer 2ard%are" 1ourt! Edition" >?P" &((:. 1(&. M. D. ErceCoEac and T. 8anC" !igital Arithmetic" ElseEier/MK" &((). 1(). *. 1eld+an and 4. Retter" A !esigner4s Te8t 5sing a Generic ,IS&" Mc ra2-.ill" 1$$%. 1(%. M. *. 1lynn and S. 1. >=er+an" Ad"anced &omputer Arithmetic !esign" #iley" &((1. 1(7. /. 4. .a+ac!er" 0. . /ranesic" and S. . 0aky" &omputer #rgani1ation" 1i,t! Edition" Mc ra2-.ill" &((&. 34!ea5 Edition6 1(:. *. P. .ayes" &omputer Architecture and #rgani1ation" T!ird Edition" Mc ra2-.ill" &((&. 34!ea5 Edition6 1(;. K. .2anC" Ad"anced &omputer Architecture : Parallelism, Scalability, Programmability" Mc ra2-.ill" 1$$). 34!ea5 Edition6 1(<. M. *o!nson" Superscalar icroprocessor !esign" Prentice-.all" 1$$1. 1($. I. Koren" &omputer Arithmetic Algorithms" Second Edition" 9K Peters" &((). 34!ea5 Edition6 11(. P. Pal 4!oud!uri" &omputer #rgani1ation and !esign" Second Edition" Prentice.all" 1$$$. 34!ea5 Edition6 111. B. Par!a+i" &omputer Architecture : From icroprocessors to Supercomputers" >?P" &((7. 11&. B. Par!a+i" &omputer Arithmetic : Algorthms and 2ard%are !esign" >?P" 1$$$. 11). D. 9. Patterson and *. 8. .ennessy" &omputer Architecture : A 0uantitati"e Approach"

Second Edition" ElseEier/MK" 1$$:. 34!ea5 Edition6 11%. D. Si+a" T. 1ountain and P. Kacsuk" Ad"anced &omputer Architecture : A !esign Space Approach" 9ddison-#esley" 1$$;. 117. .. Stone" 2igh Performance &omputer Architectures" Second Edition" 9ddison#esley" 1$$(. 3>ut o, Print6 11:. S. #ard and R. .alstead" &omputational Structures" Mc ra2-.ill/IEEE Press/MIT Press" 1$$(. 11;. *. P. S!en and M. 8i5asti" odern Processor !esign : Fundamentals of Superscalar Processors" Mc ra2-.ill" &((%. 11<. /. K. Madisetti" VLSI !igital Signal Processors" Butter2ort!-.eine+ann/IEEE Press" 1$$7. 3>ut o, Print6 May" &((: c 4EERI" Pilani 1) DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books 11$. ?. Meyer-Baese" !igital Signal Processing %ith Field Programmable Gate Arrays" S5rinCer" &((1. 1&(. S. K. Mitra and *. 1. Kaiser" 2andboo* for !igital Signal Processing" #iley" 1$$). V&DL, Verilog and &DL'(ased Design 1&1. .. B!atnaCar" Ad"anced ASI& &hip Synthesis 5sing Synopsys !esign &ompiler and PrimeTime" Second Edition" S5rinCer/Klu2er" &((&. 1&&. S. Bro2n and 0. /ranesic" Fundamentals of !igital Logic %ith V2!L !esign" Second Edition" &((7. 1&). B. 4o!en" V2!L &oding Styles and ethodologies" Second Edition" Klu2er" 1$$$. 1&%. B. 4o!en" V2!L Ans%ers to Fre/uently As*ed 0uestions" Second Edition" Klu2er" 1$$<. 1&7. IEEE Standard 1(;:-1$$)" V2!L Langauge ,eference anual" IEEE Press" 1$$). 1&:. 0. NaEa=i" V2!L : Analysis and odeling of !igital Systems" Second Edition" Mc ra2.ill" 1$$<. 34!ea5 Edition6 1&;. D. Naylor and S. *ones" V2!L : A Logic Synthesis Approach" 4!a5+an G .all" 1$$;. 1&<. D. E. >tt and T. *.#ilderotter" A !esigner4s Guide to V2!L Synthesis" Klu2er" 1$$%. 1&$. /. 9. Pedroni" &ircuit !esign %ith V2!L" MIT Press/P.I" &((%. 34!ea5 Edition6 1)(. *. Pick" V2!L : Techni/ues, $8periments and &a"eats" Mc ra2-.ill" 1$$:. 34!ea5 Edition6 1)1. S. Bro2n and 0. /ranesic" Fundamentals of !igital Logic %ith Verilog !esign" &((). 1)&. M. D. 4iletti" Ad"anced !igital !esign :ith The Verilog 2!L" P.I" 1$$$. 34!ea5 Edition6 1)). K. 4o,,+an" ,eal :orld FPGA !esign %ith Verilog" Prentice-.all" &(((. 1)%. P. 1oote and 1. EnCel+ann" Verilog 2!L ,e"ealed : A Practical Guide to System Simulation" Prentice-.all" &(((. 1)7. IEEE Standard 1)$%-1$$7" Verilog Langauge ,eference anual" IEEE Press"

1):. #. 1. 8ee" Verilog &oding for Logic Synthesis" #iley" &((). 1);. 0. NaEa=i" Verilog !igital System !esign" Second Edition" Mc ra2-.ill" &((7. 1)<. T. R. Pad+ana=!an and B. B. T. Sundari" !esign Through Verilog 2!L" #iley" &((%. 1)$. D. *. S+it!" 2!L &hip !esign : A Practical Guide" Doone Pu=lis!er" 1$$;. May" &((: c 4EERI" Pilani 1% DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books VLSI)IC C D and lgorithms, &igh'Level Synthesis 1%(. Ad"ances in &A! for VLSI" /olu+es 1 . <" ElseEier/Nort! .olland" 1$<:-$%. 1%1. P. Baner@ee" Parallel Algorithms for VLSI &A!" Prentice-.all" 1$$%. 1%&. D. D. a@ski" N. Dutt" 9. 4-.. #u and S. D-8. 8in" 2igh+Le"el Synthesis : Introduction to &hip and System !esign" Klu2er" 1$$&. 1%). *. B. oslinC" Simulation in the !esign of !igital $lectronic Systems" 4?P" 1$$). 1%%. . D. .ac!tel and 1. So+en'i" Logic Synthesis and Veri-cation Algorithms" S5rinCer" &((:. 1%7. S. .assoun and T. Sasao" Logic Synthesis and Veri-cation" S5rinCer" &((1. 1%:. 1. *. .ill and . R. Peterson" &omputer Aided Logical !esign %ith $mphasis on VLSI" 1ourt! Edition"#iley" 1$$). 1%;. P. Kuru5 and T. 9==asi" Logic Synthesis 5sing Synopsys" Second Edition" Klu2er" 1$$:. 1%<. P. Ma'u+der and E. Rudnick" Genetic Algorithms for VLSI !esign, Layout and Test Automation" Pearson/P./9#" 1$$$. 34!ea5 Edition6 1%$. 4. Meinel and T. T!eo=ald" Algorithms and !ata Structures in VLSI !esign" S5rinCer" 1$$<. 17(. P. Mic!el" ?. 8aut!er and P. Du'y" The Synthesis Approach to !igital System !esign" Klu2er" 1$$&. 171. 9. Mic'o" !igital Logic Testing and Simulation" Second Edition" #iley" &((). 17&. 8. T. PillaCe" R. 9. Ro!rer and 4. /is2es2aria!" $lectronic &ircuit and System Simulation ethods" Mc ra2-.ill" 1$$<. 17). M. Sarra,'ade! and 4. K. #onC" An Introduction to VLSI Physical !esign" Mc ra2.ill" 1$$:. 34!ea5 Edition6 17%. *. D. ?ll+an" &omputational Aspects of VLSI" #. 1ree+an/4S Press" 1$<%. 3>ut o, Print6 177. B. #ile" *. oss and #. Roesner" &omprehensi"e Functional Veri-cation : The &omplete Industry &ycle" ElseEier/MK" &((7. &ard*are)So+t*are Codesign, Embedded Systems 17:. *-M. BerCe" >. 8eEia and *. Rouillard" 2ard%are3Soft%are &o+!esign and &o+ Veri-cation"

Klu2er" 1$$:. 17;. . De Mic!eli and M. Sa+i 3Editors6" 2ard%are3Soft%are &o+!esign" Klu2er" 1$$:. May" &((: c 4EERI" Pilani 17 DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books 17<. *. Ean den .urk and *. *ess" System Le"el 2ard%are3Soft%are &odesign : An Industrial Approach" Klu2er" 1$$;. 17$. P. Eles" K. Kuc!cinski and 0. PenC" System Synthesis %ith V2!L" Klu2er" 1$$<. 1:(. *. 9. 1is!er" P. 1ara=osc!i and 4. DounC" $mbedded &omputing : A VLI: Approach to Architecture, &ompilers and Tools" ElseEier/MK" &((%. 1:1. R. K. u5ta" &o+synthesis of 2ard%are3Soft%are for !igital $mbedded Systems" Klu2er" 1$$7. 1:&. S. .eat!" $mbedded Systems !esign" Second Edition" ElseEier/Ne2nes" &((&. 1:). P. Ienne and R. 8eu5ers" &ustomi1able $mbedded Processors : !esign Technologies and Applications" ElseEier/MK" &((:. 3To 955ear6 1:%. S. I+an and M. Pedra+" Logic Synthesis for Lo%+Po%er VLSI !esigns" Klu2er" 1$$;. 1:7. 9. *erraya and #. #ol," ultiprocessor Systems+on+&hips" ElseEier/MK" &((%. 1::. *. 4. 8o5e'" R. .er+ida and #. essel!ardt" Ad"ance Techni/ues for $mbedded Systems !esign and Test" Klu2er" 1$$<. 1:;. D. E. >tt and T. *.#ilderotter" A !esigner4s Guide to V2!L Synthesis" Klu2er" 1$$%. 1:<. Proceeding of &#!$S &onference" IEEE Press. 39Eaila=le ,or /arious Dears6 VLSI Testing, Testability and Formal Veri#cation 1:$. /. 9Cra2al and S. 4. Set!" Test Generation for VLSI &hips" IEEE 4S Press" 1$<$. 1;(. 9. 4rouc!" !esign for Test for !igital I&s and $mbedded &ore Systems" Prentice.all" &(((. 1;1. T. 1it'5atrick" 9. Sal'" D. Ric! and S. Sut!erland" SystemVerilog for Veri-cation" S5rinCer" &((:. 1;&. S. 8. .urst" VLSI Testing : !igital and i8ed Analog3!igital Techni/ues" INSPE4/IEE" 1$$$. 1;). P. K. 8ala" Self+&hec*ing and Fault+Tolerant !igital !esign" ElseEier/MK" &(((. 1;%. #. K. 8a+" 2ard%are !esign Veri-cation : Simulation and Formal ethod+'ased Approaches" Prentice-.all" &((7. 1;7. 4. Maunder" The 'oard !esigner4s Guide to Testable Logic &ircuits" 9ddison#esley" 1$$&. 1;:. S. Mourad and D. 0orian" Principles of Testing $lectronic Systems" #iley" &(((. 1;;. K. P. Parker" The 'oundary Scan 2andboo* : Analog and !igital" T!ird Edition"

S5rinCer/Klu2er" &((). May" &((: c 4EERI" Pilani 1: DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books 1;<. D. 8. Perry and .. 1oster" Applied Formal Veri-cation : For !igital &ircuit !esign" Mc ra2-.ill" &((7. 1;$. D. K. Prad!an" Fault+Tolerant &omputing : Theory and Techni/ues" /olu+e I" Prentice.all" 1$<:. 3>ut o, Print6 1<(. D. K. Prad!an" Fault+Tolerant &omputing : Theory and Techni/ues" /olu+e II" Prentice.all" 1$<:. 3>ut o, Print6 1<1. R. Ra@su+an" System+on+a+&hip !esign and Test" 9rtec!" &(((. 1<&. B. /innakota" Analog and i8ed+Signal Test" Prentice-.all" 1$$<. 1<). B. #ile" *. oss and #. Roesner" &omprehensi"e Functional Veri-cation : The &omplete Industry &ycle" ElseEier/MK" &((7. Lo*'Po*er Design Techni,ues 1<%. 9. Bellaouar and M. I. El+asry" Lo%+Po%er !igital VLSI !esign : &ircuits and Systems" Klu2er" 1$$7. 1<7. 9. P. 4!andrakasan and R. #. Broderson" Lo% Po%er !igital & #S !esign" Klu2er" 1$$7. 1<:. /. Kursun and E. . 1ried+an" ulti+"oltage & #S &ircuit !esign" #iley" &((:. 1<;. *. M. Ra=aey and M. Pedra+" Lo% Po%er !esign ethodologies" Klu2er" 1$$:. 1<<. . K. Dea5" Practical Lo%+Po%er !igital VLSI !esign" Klu2er" 1$$;. VLSI Interconnects and nalysis 1<$. 4. 9. .ar5er" $lectronic Pac*aging and Interconnection 2andboo*" Mc ra2-.ill" &((%. 1$(. 9. B. Ka!nC and . Ro=ins" #n #ptimal Interconnects for VLSI" Klu2er" 1$$%. 1$1. 1. Moll and M. Roca" Interconnection 9oise in VLSI &ircuits" S5rinCer" &((%. System Design, System rchitecture 1$&. D. 9nderson" 5ni"ersal Serial 'us 65S'7 System Architecture" 9ddison-#esley" 1$$;. 1$). R. Budruk" D. 9nderson" T. S!anley" P&I $8press System Architecture" 9ddison#esley" &((%. 1$%. 1. M. 4ady" icrocontrollers and icrocomputers : Principles of Soft%are and 2ard%are $ngineering" >?P" 1$$;. May" &((: c 4EERI" Pilani 1; DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books 1$7. R. 1ord and 4. 4oulston" !esign for $lectrical and &omputer $ngineers : Theory &oncepts and Practice" Mc ra2-.ill" &((7. 1$:. R. *. .anne+ann" 9. D. Kraus and M. Pec!t" Semiconductor Pac*aging : A ultidisciplinary Approach"#iley" 1$$;.

1$;. K. *. .int' and D. Ta=ak" icrocontrollers : Architecture, Implementation and Programming" Mc ra2-.ill" 1$$&. 1$<. 1. T. 8eiC!ton" Introduction to Parallel Algorithms and Architectures : Arrays, Trees, 2ybercubes" ElseEier/MK" 1$$&. 1$$. B. M. 8unt" $lectronic Physical !esign" Prentice-.all" &((). &((. S. McDo2ell and M. D. Seyer" 5S' $8plained" Prentice-.all" 1$$$. &(1. D. K. Prad!an" Fault+Tolerant &omputer System !esign" Prentice-.all" 1$$:. &(&. T. S!anley and D. 9nderson" P&I System Architecture" T!ird Edition" 9ddison#esley" 1$$7. &(). N. R. Storey" $lectronics : A Systems Approach" Second Edition" 9ddison-#esley" 1$$<. 34!ea5 Edition6 &(%. R. K. ?lric! and #. D. Bro2n" Ad"anced $lectronic Pac*aging" Second Edition" #iley/ IEEE" &((:. Digital Logic Design &(7. M. Balc!" &omplete !igital !esign : A &omprehensi"e Guide to !igital $lectronics and &omputer System Architecture" Mc ra2-.ill" &((). &(:. D. *. 4o+er" !igital Logic and State achine !esign" >?P" 1$$%. &(;. T. 9. DeMassa and 0. 4iccone" !igital Integrated &ircuits" #iley" 1$$7. &(<. M. 1renc!" &onceptual !esign for $ngineers" T!ird Edition" S5rinCer" 1$$<. &($. *. P. .ayes" Introduction to !igital Logic !esign" 9ddison-#esley" 1$$). &1(. B. .olds2ort! and 4.#oods" !igital Logic !esign" 1ourt! Edition" ElseEier/Ne2nes" &((&. &11. 0. Ko!aEi" S%itching and Finite Automata Theory" Tata Mc ra2-.ill" 1$;<. 34!ea5 Edition6 &1&. 0. Ko!aEi" R. #. .a++inC and E. 9. 1eiCen=au+" S%itching and Finite Automata Theory" Second Edition" Mc ra2-.ill" 1$<:. &1). S. 8ee" !esign of &omputers and #ther &omple8 !igital !e"ices" Prentice-.all" &(((. &1%. M. Mano" !igital !esign" Second Edition" P.I" 1$$1. 34!ea5 Edition6 May" &((: c 4EERI" Pilani 1< DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books &17. M. Mano" !igital Logic and &omputer !esign" P.I" 1$$A. 34!ea5 Edition6 &1:. M. Mano and 4. Ki+e" Logic and &omputer !esign Fundamentals" Second Edition" Prentice-.all" &(((. &1;. 0. NaEa=i" !igital !esign and Implementation %ith Field Programmable !e"ices" S5rinCer" &((7. &1<. S. . S!iEa" Introduction to Logic !esign" Second Edition" Marcel Dekker" 1$$<. &1$. *. P. ?ye+ura" !igital Systems !esign : An Integrated Approach" T!o+son" &(((. &&(. N. #irt!" !igital &ircuit !esign" S5rinCer" 1$$7. Linu%)-ni% System dministration 1. P. 9l=it' and 4. 8iu" !9S and 'I9!" 1i,t! Edition" >R9" &((:. 34!ea5 Edition6

&. D. *. Barrett" R. E. SilEer+an and R. . Byrnes" SS2, The Secure Shell : The !e-niti"e Guide" Second Edition" >R9" &((7. ). T. Bautts" T. Da2son and . N. Purdy" Linu8 9et%or* Administrator4s Guide" T!ird Edition" >R9" &((7. %. M. Bis!o5" &omputer Security : Art and Science" 9ddison-#esley" &((). 7. D. N. Blank-Edel+an" Perl for System Administration" >R9" &(((. :. . 4arter" L!AP System Administration" >R9" &((). ;. T. 4ollinCs and K. #all" ,ed 2at Linu8 9et%or*ing and System Administration" T!ird Edition"#iley" &((7. <. B. 4ostales and Eric 9ll+an" Sendmail" T!ird Edition" >R9" &((&. 34!ea5 Edition6 $. B. 4ostales" . *ansen" 4. 9ss+ann and . S!a5iro" Sendmail <=>( &ompanion" >R9" &((%. 1(. M. K. Dal!ei+er and M. #els!" ,unning Linu8" 1i,t! Edition" >R9" &((7. 11. M. *anC" ,2&$ Linu8 Study Guide" 1ourt! Edition" Mc ra2-.ill" &((%. 1&. B. 8aurie and P. 8aurie" Apache : The !e-niti"e Guide" T!ird Edition" >R9" &((&. 1). R. 8e!tinen" &omputer Security 'asics" Second Edition" >R9" &((:. 1%. I. Ristic" Apache Security" >R9" &((7. 17. *. N. Ro==ins" :eb !esign in a 9utshell" T!ird Edition" >R9" &((:. 1:. R. 8. Sc!2art'" T. P!oeniA and B. D. 1oy" Learning Perl" 1ourt! Edition" >R9" &((7. 34!ea5 Edition6 May" &((: c 4EERI" Pilani 1$ DIT/SMDP-II Reco++ended/>t!er TeAt/Re,erence Books 1;. E. SieEer" 9. #e=er" S. 1iCCins" R. 8oEe and 9. Ro==ins" Linu8 in a 9utshell" 1i,t! Edition" >R9" &((7. 34!ea5 Edition6 1<. M. . So=ell" A Practical Guide to ,ed 2at Linu8" Second Edition" Pearson/P." &((%. 34!ea5 Edition6 1$. T. Steidler-Dennison" ,un ?our #%n:eb Ser"er 5sing Linu8 and Apache" SitePoint/>R9" &((7. &(. #. R. SteEens and S. 9. RaCo" Ad"anced Programming in the 5ni8 $n"ironment" Second Edition" Pearson/9#" &((7. May" &((: c 4EERI" Pilani &( DIT/SMDP-II >5tional Books VLSI Fabrication Technology 1. 9. 9+erasekera and 1. N. Na@+" Failure echanisms in Semiconductor !e"ices" Second Edition"#iley" 1$$;. &. K. *. Bac!+ann" The aterials Science of icroelectronics"#iley" 1$$%. ). 4. D. 4!anC and S. M. S'e" 5LSI Technology" Mc ra2-.ill" 1$$:. %. 9. 4!ristou" $lectromigration and $lectronic !e"ice !egradation"#iley" 1$$). 7. M. *. Madou" Fundamentals of icrofabrication" Second Edition" 4R4" &((&. :. P. R. S!e5!erd" I& : !esign, Fabrication and Test" Mc ra2-.ill" 1$$:. ;. R. R. Trout+an" Latchup in & #S Technology : The Problem and Its &ure" Klu2er"

1$<$. <. 4-.. TunC" . T. T. S!enC" 4-D. 8u" 5LSI Semiconductor Technology Atlas" #iley" &((). Semiconductor Devices, Device Modeling and Simulation, SPICE $. K. 1. Brennan" The Physics of Semiconductors %ith Applications to #ptoelectronic !e"ices" 4?P" 1$$$. 1(. . 1. 4arey" #. B. Ric!ardson" 4. S. Reed and B. MulEaney" &ircuit, !e"ice and Process Simulation : athematical and 9umerical Aspects" #iley" 1$$:. 11. *. 9. 4onnelly and P. 4!oi" acromodeling %ith SPI&$" Prentice-.all" 1$$&. 1&. D. K. 1erry and R. >. rondin" Physics of Submicron !e"ices" Plenu+" 1$$1. 1). . Di iaco+o" ,eliability of $lectronic Pac*ages and Semiconductor !e"ices" Mc ra2.ill" 1$$:. 1%. 4. .a+aCuc!i" 'asic Semiconductor Physics" S5rinCer" &((:. 17. K. .ess" Ad"anced Theory of Semiconductor !e"ices" #iley/IEEE" 1$$$. 34!ea5 Edition6 1:. K. .ess" &omputational $lectronics : Semiconductor Transport and !e"ice Simulation" Klu2er" 1$$1. 1;. S. >. Kasa5" Principles of $lectronic aterials and !e"ices" T!ird Edition" Mc ra2.ill" &((7. 1<. K. M. Kra+er and#. N. . .itc!on" Semiconductor !e"ices : A Simulation Approach" Prentice-.all" 1$$;. 1$. K. S. Kundert" The !esigner4s Guide to SPI&$ and SP$&T,$" Klu2er" 1$$7. May" &((: c 4EERI" Pilani &1 DIT/SMDP-II >5tional Books &(. *. *. 8iou" 9. >rti'-4onde and 1. racia-Sanc!e'" Analysis and !esign of #SF$Ts : odeling, Simulation and Parameter $8traction" Klu2er" 1$$<. &1. D. 9. Nea+en" Semiconductor Physics and !e"ices : 'asic Priciples" Second Edition" #iley" &((&. &&. R. *. Pierrett" Semiconductor !e"ice Fundamentals" Prentice-.all" 1$$:. &). R. *. Pierrett" Ad"anced Semiconductor Fundamentals" Second Edition" Pearson/P." &((&. &%. 4-T. Sa!" Fundamentals of Solid State $lectronics"#orld Scienti-c" 1$$1. &7. 9. Sc!enk" Ad"anced Physical odels for Silicon !e"ice Simulation" S5rinCer" 1$$<. &:. *. SinC!" Semiconductor !e"ices : 'asic Principles" #iley" &(((. &;. *. SinC!" Semiconductor !e"ices : An Introduction" Mc ra2-.ill" 1$$%. &<. M. S. TyaCi" Introduction to Semiconductor aterials and !e"ices" #iley" 1$$1. &$. S. .. /old+an" $S! : Physics and !e"ices" #iley" &((%. )(. #. T. #encke=ac!" $ssentials of Semiconductor Physics" #iley" 1$$$. VLSI Design, VLSI Subsystem Design )1. E. 9. 9+erasekera and 4. DuEEury" $S! in Silicon Integrated &ircuits" Second Edition"

#iley" &((&. )&. S. Da=ral and T. Maloney" 'asic $S! and I3# !esign" #iley" 1$$<. )). K. o5alan" Introduction to !igital icroelectronics &icuits" Ir2in" 1$$:. )%. 4. *. Myers" Asynchronous &ircuit !esign" #iley" &((1. )7. /. . >klo=d'i@a" /. M. Sto@anoEic" D. M. MarkoEic and N. M. NedoEic" !igital System &loc*ing : 2igh+Performance and Lo%+Po%er Aspects" #iley/IEEE" &((). ):. B. Prince" 2igh Performance emories : 9e% Architectures !,A s and S,A s" ReEised Edition" #iley" 1$$$. );. B. Ra'aEi" !esign of Integrated &ircuits for #ptical &ommunications" Mc ra2-.ill" &((). )<. R. See5old and 9. Kun'+ann" ,euse Techni/ues for VLSI !esign" Klu2er" 1$$$. )$. S. .. /old+an" $S! : &ircuits and !e"ices" #iley" &((:. May" &((: c 4EERI" Pilani && DIT/SMDP-II >5tional Books SIC Design, FP! Design, "econ#gurable Com$uting %(. S. D. Bro2n" R. *. 1rancis" *. Rose and 0. . /ranesic" Field Programmable Gate Arrays" Klu2er" 1$$&. %1. R. 4. 4o,er and B. 1. .ardinC" ,apid System Prototyping %ith FPGAs : Accelerating the !esign Process" ElseEier/Ne2nes" &((7. %&. *. Di iaco+o" !esigning %ith 2igh Performance ASI&s" Prentice-.all" 1$$&. %). 4. MaA-eld" The !esign :arrior4s Guide to FPGAs" ElseEier/Ne2nes" &((%. 34!ea5 Edition6 %%. R. MurCai" R. K. Brayton and 9. SanCioEanni-/incentelli" Logic Synthesis for FPGAs" Klu2er" 1$$7. %7. M. S. B. Ro+d!ane" /. K. Madisetti and *.#. .ines" 0uic*+Turnaround ASI& !esign in V2!L &ore+'ased 'eha"ioral Synthesis" Klu2er" 1$$:. %:. B. 0eid+an" !esigning %ith FPGAs and &PL!s" 4MP Books" &((&. nalog IC Design, Mi%ed Signal Design, "F IC Design %;. R. E. Best" Phase+loc*ed Loops : Theory, !esign and Applications" 1i,t! Edition" Mc ra2-.ill" &((). %<. . Bianc!i" Phase+Loc*ed Loop Synthesi1er Simulation" Mc ra2-.ill" &((7. %$. P. /. Brennan" Phase+loc*ed Loops : Principles and Practices" Mc ra2-.ill" 1$$:. 7(. D. *. 4o+er and D. T. 4o+er" Fundamentals of $lectronic &ircuit !esign" #iley" &((). 71. D. *. 4o+er and D. T. 4o+er" Ad"anced $lectronic &ircuit !esign" #iley" &((). 7&. N. Dye and .. ran=erC" ,adio Fre/uency Transistors : Principles and Practical Applications" Second Edition" ElseEier/Ne2nes" &((1. 7). *. EEerard" Fundamentals of ,F &ircuit !esign %ith Lo% 9oise #scillators" #iley" &((1. 7%. S. 1ranco" !esign %ith #perational Ampli-ers and Analog Integrated &ircuits" T!ird Edition" Mc ra2-.ill" &((&. 77. R. 8. eiCer" P. E. 9llen and N. R. Strader" VLSI !esign Techni/ues for Analog and !igital &ircuits" Mc ra2-.ill" 1$$(. 3>ut o, Print6 7:. R. oyal" 2igh Fre/uency Analog I& !esign" #iley" 1$$7.

7;. P. ray" Analog #S Integrated &ircuits" IEEE Press" 1$<(. 3>ut o, Print6 7<. P. ray" Analog #S Integrated &ircuits II" IEEE Press" 1$$(. 3>ut o, Print6 May" &((: c 4EERI" Pilani &) DIT/SMDP-II >5tional Books 7$. 9. B. re=ene" 'ipolar and #S Analog Integrated &ircuit !esign"#iley" 1$<%/&((&. :(. M. Is+ail and T. 1ie'" Analog VLSI : Signal and Information Processing" Mc ra2.ill" 1$$%. 3>ut o, Print6 :1. 4. Mead" Analog VLSI and 9eural Systems" 9ddison-#esley" 1$<$. 3>ut o, Print6 :&. P. /. 9. Mo!an" /. Ra+ac!andran and M. N. S. S2a+y" S%itched &apacitor Filters : Theory, Analysis and !esign" Prentice-.all" 1$$7. :). E. S. >c!otta" T. Muk!er@ee" R. 9. Ruten=ar and 8. R. 4arley" Practical Synthesis of 2igh+Performance Analog &ircuits" Klu2er" 1$$<. :%. S. R. Nors2ort!y" R. Sc!reier and . 4. Te+es" !elta+Sigma !ata &on"erters : Theory, !esign, and Simulation"#iley/IEEE" 1$$:. :7. /. Peluso" M. Steyaert" #. M. 4. Sansen" !esign of Lo%+Voltage Lo%+Po%er & #S !elta+Sigma A3! &on"erters" Klu2er" 1$$$. ::. S. Ra=ii and B. 9. #ooley" !esign of Lo%+Voltage Lo%+Po%er Sigma+!elta odulators" Klu2er" 1$$<. :;. M. .. Ras!id" icroelectronic &ircuits : Analysis and !esign" T!o+son" 1$$$. :<. B. Ra'aEi" ,F icroelectronics" IEEE Press" 1$AA. :$. B. Ra'aEi" onolithic Phase+loc*ed Loops and &loc* ,eco"ery &ircuits : Theory and !esign" IEEE Press" 1$$:. ;(. B. Ra'aEi" Phase+loc*ing in 2igh+Performance Systems : From !e"ices to Architectures" #iley/IEEE Press" &((). ;1. R. 9. Ruten=ar" . . E. ielen and B. 9. 9ntao" &omputer+Aided !esign of Analog Integrated &ircuits and Systems" #iley/IEEE" &((&. ;&. *. SilEa-Martine'" M. Steyaert" and#. Sansen" 2igh+Performance & #S &ontinuous+ Time Filters" Klu2er" 1$$). ;). 4. To+a'ou" *. B. .uC!es" N. 4. Butters=y" S%itched &urrent : An Analog Techni/ue for !igital Techni/ues" IEE Press" 1$$). ;%. R. ?n=e!auen and 9. 4ic!ocki" #S S%itched &apacitor and &ontinuous+Time I&s and Systems" S5rinCer" 1$<$. ;7. P. #a+=neq and #. M. 4. Sansen" !istortion Analysis of Analog Integrated &ircuits" Klu2er" 1$$<. ;:. 4. *. #eis+an" The $ssential Guide to ,F and :ireless" Second Edition" Pearson/P." &((&. ;;. D. .. #olaEer" Phase+loc*ed Loop &ircuit !esign" Prentice-.all" 1$$1. May" &((: c 4EERI" Pilani &% DIT/SMDP-II >5tional Books VLSI Systems rchitecture, Com$uter rchitecture, DSP rchitecture

;<. D. E. 4o+er" $ssentials of &omputer Architecture" Pearson/P." &((%. ;$. 9. 8. De4eCa+a" Parallel Processing Architectures and VLSI 2ard%are" /olu+e 1" Prentice-.all" 1$<$. <(. ?. ol'e" VLSI &hip !esign %ith the 2!L Verilog" S5rinCer" 1$$:. <1. . Kane and *. .einric!" IPS ,IS& Architecture" Prentice-.all" 1$$&. <&. M. 8u" Arithmetic and Logic in &omputer Systems" #iley" &((%. <). M. Malone" The icroprocessor : A 'iography" S5rinCer" 1$$7. <%. M. Murdocca" &omputer #rgani1ation and Architechture" #iley" &((:. 3To 955ear6 <7. M. *. Murdocca and /. P. .eurinC" Principles of &omputer Architecture" Prentice.all" &(((. <:. N. Nisan" S. Sc!ocken" The $lements of &omputing Systems : 'uilding a odern &omputer from First Principles" MIT Press/P.I" &((A. 34!ea5 Edition6 <;. P. /. S. Rao" Perspecti"es in &omputer Architecture" P.I" &((A. 34!ea5 Edition6 <<. P. M. Sailer and D. R. Kaeli" The !L; Instruction Set Architecture 2andboo*" ElseEier/ MK" 1$$:. <$. SP9R4 International" SPA,& Architecture anual" Prentice-.all" 1$$&. $(. E. E. S2art'lander" &omputer Arithmetic" /olu+e I" IEEE Press" 1$$(. 3>ut o, Print6 $1. E. E. S2art'lander" &omputer Arithmetic" /olu+e II" IEEE Press" 1$$(. 3>ut o, Print6 $&. 4. T!i++annaCari" &P5 !esign : Ans%ers to Fre/uently As*ed 0uestions" S5rinCer" &((7. $). D. 8.#eaEer and T. er+ond" The SPA,& Architecture anual 6Version @7" Prentice.all" 1$$%. V&DL, Verilog and &DL'(ased Design $%. 8. Baker" V2!L Programming %ith Ad"anced Topics" #iley" 1$$). $7. *. B!asker" A Guide to V2!L Synta8" Prentice-.all" 1$$7. $:. D. R. 4oel!o" The V2!L 2andboo*" Klu2er" 1$<$. 3>ut o, Print6 $;. 9. De2ey" Analysis and !esign of !igital Systems %ith V2!L" T!o+son" 1$$;. $<. R. 8i5sett" 4. Sc!ae,er and 4. ?ssery" V2!L : 2ard%are !escription and !esign" Klu2er" 1$<$. 3>ut o, Print6 May" &((: c 4EERI" Pilani &7 DIT/SMDP-II >5tional Books $$. S. 8ee" Ad"anced !igital Logic !esign 5sing V2!L, State achines, and Synthesis for FPGAs" T!o+son" &((:. 1((. D. 8. Perry" V2!L : Programming by $8ample" 1ourt! Edition" Mc ra2-.ill" &((&. 34!ea5 Edition6 1(1. 4. .. Rot!" !igital System !esign %ith V2!L" T!o+son" 1$$<. 34!ea5 Edition6 1(&. M. 02olinski" !igital System !esign %ith V2!L" Second Edition" Prentice-.all" &((). 1(). N. M. Botros" 2!L Programming Fundamentals : V2!L and Verilog" T!o+son/Del+ar" &((:.

1(%. *. M. 8ee" Verilog 0uic*start" Klu2er" 1$$;. 1(7. S. 8ee" Ad"anced !igital Logic !esign 5sing Verilog, State achines, and Synthesis for FPGAs" T!o+son" &((:. 1(:. E. Mednick" $lements of Verilog Style" Prentice-.all" 1$$$. 1(;. /. SaCdeo" The &omplete Verilog 'oo*" Klu2er" 1$$<. VLSI)IC C D and lgorithms, &igh'Level Synthesis 1(<. E. 9arts and *. K. 8enstra" Local Search in &ombinatorial #ptimi1ation"#iley" 1$$;. 1($. R. 4a+5osano and #. #ol," 2igh+le"el VLSI Synthesis" Klu2er" 1$$1. 11(. S. DeEadas" 9. !os! and K. Keut'er" Logic Synthesis" Mc ra2-.ill" 1$$%. 111. 9. Kue!l+ann" The 'est of I&&A! : AB ?ears of $8cellence in &omputer+Aided !esign" S5rinCer" &((). 11&. E. 8a2ler" &ombinatorial #ptimi1ation : 9et%or*s and atroids" DoEer" &((1. 11). R. Mot2ani and P. RaC!aEan" ,andomi1ed Algorithms" 4?P" 1$$7. 11%. 4. .. Pa5adi+itriou and K. SteiClit'" &ombinatorial #ptimi1ation : Algorithms and &omple8ity" P.I" 1$<&. 34!ea5 Edition6 117. R. RaC!ura+" &omputer Simulation of $lectronic &ircuits" #iley" 1$<$. 34!ea5 Edition6 11:. S. Ru=in" &omputer Aids for VLSI !esign" 9ddison-#esley" 1$<;. 3>ut o, Print6 See http://www.rulabinsky.com/cavd/ ,or >nline Second Edition 11;. T. Sasao" S%itching Theory for Logic Synthesis" Klu2er" 1$$$. 11<. S. M. Tri+=erCer" An Introduction to &A! for VLSI" Klu2er" 1$<;. 3>ut o, Print6 11$. /. /. /a'irani" Appro8imation Algorithms" S5rinCer" &((%. May" &((: c 4EERI" Pilani &: DIT/SMDP-II >5tional Books 1&(. R. 9. #alker and R. 4a+5osano" A Sur"ey of 2igh+le"el Synthesis Systems" Klu2er" 1$$1. &ard*are)So+t*are Codesign, Embedded Systems 1&1. S. Ball" $mbedded icroprocessor Systems : ,eal :orld !esign" T!ird Edition" ElseEier/ Ne2nes" &((). 1&&. 9. S. BerCer" $mbedded Systems !esign : An Introduction to Processes, Tools and Techni/ues" 4MP Books" &((1. 1&). 4. .olla=auC!" $mbedded Linu8 : 2ard%are, Soft%are, and Interfacing" 9ddison#esley" &((&. 1&%. H. 8i and 4. Dao" ,eal+Time &oncepts for $mbedded Systems" 4MP Books" &((). 1&7. R. Nie+ann and P. Mar2edel" 2ard%are3Soft%are &o+!esign for !ata Flo% !ominated $mbedded Systems" Klu2er" 1$$<. 1&:. P. RaC!aEan" 9. 8ad and S. Neelakandan" $mbedded Linu8 System !esign and !e"elopment" 9uer=ac!" &((7. 1&;. K. DaC!+our" 'uilding $mbedded Linu8 Systems" >R9" &(().

1&<. T-D. Den and#.#ol," 2ard%are3Soft%are &o+Synthesis of !istributed $mbedded Systems" Klu2er" 1$$:. VLSI Testing, Testability and Formal Veri#cation 1&$. P. .. Bardell"#. .. Mc9nney and *. SaEir" 'uilt+in Self Test for VLSI : Pseudorandom Techni/ues" #iley" 1$<;. 1)(. .. Bleeker" P. Ean den Ei@nden and 1. de *onC" 'oundary+Scan Test : A Practical Approach" Klu2er" 1$$). 1)1. R. *. 1euCate and S. M. McIntyre" Introduction to VLSI Testing" Prentice-.all" 1$<<. 1)&. M. Nicolaidis" D. 0orian and D. K. Prad!an" #nline Testing for VLSI" Klu2er" 1$$<. 1)). /. N. Dar+olik" Fault !iagnosis of !igital &ircuits" #iley" 1$$(. Lo*'Po*er Design Techni,ues 1)%. S. S. Ro,ail and K-S. Deo" Lo%+Voltage Lo%+Po%er !igital 'i& #S &ircuits : &ircuit !esign, &omparati"e Study and Sensiti"ity" Prentice-.all" 1$$$. May" &((: c 4EERI" Pilani &; DIT/SMDP-II >5tional Books VLSI Interconnects and nalysis 1)7. 4. 9. .ar5er" $lectronic Pac*aging and Interconnection 2andboo*" Second Edition" Mc ra2-.ill" 1$$;. 1):. 4. 9. .ar5er and M. B. Miller" $lectronic Pac*aging, icroelectronics and Interconnection !ictionary" Mc ra2-.ill" 1$$). System Design, System rchitecture 1);. 4. 1. 4oo+=s" &oomb4s Printed &ircuits 2andboo*" 1i,t! Edition" Mc ra2-.ill" &((1. 1)<. I. EnClander" The Architecture of &omputer 2ard%are and Systems Soft%are : An Information Technology Approach" T!ird Edition"#iley" &((). 34!ea5 Edition6 1)$. T. ran=erC" 2andboo* of !igital Techni/ues for 2igh+Speed !esign" Prentice.all" &((%. 1%(. 9. *erraya and #. #ol," ultiprocessor Systems+on+&hips" ElseEier/MK" &((%.