Design, Prototype, and Deploy Digital Control Systems for Power Electronics Applications

Publish Date: Feb 25, 2013

Overview
This application note discusses a new design approach for the development of digital control systems for switching power electronics circuits. By taking advantage of the co-simulation capabilities between NI Multisim and NI LabVIEW, and the common National Instruments Reconfigurable I/O (NI RIO) architecture, designers can increase their productivity and reduce cost and time to market.

Table of Contents
1. Introduction 2. Application Requirements 3. Design: Analog Power Stage & Digital Controller 4. Prototype: NI CompactRIO 5. Deploy: NI Single-Board RIO 6. Conclusion 7. Additional Resources

1. Introduction
Digital controllers offer many advantages for power electronics applications where high efficiency, flexibility and size are important. Engineers have been using microprocessors and DSPs for the development of these control systems, however the complexity of these designs is high and prototypes are expensive. Furthermore, many design iterations are needed to test and validate these systems because there is a disconnect in the development tools, which results in higher costs and increased time to market. For instance, a typical DC motor control application requires the development of a power stage circuitry (analog design) to drive the DC motor, and a control algorithm (digital design). Traditionally both stages are developed and simulated separately which results in errors that can be propagated to the prototype stage. National Instruments offers a new design approach for power electronics applications. Designers can now simulate and optimize an entire system using system co-simulation. NI Multisim, a SPICE-based circuit design and simulation tool, is used to model and analyze the power stage; NI LabVIEW, a graphical programming environment, is used to design the digital controller. Then, the entire system is simulated and optimized using multi-domain co-simulation. Moreover, the code developed in the simulation stage can be compiled to physical hardware with minor modifications. In this application note, we design, prototype and deploy a digital speed controller for a brushed DC motor to illustrate the advantages of this new design approach for power electronics.

2. Application Requirements
The application requirements for the design are: Use a brushed DC motor with quadrature encoder. Run the motor using a 12 V supply. Spin an inertial load (0.001 kg m 2) periodically at 1200 RPM for 3 seconds and at -1200 RPM for 3 seconds. Speed overshoot must not exceed 1400 RPM. Motor must reach the final speed in under a second. Use 20 kHz for the PWM switching frequency.

3. Design: Analog Power Stage & Digital Controller

Analog Power Stage The analog power stage of the design provides the interface to connect and control the DC motor. Since one of the key application requirements for the design is that the motor must spin in both directions, the design can be built around a common H-bridge topology (Figure 1).

Figure 1. H-bridge topology The DC motor will be powered by a 12 V power supply that must be able to accelerate the motor to the required speed within the required amount of time (< 1s). Circuit simulation in Multisim can help the designer determine whether the available power supply meets this requirement. The circuit shown in Figure 2 was built and simulated in Multisim using one of the brushed DC machine SPICE models included in the Master Database. This model can be customized using the nominal motor parameters from the manufacturers datasheet.

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Figure 2. Circuit used to measure theoretical speed and current response Simulation results in Multisim (Figure 3) indicate that the motor is capable of reversing from -1200 RPM to +1200 RPM in 0.51 s, however the motor experiences a large inrush current of approximately 18 A when driven hard in the opposite direction. This can be resolved by applying voltage to the armature more gradually. After extensive simulation it is determined that by applying the 12 V supply with a slew rate limit of 34 V/s, the peak inrush current can be reduced to 13.5 A. With this approach it takes 0.7 s (instead of 0.51 s) to reach the desired speed, which is still within the design requirement.

Figure 3. Theoretical speed and current responses The switch selection for the H-bridge topology is based on the operating voltage and the maximum expected armature currents. This design features 58A N-channel MOSFETs for the low-side switch and 80A P-channel MOSFETs for the high-side. Also, a gate driver is selected for all the switches. Multisim simulation can also be used to model worst case switching losses. In preparation for the next step (digital controller design) you need to build a plant model to design and test the controller using co-simulation with Multisim and LabVIEW. In Figure 4 you can see the plant model in Multisim. Gate drivers are not considered in the plant model because their effect on the system dynamics is minimal.

Figure 4. Plant model in Multisim for co-simulation Digital Controller Design The digital controller is implemented in LabVIEW and consists of the following design blocks: speed decoder, PI controller, PWM Generator and H-bridge driver. Figure 5 shows a block diagram of the digital controller. All these blocks are implemented in LabVIEW, except the DC Motor (plant model). Table 1 provides details about the components of the digital controller.

Figure 5. Digital controller diagram Table 1. Elements of the digital controller Design Block Speed decoder PI controller PWM generator Description Calculates position, velocity and acceleration based on a quadrature encoder signal from the motor. Discretized PI controller designed to operate at a rate of 40 MHz (default clock speed for most FPGAs). A PWM duty cycle of 50-100% spins the motor in the clockwise (positive) direction, while a 0-50% PWM duty cycle spins the motor in the counter-clockwise (negative) direction. Converts the PWM duty cycle into the drive signals for the H-bridge switches.

H-bridge driver System Co-simulation

Now that the analog power stage and the digital controller design have been completed, the entire system can be analyzed and optimized using Multisim-LabVIEW co-simulation without the need of building a physical prototype. This reduces design iterations because errors can be detected and fixed early in the design flow. Furthermore, the LabVIEW code created for the system simulation can be reused and implemented in hardware with minimal changes. In the co-simulation environment, the Multisim and LabVIEW simulation engines concurrently perform a non linear time-domain analysis, exchanging data at the end of each time-step. This means

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In the co-simulation environment, the Multisim and LabVIEW simulation engines concurrently perform a non linear time-domain analysis, exchanging data at the end of each time-step. This means the simulation results are accurate because all the system dynamics is taken into consideration. The LabVIEW block diagram for the system simulation is shown in Figure 6.

Figure 6. Closed loop system simulation in LabVIEW From the previous figure you can see that nodes 1-4 are elements of the digital controller: 1. Speed decoder 2. PI controller 3. PWM generator 4. H-bridge driver The plant model, represented by node 5, consists of the MOSFET switches, brushed DC motor, and an optical encoder executing in the Multisim simulation environment. Figure 7 features a 1 s simulation of the system setting the motor speed from stopping to 1200 RPM. In the graph, the setting speed is represented by the red trace. The yellow trace depicts the simulated sensed speed. These results show that the design meets the application requirements.

Figure 7. Co-simulation results With Multisim and LabVIEW co-simulation designers can also evaluate current peaks and control signals, assess the efficiency of speed encoding/decoding and predict the transient time response of the motor speed build-up. Click here to get more technical details on the LabVIEW-Multisim co-simulation for the DC Motor controller design.

4. Prototype: NI CompactRIO
After evaluating the system co-simulation results and fine tuning the digital controller, designers have confidence to develop a physical prototype. An FPGA-based platform like NI CompactRIO can be used to deploy the code of the digital controller and the analog stage can be built on a protoboard. The NI cRIO-9074 controller features a Xilinx Spartan-2 2M FPGA and a 400 Mhz real-time processor, 8 slots for I/O modules and communication ports. In this stage there is no need to create new LabVIEW code to program the digital controller in the CompactRIO controller, we can simply reuse (with minor modifications) the same code developed for the system co-simulation. In Figure 8 we can see that nodes 1-4 are the same nodes that were used for Multisim and LabVIEW co-simulation.

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Figure 8. FPGA implementation of the motor controller The analog power stage (H-bridge and gate drivers) is prototyped on a basic protoboard using discrete components. NI CompactRIO I/O modules are used to sample the armature current and interface with the velocity encoder and the gate drivers. Figure 9 shows a photograph of the first physical prototype.

Figure 9. DC motor controller prototype In order to have a more solid prototype for testing purposes, designers can build a Printed Circuit Board (PCB) of the analog circuitry using Multisim and Ultiboard. One of the advantages of Multisim for quick prototyping is its database of connector symbols and footprints for NI hardware (for instance: CompactRIO, Single-Board RIO), which saves time and reduces errors. In addition, Multisim includes industry standard connectors from leading manufacturers. Once the Multisim schematic is transferred to Ultiboard, designers can take advantage of a flexible and friendly environment optimized for rapid PCB design. In Figure 10 you can see the PCB design of the analog circuitry for the DC motor controller. This is a four-layer board with a current rating of 20 A. Ultiboard can generate all the standard files (Geber, DXF, NC Drill) needed to fabricate the PCB.

Figure 10. PCB design in Ultiboard

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Figure 11. DC motor controller prototype with PCB created in Multisim and Ultiboard Click here to get more technical details on how to use Multisim and Ultiboard for quick prototyping.

5. Deploy: NI Single-Board RIO

For high-volume and OEM applications designers can take advantage of the NI Single-Board RIO embedded products. These embedded devices offer the same hardware architecture as NI CompactRIO in a board-level reconfigurable system. The digital controller for the DC motor can be easily implemented on a NI Single-Board RIO device with minor modifications to the design. The NI sbRIO-9606 (Figure 12) offers the smallest form factor of the Single-Board RIO family. This device features a RIO Mezzanine Card (RMC) connector, which is a high-speed connector that provides direct access to the processor and 96 3.3 V digital I/O FPGA lines. With Multisim and Ultiboard designers can create custom boards (or RIO Mezzanine Cards) to take more advantage of the platform.

Figure 12. Back view of the sbRIO-9606 featuring a RMC connector For the DC motor controller design the digital stage can be deployed to the sbRIO-9606 with minor changes to the LabVIEW code. These modifications are needed to ensure you use the appropriate I/O in the Single-Board RIO device. On the other hand, a RIO Mezzanine Card containing the analog circuitry can be designed with Multisim and Ultiboard; Figure 13 shows a photograph of the final design.

Figure 13. DC motor controller deployment The custom board features push buttons that the user can use to set/change the desired speed and an LCD screen that displays the current speed and direction of the motor controller. The digital

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The custom board features push buttons that the user can use to set/change the desired speed and an LCD screen that displays the current speed and direction of the motor controller. The digital controller is running in the sbRIO-9606, which is attached to the custom board (Figure 14).

Figure 14. Secondary side of the custom board with the sbRIO-9606 attached Click here to get more technical details of the DC motor controller implementation with Multisim and Single-Board RIO.

6. Conclusion
In this application note we discussed a new design approach for power electronics applications with Multisim, LabVIEW and the NI RIO platform. By using system co-simulation and the common hardware architecture offered by NI RIO devices, designers can quickly develop and optimize digital control systems for switching power electronics circuits.

7. Additional Resources
Introduction to Digital and Analog Co-simulation Between NI LabVIEW and NI Multisim Power Electronics Development Center Power Electronics Design Guide & Evaluation Software Download

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