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SRAM Cell and Column IO Design
SRAM Cell and Column IO Design
3/16/2005
RAS
EECE481 Lecture 18
bitline 2n
=256
n=8
2m
Column Mux
Read/Write
Sense amplifier
Write driver
Data In RAS EECE481 Lecture 18 Data Out 2
EECE481
3/16/2005
inverter 1
Single Stage Noise Margin
2 1 a a inverter 2
Bitline
Bitline
VOL VS
VOH
Read and write operations use the same port. There is one wordline and two bit lines. The bit lines carry complementary data, a fact that will be used to reduce access time. The cell layout is small since it has a small number of wires (but large relative to DRAM).
RAS EECE481 Lecture 18 3
Cell Design
Problem: Find wa, wd, wp such that 1) minimize cell area 2) obtain good read and write cell margins 3) good soft error immunity 4) good cell read current in that order
wl
Vdd wp a wa a wd Vdd Vdd
Since the cell is symmetric we need only design three transistor sizes
RAS
EECE481 Lecture 18
EECE481
3/16/2005
Icell =
b M6 M4
Cbit V
wl
trigger
Icell
M3
M5 a (=0)
b,b
Cbit
(1=) a M2
a a
Cbit
M1
wl
RAS
Need to make sure M4 is strong enough to pull internal node a low while M6 is trying to pull it high Use switching threshold as trigger point for regenerative switch point; usually want to make it less than the switching threshold This will force inverter M5-M1 switch to new state Make ratio of currents between M4 and M6 about 3 to 4
Vdd
M5 M3 a M1 ( = 0)
M6 M4 (1=) a M2
wl b a a b
Vdd
~Gnd
EECE481
3/16/2005
Layout of SRAM cell word line running horizontally bit lines running vertically cross-coupled inverters on top access transistors on bottom Portion of the core array using SRAM cell scaled in dimensions compared to single bit cell 2 cells across, 3 cells high replicated in this manner to build the core array
RAS EECE481 Lecture 18 7
Wordline Capacitance
Word line presents a large capacitance to the decoder Each cell loads the word line with two transistor capacitances and one wire capacitance (plus wire resistance) Total capacitance is the capacitance per cell x number of cells on word line clock
b b b b b b w1
Row Address Bits
w2 x x x w3
1 wordline 2 a a
decoder
w4 w5
RAS EECE481 Lecture 18
Bitline
Bitline
EECE481
3/16/2005
Bitline Capacitance
Load capacitance is mostly self-loading of the cells Drain cap and drain contacts (0.5-1 fF) of transistors are shared Junctions are biased at Vdd (lower cap than normal) Wire capacitance ~ .2fF/micron of wire
clock
b b
b w1
w2 w3 w4
decoder
Bitline
Bitline
w5
RAS EECE481 Lecture 18 10
EECE481
3/16/2005
b b,b PC
b
VDD
Latch-based
Sense amplifier
b,b PC wl
EECE481 Lecture 18
VDD
wl
RAS
PC
VDD VDD-VTN
11
Write Circuitry
M7 M8 clk
Precharge bitlines high Pull one column line low Turn on word line Wait until internal values of cell are established Turn off word line Design precharge transistors to pull bit lines high Design write drivers to pull one side low depending on data value
RAS
pre
cell pre
Cbit Cbit
addr data
wl
b a WL
cell a
col
b, b
M13
M14
Write Driver
col.sel.
EECE481 Lecture 18
M15
12
EECE481
3/16/2005
Read Circuitry
Precharge bitlines high Turn on word line One line will slowly discharge Wait until bit line reaches required low voltage level Turn on column select Amplify difference with sense amplifier
WL
Cbit Cbit
pre
M7 cell
cell a a
wl
trigger
Design sense amplifier M9 based on desired response time and power col.enable requirements Use precharge based on enable type of sense amp used.
RAS
Sense
out Output
13
Column Decoder/Mux
Need decoder for column address followed by a mux to select column for input or output operations Require two outputs to drive complementary pass gates Since the requirements for read and write are different can use separate read and write IO lines Have PMOS access for the read IO lines, since the read happens near Vdd Have NMOS devices for the write IO lines, since you need to drive bitlines to Gnd (see next slide)
RAS
cell
cell
cell
cell
cell
cell
cell
cell
1
C O L U M N D E C O D E R
2 3
col addr
2M
EECE481 Lecture 18
14
EECE481
3/16/2005
RAS
EECE481 Lecture 18
15
COLUMNS Bi
A1 A1
Bi + 1
Bi + 2
B i+ 3
A2 A
2
TREE DECODER
SENSE CIRCUIT
EECE481 Lecture 18
16
EECE481
3/16/2005
RAS
EECE481 Lecture 18
17
Building Amplifiers
We need an amplifier to handle small voltage swings on the bit lines for fast operation Normally you need to choose between Drawing DC power (diff. sense amplifier) Using a clock edge (latch-based amplifier)
(to turn DC power on only when the signal is present)
For CMOS logic gates When input is at VDD or Gnd, one of the transistors is off Nothing can happen until this transistor turns on
And even then you need to wait some more for gate to switch Sitting in low gain region of transfer curve
EECE481
3/16/2005
Bit
VDD
Bit_b
SenseEnable
RAS
EECE481 Lecture 18
19
SenseEnable
Sense_b
M2
M3
Sense
M1
EECE481 Lecture 18
20
10