INTRODUCTION TO MICROPROCESSOR MICROPROCESSOR is the single chip CPU in all the microcomputers. The follo ing topics !

!eals microprocessor" its architecture" programming an! interfacing. #. Microcomputer arrangement $. Memor% a general !iscussion &. Rea! onl% memor% 'ROM( ). Ran!om access memor% 'R*M( +. Microprocessor as CPU ,. Input unit -. Output unit .. S%stem /us an! /us structure 0. E1ecution of an instruction INTRODUCTION TO MICROCOMPUTER. *n% !igital computer s%stem has /asicall% four functional /loc2s MEMORY ith the

INPUT #. INPUT UNIT

CPU

OUTPUT

$. CENTR*3 PROCESSIN4 UNIT 'CPU( &. MEMOR5 UNIT ). OUTPUT UNIT COMUPUTER 6 * computer is a large electronic !ata processor that accepts certain input an! a set of instructions calle! a program an! !eli7ers the !esire! output. D*T* * !ata is a collection of ra material consisting of facts an! figures" hich !o not re7eal an% meaning on their o n. IN8ORM*TION * process !ata is 2no n as information an! the information can act as !ata for another information.

T5PES O8 COMPUTERS *N*3O4 Computers that or2s on the principle of 7ar%ing ph%sical 9uantities are calle! analog computers. DI4IT*3 Computers that or2s on !iscrete 7alues are terme! as !igital computers. :5;RID These computers are com/ination of /oth analog an! !igital computers. INPUT UNIT The input unit is use! for accepting !ata an! instructions from the user. OUTPUT UNIT6The output unit re!irects the information from the memor% unit to the output ser7ices li2e monitor" printer etc. MEMOR5 UNIT The memor% unit acts as the storage me!ium" the entire !ata an! the instructions fe! into the computer are store! in the memor% for processing /% the *3U. There are t o t%pes of memor% namel% ROM an! R*M. ;oth ROM < R*M are calle! primar% memor%. ROM 'Rea! onl% memor%( the ROM is a permanent memor%. The contents of the memor% are not ipe! out hen the po er is s itche! off. *lso the user ill not /e a/le to rite or store an% of his !ata into this memor%. the user cannot change the contents hen he ants to" to o7ercome this pro/lem EPROMs ere intro!uce!. EPROM is an Erasa/le Programma/le Rea! Onl% Memor%" the user can /ut e7en a single EPROM an! loa! the chip using an EPROM programmer. R*M 'Ran!om access memor%( it is highl% 7olatile memor%" this memor% contents of R*M are erase! if the po er suppl% to the memor% is s itche! off. There are /asicall% t o t%pes of R*Ms. #. Static R*M'SR*M( /inar% information is store! in flip flops" one /it for each flip6flop " a large num/er of flip flops are arrange! in the form of a matri1 'comprising of num/er of ro s an! columns( * =>? or a?#? can /e store! temporaril% in a flip flop. $. D%namic R*M'DR*M( /inar% #s an! >s are store! as an electric change or no change on a tin% capacitor. *3U The *3U is the area of the computer here mathematical an! logical calculations ta2e place.

T:E S5STEM ;US *ND ;US STRUCTURE @arious inputAoutput units an! memories are connecte! to the CPU /% a group of lines calle! a /us. * /us is a set of con!uctors carr%ing signals. The s%stem /us contain three /uses. #. *!!ress /us the a!!ress /us carries the a!!ress of memor%" input or output unit for the CPU that is the CPU sen!s out the a!!ress of the memor% location or the input A output ports that is to /e ritten or rea! from. On the a!!ress /us" information transfer ta2es place onl% in one !irection" from the microprocessor to the memor% or IAO elements. Therefore a!!ress /us is calle! as uni!irectional /us. The num/er of memor% locations that a CPU can a!!ress is !etermine! /% the num/er of a!!ress lines. If the CPU has N a!!ress lines" then it can !irectl% a!!ress $ N memor% locations. $. Data /us is use! to transfer !ata /et een the processor an! memor% or IAO the !ata /us consists of ."#, or &$ parallel signal lines. The . /it microprocessor .>.+ has . /it !ata /us. The #, /it microprocessor .>., uses #, /it !ata /us. The !ata /us is /i!irectional. This means that the CPU can rea! !ata in from memor% or from an input port or it can sen! !ata out to memor% or an output port on these lines.

&. Control /us is use! to transmit signals that are use! to s%nchroniBe the operation of the in!i7i!ual microcomputer elements. The CPU issues RD an! CR control signals for rea! an! rite operations. These control signals are uni!irectional from CPU to memor% or IAO. to rea! a /%te of !ata from a memor% location the CPU sen!s out the memor% a!!ress of the !esire! /%te on the a!!ress /us an! then sen!s out a memor% rea! signal on the control /us. The memor% rea! signal ena/les the a!!resse! memor% !e7ice to output a !ata on the !ata /us. The !ata from the memor% no reaches the CPU trough the !ata /us. MICROCOMPUTER OR4*NIS*TION

ADDRESS BUS

CPU MEMORY INPUT OUTPUT

DATA BUS

CONTROL BUS

EDECUTION O8 *N INSTRUCTION *ssem/l% language program is ritten using instructions hich are pro7i!e! /% the manufacturer of the microprocessor. The instructions are in mnemonic form an! each instruction has to /e con7erte! into /inar% co!es ith the help of a manual. The /inar% co!es also 2no n as he1 co!es or the machine co!es are to /e entere! in successi7e locations of the users memor%. Some instructions are represente! /% Eust one /%te represente! /% t o or more /%tes an! so occup% t o or more memor% locations. To e1ecute that instruction #. The microprocessor sen!s the a!!ress of the memor% location to the R*M chip using the a!!ress /us. $. * memor% rea! control signal is issue! /% the microprocessor to the R*M chip through the control /us. &. The contents of the memor% 'the machine co!e( no e1ecution. reach the !ata /us an! enters the microprocessor for

COMMUNIC*TION ;ETCEEN CPU *ND MEMOR5 *DDRESS D*T*

ADDRESS BUS MICROPROCESS OR MEMOR5 RE*D - - - - --- --- -- - - - - - - - - - ---

D*T* ;US

.>.+ MICROPROCESSOR Intel .>.+ is an .6/it microprocessor. It operates on .6/it /inar% or!s. That is it has .6/it !ata /us an! its arithmetic an! logic unit an! internal registers use .6/its. The .>.+ s%stem has #,6/it a!!ress /us an! hence it can a!!ress an% one of $#, memor% locations. .>.+ microprocessor pinout !iagram fig .>.+ pin6out signal function !iagram .>.+ fig PIN 8UNCTIONS O8 .>.+ Intel .>.+ is fa/ricate! on a single 3SI'3arge Scale Integration( chip an! pac2age! in )> pin !ual in line pac2age. The pin !etails are in fig a/o7e an! the pin out signal function !iagram are gi7en in fig. the functions of !ifferent pins are !iscusse! /elo *.6*#+ 'pins $# $.( The most significant eight /its of the #,6/it a!!ress /us is sent o7er these pins. The .6/it IAO a!!ress is also sent along these lines !uring IN an! OUT instructions. *D>6*D- 'pins #$ #0( The eight !ata /its D>6D- an! the lo er or!er a!!ress /its *>6*- are multiple1e! an! sent through these pins. Chile e1ecuting instructions !uring the /eginning of each machine c%cle" the microprocessor .>.+ sen!s out the a!!ress * >6*an! in the later part of the machine c%cle the processor sen!s out the !ata D >6D-

*3E 'pin &>(

*3E stan!s for a!!ress latch ena/le" e ha7e Eust seen that *D >6*D- are multiple1e! a!!ressA!ata lines. *t the /eginning of each machine c%cle 'first cloc2 perio!( .>.+ sen!s the a!!ress * >6*- o7er the lines *D>6*D- !uring the same perio! .>.+ sen!s out a pulse calle! *3E. IOAM 'pin &)( The logic le7el of IOAM tells e1ternal circuitr% hether an IAO or memor% transfer is ta2ing place. Chen the pin is in # state" it in!icates an IAO relate! operation an! hen the pin is in > state" it in!icates a memor% relate! operation. RD 'pin &$( * logic > on this pin in!icates that the processor is performing either a memor% rea! or an IAO rea! operation. * rea! /us c%cle is in progress. CR 'pin &#( * logic > on this pin in!icates that the processor is performing either a memor% rite or an IAO rite operation. * rite /us c%cle is in progress. S#6S> 'pin &&"$0( These are status signals sent /% microprocessor an! can /e use! to 2no performs. This is gi7en in ta/le S# > > # # S> > # > # Status :alt Crite Rea! Opco!e fetch the t%pe of current operation the .>.+

Com/ining IOAM ith S# an! S> more specific information a/out the machine c%cle status can /e o/taine! IOAM > > # # > # :F 'high impe!ance( S# # > # > # # > S> > # > # # # > Machine c%cle Status Memor% rea! Memor% rite IAO Rea! IAO Crite Opco!e fetch Interrupt ac2no le!ge :alt

D#D$'pins #" $( * cr%stal is connecte! at these pins. E1cept for the cr%stal the re9uire! circuit to ma2e a cr%stal controlle! oscillator is integrate! ithin the chip. Usuall% a cr%stal of fre9uenc% ,.#)) M:B is use!. This arrangement generate! ,.#)) million cloc2 pulses per secon!. This fre9uenc% is internall% !i7i!e! /% t o an! the operating fre9uenc% of the .>.+ s%stem.

C3GOUT 'PIN &-( S%stem cloc2 of fre9uenc% &.>-$ M:B is output through this pin" so that other peripheral chips can ma2e use of this sta/le cloc2. SID 'PIN +( Serial input !ata line use! ith serial communication. The !ata on this line is loa!e! as /it . in the accumulator RIM instruction is e1ecute!. SOD 'PIN )( Serial output !ata line use! instruction. INTR 'PIN #>( This is an interrupt re9uest pin. It is use! as a general purpose interrupt. Chen .>.+ is interrupte! using this pin" the processor completes the current instruction an! !i7erts to e1ecute an interrupt ser7ice routine. The interrupt can /e ena/le! or !isa/le! /% soft are. INT* 'PIN ##( It is an interrupt ac2no le!ge signal after INTR is recei7e! RST +.+" RST ,.+ an! RST -.+ 'pin0". an! -( Restart interrupt. These are 7ectore! interrupts an! transfer the program control to specific memor% locations as sho /elo RST +.+ program counter mo!ifie! to >>$C: RST ,.+ program counter mo!ifie! to >>&): RST -.+6 program counter mo!ifie! to >>&C: TR*P 'pin ,( This is a non mas2a/le interrupt. Chen an interrupt occurs through the pin" the program control is transferre! to the memor% location >>$): RESETIN 'pin&,( *n acti7e lo signal on this pin resets the microprocessor the program counter is ma!e >>>> : an! e1ecution of instructions start from that point. The /uses are also tri state!. ith serial communication. The output SOD is set or reset as specifie! /% the SIM hen

RESET OUT 'PIN &( Reset out in!icates that the cpu is /eing reset it can /e use! to reset all the peripheral chips connecte! to the microprocessor. :O3D 'PIN &0(

* logic # on this pin in!icates that another master circuit is re9uesting the use of a!!ress an! !ata /uses. The cpuupon recei7ing the :O3D re9uest" ill relin9uish the use of the /us after completing the current /us transfer. :3D* 'PIN &.( This is hol! ac2no le!ge pin it in!icates that the cpu has recei7e! the :O3D re9uest ill relin9uish the /us in the ne1t c%cle. RE*D5 'PIN &+( If RE*D5 is high !uring a rea! or rite c%cle" it in!icates that the memor% or peripheral is rea!% to sen! or recei7e !ata. If RE*D5 is lo " the CPU ill ait for an integral num/er of cloc2 c%cles. This is use! hen the e1ternal memor% or IAO !e7ices connecte! to the microprocessor ha7e a slo er response. *RC:ITECTURE O8 .>.+ The internal architecture of the microprocessor .>.+ inclu!es the follo ing units Register arra% the .>.+ has si1 general purpose registers name! as ;"C"D"E": an! 3. each register can hol! an .6/it !ata. The si1 registers can also /e com/ine! as register pairs ;C"DE an! :3. The instruction set of .>.+ contains a num/er of instructions to mo7e a !ata from one register to another register. * register pair can hol! a #, /it !ata or #, /it a!!ress. Program counter 6 the program counter is a #, /it register. The pc hol!s the #, /it a!!ress of the memor% from hich the ne1t /%te is to /e fetche!. The /%te ma% correspon! to an opco!e of an instruction or simpl% an .6/it !ata. Chen a /%te is /eing fetche! the program counter is automaticall% incremente! /% one to point to the ne1t memor% location. Stac2 pointer the stac2 pointer is also a #, /it register. It hol!s the a!!ress of the stac2 top. * stac2 is a group of memor% locations in R*M !efine! /% the programmer. The stac2 is use! to sa7e the contents of the registers an! !uring interrupts an! su/routine calls. *!!ress latch increment A !ecrementer The a!!ress latch is useful in selecting the a!!ress of the memor% to /e sent out from program counter or stac2 pointer or an% of the register pairs. *n incrementer an! !ecrementer allo s the contents of an% of the #,6/it registers hich hol! the a!!ress to /e incremente! or !ecremente!. *3U an! associate! circuitr% The arithmetic logic unit of .>.+ performs arithmetic an! logic operations on t o .6/it !ata. The *3U com/ines ith a special register calle! the accumulator" a temporar% register an! fi7e flag flip flops to carr% out the arithmetic operations.

The *ccumulator is a special .6/it register. This register is use! to store .6/it !ata as ell as to perform arithmetic an! logic operations. This register is i!entifie! as *. hile performing arithmetic operation li2e a!!ition one of the operan! is automaticall% assume! to /e in * register. *lso the result of the a!!ition is place! in * register. 8rom the e1ample the instruction *DD ; Temporar% register simpl% recei7es one of the operan!s from the internal !ata /us an! sen!s it to the *3U. The other operan! is recei7e! from the accumulator an! the re9uire! arithmetic or logic operation is carrie! out. *DD ; the

contents of * register !irectl% goes to *3U /ut the contents of ; register is first sent to the temporar% register an! then to the alu. INSTRUCTION SET O8 .>.+ I M*C:INE 3*N4U*4E *ND *SSEM;35 3*N4U*4E there are instructions in .>.+ hich re9uire t o or three /%tes an! the% are store! in t o or three successi7e memor% location. The /inar% form of the program is 2no n as machine language. Other or!s programs ritten using mnemonic form of instructions are 2no n as assem/l% language program. D*T* TR*NS8ER INSTRUCTIONS I Mo7e instructionsH #. Mo7e /et een register an! register these instructions cop% an .6/it register to another .6/it register. The register use! are *" ;" C" D" E" : an! 3. the general form of mo7e instruction is MO@ r !"rs in this instruction MO@ is opco!e an! r!"rs are operan!s. $. Mo7e /et een register an! memor% the letter M is use! to represent memor%. There are thousan!s of memor% locations an! each location has a !istinct a!!ress. In .>.+ the !esire! #,6/it memor% a!!ress is first loa!e! in :3 register /efore using an% instruction M '':3(( ' r ( an! ' r ( M'':3(( ':3( represent content of :3 register '':3 (( represents contents of memor% hose a!!ress is a7aila/le in :3 register pair M ith '':3(( is optional. &. Mo7e imme!iate instruction the mo7e imme!iate instruction has the form M@I r" !ata . an! M@I M" !ata . Chere r is a general purpose register or accumulator an! M refers to memor%. This instruction transfers the /%te of !ata specifie! ithin the instruction itself to a register or memor%. ' r ( !ata . an! M'':3(( !ata . ). 3oa! imme!iate register pair '3oa! e1ten!e! imme!iate( The loa! imme!iate register pair instruction is use! to loa! a #, /it imme!iate !ata into a specifie! register pair. Since #,6 /it num/er is in7ol7e! the or! e1ten!e! is also use!. The general form of this instruction is 3DI rp" !ata #,

Chere rp stan!s for one of the register pairs ;C" DE" :3 or the #,6/it stac2 pointer SP. ' rp ( !ata #, 3DI :" $>+>: ill loa! three /it instructions. +. Store accumulator !irect ST* a!!r stores the contents of the accumulator in the memor% hose a!!ress is specifie! in the instruction itself. M 'a!!r( '*( ST* $++>:

,. 3oa! accumulator !irect 3D* a!!r loa!s the accumulator ith a /%te from the memor% location hose a!!ress is specifie! in the instructions itself. (A) M'a!!r> 3D* $)+>: *RIT:METIC INSTRUCTIONS #. *!!ition instructions i( *DD ith register A memor% the a!! instructions *DD r an! *DD M are use! to a!! the contents of a specifie! register or memor% to the contents of the accumulator. The result is store! in the accumulator. (A) '*( I ' r ( ii( '*( '*( I ';(

*DD imme!iate the a!! imme!iate instruction *DI !ata ." a!!s the contents of the accumulator ith an . /it !ata that is inclu!e! in the instruction itself '*('*( I!ata .

iii(

*DD ith carr% instruction is use! to a!! the contents of a specifie! register or memor% along ith carr% flag to the contents of the accumulator. The result is store! in the accumulator. The instruction is of the form *DC r an! *DC M

i7(

*DD imme!iate ith carr%6 this instruction if of the form *CI !ata . an! a!!s ith carr% the contents of the accumulator ith an . /it !ata that is inclu!e! in the instruction itself. (A) '*( I !ata . I c%

$. Su/tract instructions i( SU; ith register A memor% the su/tract instructions SU; r an! SU; M are use! to su/tract the contents of a specifie! register or memor% from the contents of the accumulator. The result is store! in the accumulator. ' *( '*( ' r (

ii(

SU; imme!iate instruction SUI !ata ." su/tracts the .6/it !ata that is inclu!e! in the instruction from the accumulator. (A) '*( !ata .

iii(

SU; ith /orro The su/tract ith /orro instruction is use! to su/tract the contents of a specifie! register or memor% along ith /orro from the contents of the accumulator. The result is store! in the accumulator. The instruction is of the form S;; r an! S;; M

(A) ' *( ' r ( C% '*(' *( ' ; ( 66 C% i7( SU; imme!iate ith /orro This instruction is of the form S;I !ata . an! su/tracts a !ata /%te ith /orro 'carr% flag( from the contents of the accumulator an! places the result in the accumulator. The .6/it !ata is inclu!e! in the instruction itself. (A) '*( !ata . 66 C%. &. Increment A Decrement instructions i( Increment Register or memor% The instruction INR r increments the contents of the specifie! register /% #. ' r( ' r ( I # The instruction INR M increments the contents of memor% location pointe! to /% :3 register /% #. ii( Decrement register or memor% The instruction DCR r !ecrements the contents of the specifie! register /% #. ' r( ' r ( 6 # The instruction DCR M !ecrements the contents of memor% location pointe! to /% :3 register /% #. iii( Increment register memor% The instruction IND rp increments the contents of the specifie! register pair /% #. ' rp ( ' rp ( I # The register pairs use! are ;C"DE" :l an! the #,6/it stac2 pointer i7( Decrement register pair The instruction DCD rp !ecrements the contents of the specifie! register pair /% #. ' rp ( ' rp ( 6 # The register pairs use! aer ;C"DE" :3 an! the #,6 /it stac2 pointer. ). Dou/le a!! instructions The instruction D*D rp a!!s the contents of the specifie! register pair to :3 register pair. The result is left in the :3 register pair. ':3( ':3( I 'rp( D*D ; instruction a!!s the contents of ;C register pair ith the contents of :3 register pair an! the #,6/it result is store! in :3 register pair. This instruction is useful to a!! t o #,6/it num/ers ith one instruction. 3O4IC INSTRUCTIONS a( *ND instructions

i( *ND ith register A memor% ii( *ND Imme!iate /( OR instructions i( OR ith registerA memor% ii( OR imme!iate c( ED6 OR instructions i( ED6OR ith register A memor% ii( ED6OR imme!iate !( Compare instructions i( Compare ith register A memor% ii( Compare imme!iate e( Rotate instructions i( Rotate accumulator left ithout carr% ii( Rotate accumulator left through carr% iii( Rotate accumulator right ithout carr% i7(Rotate accumulator right through carr% SPECI*3 INSTRUCTIONS a(Decimal a!Eust accumulator instruction /( Complement *ccumulator c( Set Carr% !( Complement Carr%

INSTRUCTION SET O8 .>.+ II

D*T* TR*NS8ER INSTRUCTIONS II

a(Store accumulator in!irect /(3oa! accumulator in!irect c( Store : an! 3 Direct !( 3oa! : an! 3 Direct e( E1change the register pairs :3 an! DE

f( E1change stac26top ith : an! 3 ;R*NC: INSTRUCTIONS a(Jump instruction i(Uncon!itional Eump ii(Con!itional Eump /( call an! return instructions i( uncon!itional call an! return instructions ii( con!itional call an! return c( Restart instructions !( 3oa! program counter ith :3 instructions ST*CG *ND ST*CG RE3*TED INSTRUCTIONS PUS: instruction POP instruction IAO M*C:INE CONTRO3 INSTRUCTIONS a(IAO instructions /(Machine control instructions i(:alt instructions ii(No operation instruction iii( Interrupt relate! instructions .>.+ *DDRESSIN4 MODES i(Direct a!!ressing ii( Register a!!ressing iii( Register in!irect a!!ressing i7(Imme!iate a!!ressing 7(Implie! a!!ressing A implicit a!!ressing

.>.+ INSTRUCTIONM TIMIN4S *ND DE3*5 C*3CU3*TIONS T6 ST*TE M*C:INE C5C3E MEMOR5 RE*D C5C3E

MEMOR5 CRITE C5C3E.