Digital Systems Design

VHDL Synthesis by Example

A Comprehensive tutorial for VHDL can be found by clicking the following link VHDL Tutorial

Introduction
Hardware Description Languages (HDLs allow!

"fficient description of large systems Automation of synthesis algorithms #imulation of designs

$ost popular are Verilog and VHDL A%"L (Advanced %oolean "&pression Language is simpler' also used e&tensively( )n this lesson' we will concentrate on Hardware Description Language VHDL for describing basic systems like A*D' +, and full adder(

Learning Objectives
As described above' the purpose of this lesson is to introduce you to the basic VHDL concepts( At the end of this lesson' you should be able to!

$odel simple combinational and se-uential circuits for simulation and synthesis(

What is VHDL
VHDL (VH#)C' i(e( Very High #peed )ntegrated Circuit Hardware Description Language is a hardware description programming language useful for documentation' simulation and synthesis( VHDL is suited to the specification, design and description of digital electronic hardware. )t is used to describe the structure and behavior of A#)Cs' ./0As as well as conventional digital circuits( )t is an international standard' regulated by the )"""( The definition of the language is non1proprietary( #imulation and synthesis are the two main kinds of tools that we will be using which operate on this language( Designs can be described using top down' bottom up or middle out methodology( Thus hardware can be described at the gate level or in a more abstract way using VHDL( !rie" History#

1981 Initiated by US DoD to address hardware life-cycle crisis 1983-85 Development of baseline lang age by Intermetrics! I"# and $I 198% &ll rights transferred to I''' 198( ) blication of I''' Standard 198( #il Std *5* re+ ires comprehensive ,-D. descriptions to be delivered with &SI/s 199* 0evised standard 1named ,-D. 12(%-19933 The development of VHDL was initiated in 2342 by the 5nited #tates Department of Defense to address the hardware life cycle crisis( The cost of reproducing electronic hardware as technologies became obsolete was reaching crisis point' because the function of the parts was not ade-uately documented' and the various components making up a system were individually verified using a wide range of different and incompatible simulation languages and tools( The re-uirement was for a language with a wide range of descriptive capability that would wor4 the same on any simulator and was independent of technology or design methodology( The standardi6ation process for VHDL was uni-ue in that the participation and feedback from industry was sought at an early stage( A baseline language (version 7(8 was published 8 years before the standard so that tool development could begin in earnest in advance of the standard( All rights to the language definition were given away by the DoD to the )""" in order to encourage industry acceptance and investment( The high level design flow for an A#)C (ie( gate array' standard cell or ./0A can be summari6ed as follows!

!eni"its o" VHDL VHDL is defined by )"""( This standard is known by all the VHDL tool developers( #o there is only one language to learn( This language is used by all the circuit designers around the world( The life time for this language is assured' since it is an )""" standards( Any investment or learning is assured for lifetime( Abundance of models available from different sources can be used with ease( #ome tools might support .oreign Language )nterface' by which you can add your model in C language to the VHDL code( )t is a modern language' powerful and general( +ther advantages include readability of the code and portability( The code developed is portable to any technology at any time( Time to market is short (leads to leadership in the market ( Any error found during the simulation phase is less e&pensive than by discovering the errors after making the circuit board ()nvestment is saved ( The great advantage is that the /ro9ect $anagers can modify the specification without leading to disaster (only the necessary portion of the code need to be changed ( )t can deliver designs 2::; error free at short duration( *ew Concepts in hardware design (for e&ample' in image processing' D#/' etc(' can be modeled in VHDL and its efficiency or viability can be proven without doing the hardware( A large number of A#)Cs fail to work when plugged into a system even if they meet their specifications first time( VHDL addresses this issue in two ways! A VHDL specification can be e&ecuted in order to achieve a high level of confidence in its correctness before commencing design' and may simulate one to two orders of magnitude faster than a gate level description( A VHDL specification for a part can form the basis for a simulation model to verify the operation of the part in the wider system conte&t (eg( printed circuit board simulation ( This depends on how accurately the specification handles aspects such as timing and initiali6ation(

Designing Hard$are using VHDL

VHDL files are created by using the built1in te&t editor( The editor contains special support for the VHDL synta&( A design is described in VHDL using the concept of a design entity( A design entity is split into two parts!

entity declaration represents the e&ternal interface to the design entity( architecture body represents the internal description of the design entity 1 its behavior' its structure' or a mi&ture of both(

An e&ample will be the best way to describe each! Lets consider an A+) gate shown below as a single chip package with four input pins and one output pin ()gnore power and ground pins in modeling (

The design entity for the above A+) gate is given below
-- VHDL code for AOI gate library IEEE; use IEEE.STD_LOGI _!!"#.all; e$tity AOI is %ort & A' (' ' D) i$ STD_LOGI ; * ) out STD_LOGI +; e$d AOI; arc,itecture be,a-ior of AOI is begi$ . /0 $ot &&A a$d (+ or & a$d D++; e$d be,a-ior;

Explanation# The above design entity for the A+) gate is e&planed as follows!
-- VHDL code for AOI gate -- Si1ilar to 1a$y %rogra11i$g la$guages' VHDL su%%orts co11e$ts -- T,e 2ords3li$es after 4--4 are co11e$ts library IEEE; -- Library clause &library IEEE;+ use IEEE.STD_LOGI _!!"#.all; -- 5se clause &library IEEE;+ -- T,e 5se clause gi-es t,e e$tity AOI access -- to all t,e $a1es declared 2it,i$ %ac6age STD_LOGI _!!"# -- i$ t,e library IEEE' a$d to data ty%e STD_LOGI e$tity AOI is -- Defi$es t,e begi$$i$g of a $e2 VHDL desig$ %ort & -- Defi$es t,e %i$s of our AOI c,i% A' (' ' D) i$ STD_LOGI ; -- I$%ut declaratio$ . ) out STD_LOGI -- Out%ut declaratio$ +; e$d AOI; -- ter1i$atio$ of e$tity declaratio$ arc,itecture be,a-ior of AOI is -- Arc,itecture (egi$$i$g -- I$ t,e abo-e state1e$t -- arc,itecture' of a$d is are VHDL 6ey2ords. begi$ -- start of t,e arc,itecture state1e$t . /0 $ot &&A a$d (+ or & a$d D++; -- co$curre$t sig$al -- assig$1e$t e$d be,a-ior; -- ter1i$atio$ of arc,itecture

The entity and is are VHDL keywords( The name A+) of the design entity is 9ust an arbitrary label invented by the user( A port may correspond to a pin on an )C( "ach port declaration includes the name of one or more ports ( e(g(' A' % ' the direction that information is allowed to flow through the ports (in' out or inout ' and the data type of the ports (i(e(' #TD<L+0)C ( The data type of a port defines the set of values that may flow through the port( .or the above design' the ports are of type #TD<L+0)C' which is found in package #TD<L+0)C<22=> in library )"""( A package is a VHDL language construct where new data types may be defined' and the particular package #TD<L+0)C<22=> is an )""" standard for representing digital signals in VHDL( Adding the name of the design entity after the end keyword is not compulsory(

The name of the architecture body (behavior is 9ust an arbitrary label that we have used( )t is possible to define several alternative architecture bodies for a single design entity' and the only purpose of the architecture name is to distinguish between these alternatives( All the names used in the architecture statement part are declared in the entity declaration' and so the architecture declarative part is empty( The concurrent signal assignment' which describes the function of the design entity( The concurrent assignment e&ecutes whenever one of the four ports A' %' C or port D change value(

Lets write the VHDL code for this circuit step by step! Lets add some comments in the beginning(
-- VHDL code for t,e abo-e circuit

?rite the library clause and use clause( These are almost the same in all simple level designs like the ones we will be discussing(
library IEEE; use IEEE.STD_LOGI _!!"#.all;

Declare "ntity with an arbitrary name' say AOI2( Add the ports for

)nput A' %' C and D +utput @

and donAt forget to end "ntity(

e$tity AOI7 is %ort &A' (' ' D) i$ STD_LOGI ; . ) out STD_LOGI +; e$d AOI7;

%egin the architecture of the design with the statement

arc,itecture be,a- of AOI7 is

#ince the architecture contains three internal signals A%' CD and "' declare them here(
sig$al A(' D' O) STD_LOGI ;

A signal is always declared before the begin' of an architecture' and has its own data type (eg( #TD<L+0)C ( Technically' ports are signals' so signals and ports are read and assigned in the same way(

%egin the architecture with the begin statement(

begi$

Add the concurrent signal assignments needed to generate internal signals( concurrent signal assignments e&ecute whenever a signal on the right hand side of the assignment changes value( Therefore' the order in which concurrent assignments are written has no effect on their e&ecution(
A( /0 A a$d ( after 7 8S; D /0 a$d D after 7 8S; O /0 A( or D after 7 8S; * /0 $ot O after ! 8S; e$d be,a-;