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30416
30416
30416
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Spring 2010
EE 201L
2.
Course administration: a) Course prerequisites: EE101 'Introduction to Digital Logic'. Students are expected to know ALL the material covered in EE101, particularly combinational logic and sequential logic design. b) Course web page: BlackBoard (https://blackboard.usc.edu/) c) Classes and labs: Please refer to the course web page for class timings, classrooms, and lab timings. Labs are held in OHE336. Quiz slot: The quiz slot is created to hold common midterm exams. We meet only three times during the whole semester during the quiz slot for writing the three midterm exams. d) Final Exam: There is no final exam. The Final project serves as final exam. The Final Project report is due on the first day of the final exams.
e) Grading policy:
Weights: Homeworks Quiz Midterm Exam I Midterm Exam II Laboratory TAs points Final Project
Friday 02/26/2010 4-6:00PM (QUIZ slot) Friday 03/26/2010 4-6:20PM (QUIZ slot) Friday 04/30/2010 4-6:20PM (the last QUIZ slot) Lab attendance is mandatory. TAs discretionary points Project demonstrations shall be in the final week
classes along with a draft of the report showing all design details. Final report is due on the first day of final exams (Wed. 5/5/2010). f) Miscellaneous administrative matters: Major portion (75% or more) of the exams is OPEN-BOOK type. In the open-book portion of the exams, students are allowed to use Any printed or hand-written (but not electronic) material such as CLASSNOTES (EE101 and EE201L), TEXTBOOK, Lab manual, HDL Quick reference guide, ICs data book, homework assignments/solutions, etc. In this course, we want to test your ability to design (and not your ability to memorize). However, you are NOT allowed to use a computer or any electronic devices to search answers for the questions! Students should NOT borrow any item from other students as it helps COPYING. Academic dishonesty cases will be dealt with severely. Using another student's work (wired circuit board, HDL code, or simulation results, in the lab or copying another student's logic simulation/FPGA implementation work or homework will earn an F grade in the course to both the students involved. However students are encouraged to discuss among themselves and share their views on homeworks/labs/project. Discussing is different from copying! Please be aware that we will be using tools such as MOSS from Berkeley/Stanford to catch cheaters. MOSS stands for "Measure of Software Similarity". It is a program for detecting software plagiarism. http://moss.stanford.edu/ So, do not even think of copying. USC VSoE takes academic integrity very seriously and reports cases of cheating to the SJACS (Student Judicial Affairs and Community Standards) committee. http://www.usc.edu/student-affairs/SJACS/communitystds.html No makeup exams, sorry. Incomplete grade can only be assigned, if there is a verifiable cause, which is acceptable to the department and the university. g) Instructor and graders office hours: Please refer to the course web site or a separate announcement for this information. h) Academic Accommodations: Any student requiring academic accommodations based on a disability is required to register with Disability Services and Programs (DSP) each semester. A letter of verification for approved accommodations can be obtained from DSP. Please be sure the letter is delivered to me as early in the semester as possible. DSP is located in STU 301. Their phone number is (213) 740-0776. Please visit http://www.usc.edu/student-affairs/asn/dsp/index.htm 3. Laboratory Schedule: Please refer to the lab manual for the list of lab assignments and rules pertaining to the lab. Occasionally, some labs may be revised during the semester. Then the lab assignment may be provided to you via BlackBoard. Lab work is an important part of the course. Making a reasonable attempt at ALL lab assignments is a requirement of this course. Lab attendance is mandatory. The TAs are asked to record your attendance. You may not miss more than one lab session. You need to
make up for any missed lab session/lab experiment. You may at most have one incomplete/missed lab experiment/assignment. Poor performance in the lab may result in a failing grade. 4. Readings: The required readings are mainly from classnotes. You may like to refer to relevant sections of the textbook (Wakerly). Books: * "Digital Design Principles and Practices" by J.F. Wakerly 4th ed * Verilog Quick Reference Guide (Esperan/Cadence) * Digital IC Data Handbook (Manufacturer Motorola/Signatics/TI) Printed copies are not available. We will use datasheets on web. * Lab Manual: <= Please purchase from the book store. * Class Notes: <= Please purchase from the book store. 5. Labs (Following is the list of labs during Spring/Fall 2008. The course and the labs are being revised progressively during 2008/2009 to include Verilog HDL-based labs and labs associated with the newly added material (particularly SSRAMs, FIFOs, and CAMs). There will be some take home labs.
6. Course schedule: The course is under revision. It recently changed from a 3-unit one lecture per week course to a 4-unit two lectures per week course. The following is just the list of topics we intend to cover in the revised course. Week-by-week plan is not yet made. 6.1 A preliminary list of Verilog topics is:
Net and Register Data Types Operators Initial and Always Blocks Assign Statement Sequential Statements Blocking and Non-Blocking procedural assignments Tasks (Procedures) and Functions System Tasks and Functions Synthesis Issues Tristate and Latch Inference File I/O Test Benches
6.2
Course Introduction, EE101 review, Homework #1 Logic families & their characteristics Schmitt trigger input devices, Totem-pole outputs, Open-collector outputs, and three-state outputs, Homework #2 Three State Buffers State Machine Design and Implementation One-Hot method of designing state machines Exercises on one-hot method of design, Homework #5 Design of a Micro-programmed control unit Exercises on uProg. CU design, Homework #6
Datapath Design and Data Registers Glitches in combinational logic, common misconceptions in exercising control over data registers, counters, etc. Homework #7 and # 8 System Design Based on a word statement, arrive at a datapath and a control unit to perform the task. Realize that one can think of a number of designs to perform the same task, understand the difference between an informal flow chart and a formal state diagram, understand what changes will perhaps decrease the number of clocks taken without increasing the clock width and what changes imply reducing the number of clocks at the cost of widening the clock. Timing Analysis Propagation delays in combinational logic, longest path and shortest path, maximum and minimum delays Setup time margin and hold time margin Homework #9 Timing analysis and Counters Arithmetic Components Carry look-ahead adders, fast incrementers and decrementers, fast multipliers.