GiantMeterwave RadioTelescope

National Center for Radio Astrophysics

Tata Institute of Fundamental Research
NCRATTF'R
Interfacebetween
aPCparallelportandGPIBdevices
Author: L. Pommier
Projectdirector: T.L.VeHkanmuBHUllmll
Date: 06102104
Table of Contents
1.Introduction ...................................................................................................................................2-
2.TheGPminterface....................................................................................................................... .
2.1.GPIBmessages....................................................................................................................................................2
2.2.GPIBdevices.......................................................................................................................................................2
2.3.6PIBSignals........................................................................................................................................................2
2.3.1.Datalines....................................................................................................................................................Z
2.3.2.Managementlines......................................................................................................................................Z
2.3.3.Handshakelines.......................... ...............................................................................................................Z
2.4.Thehandshaldngprotocol....................................................................................................................................
3.Theparallelportinterface............................................................................................................,2
3.1.Theinterfacemodes ............................................................................................................................................2-
3.2.Theparallelportsignals......................................................................................................................................2
3.2.1.TheDataRegister .................................................................................................................................... 10
3.2.2. TheStatusRegister .................................................................................................................................. 10
3.2.3.TheControlRegister ................................................................................................................................11
3.3.Accessingtheparallelport ................................................................................................................................12
3.3.1. Programmingways .................................. ................................................................................................ 12
3.3.2.Linuxdirectaccessandresults...............................................................................................................12
4.Theexistingparallelport-to-GPminterlace.......... . ..........................................................13
4.1.Theparallelport-to-GPIBdriver...................... .......................................................13
4.2.Cableconnectionbetweenthetwo' ................................................11
4.3.Electricalspecifications................................ ..................................................15
4.3.1. Parallelportelectrical .....................................................15
4.3.2.GPIBelectricalspecifications........... ........................................16
4.4.Electricalcompatibilitybetweenthetwo ................................17
4.4.1. Outputtypes.............................................. ..................................................17
4.4.1.1.Open-collectorandopen-drain .......... ~ .................... 17
4.4.1.2.Totem-poleandpush-pull ............; ..................................................................................................17
4.4.I.3.Tri-state............................................................................................................................................ j!
4.4.1.4.Conc1usion.......................................................................................................................................ll
4.4.2.Conclusicnonelectricalcompatibilitybetweenthetwointeifaces .....................................................19
5.Furtherinterlacingsolution:theadapterbox............................................................................ 20
5.I.Introduction............................................................................................~ ...........................................................20
5.2.AdapterboxDesign ...........................................................................................................................................21
5.2.1.Adapterboxwithoutdirectioncontrol ...................................................................................................21
5.2.1.1.Presentation......................................................................................................................................21
5.2.1.2.ResistancesnotcompatiblewithGPIBcurrents...........................................................................21
5.2.2.Adap(erboxwitha3-statecontroL...... .................................................................................................23
5.2.2.1.Presentation......................................................................................................................................23
5.2.2.2.Finaladapterboxdesign.................................................................................................................24
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6.Multi-devicestestingandfurtherproceedings..........................................................................25
6.1.Multi-devicestesting.........................................................................................................................................25
6.2.Furtherproceedings..........................................................................................................................................25
7.Conclusion............................................................................: ....................: ................................26
8.References...................................................................................................................................27
9.Appendix................................................................................................................ ....................28
Illustration Index
Illustration I :GPmdevices...........................................................................................................................................6
Illustration2:GPmhandshaking..................................................................................................................................8
Illustration3:Parallelport GPmhybridcableandconnectors.............................................................................13
Illustration4:IEEE488buscurrentaccordingtobusvoltage.................................................................................16
Fig.5:open-collectoroutput ........................................................................................................................................17
Fig.6:bidirectionallinewithopen-collectoroutputs ................................................................................................17
Fig.7:Totem-poleoutput ............................................................................................................................................17
Fig.8:Tri-stateoUtpul.................................................................................................................................................18
Illustration9 :Linear-chainedconfiguration...............................................................................................................20
TIlustration 10:Star-chainedconfiguration .................................................................................................................20
Illustration. 11 :Adapterboxtransceiverwithoutdirectioncontrolforbidirectionallines....................................21
Illustration. 12:Adapterboxtransceiverwitha3-statecontrolforbidirectionallines ...........................................23
Illustration 13:Adapterboxdesign.............................................................................................................................24
Illustration14 ;Testsetting ..........................................................................................................................................25
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ParallelportI GPIB interface 3128
Index of Tables
Table I :ParallelportbitsoftheDataRegister ..........................................................................................................1 0
Table2:ParallelportbitsoftheStatusRegister ....................................................................................................; ...1 0
Table3:ParallelportbitsoftheControlRegister.....................................................................................................11
Table4:Read/WritepossibilitiesfromPCtoitsparallelport ................................................................................12
Table5:Connectionsofthehybridcable..................................................................................................................14
Table6:IEEE 1284voltagespecifications.................................................................................................................15
Table7:IEEE488voltagespecifications ...................................................................................................................16
Table8:GPmlinesdirection......................................................................................................................................23
Index

1":'1}. "., ,11'
""-'............."'."*t"...
..-.. .. , .".. ..'--.., ' ,
'")' , _ , '
.... ..... '" ..... .. _"" """, ""''''_ __
" "" ..
' 'j,,'
_'- _,4 .....1,:.-_
ECP ExtendedCapabilityPort
EPP EnhancedParallelPort
DAQ DataAcquisition
DMA DirectMemory Access
GMRT GiantMeterwaveRadioTelescope
GPm GeneralPurposeInterfaceBus
Ipr Localprinterport
OS OperatingSystem
SPP StandardParallelPort
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Parallelport1GPminterface 4/28
I
1.lntroduction
The Giant Meter wave Radio Telescope (GMRT) is a radio telescope lO::ated in Khodad, at 80 km from Pune. It
is composed of an array of 30 antennas spread over distances up to 25 km. Each antenna is 45 m in diameter,
and has been designed to operate at a range of frequencies from 50 to 1500 MHz.
For all its experiments and internal divisions, the GMRT requires different data acquisition systems. This
document deals with one of these systems: the parallel port-to-GPm driver.
The General Purpose Interface Bus (GPm) is an interface system through which interconnected electronic
devices communicate. It is a digital, 8-bit parallel communication interface which usually allows a PC to be
connected with programmable instruments. to control them and to acquire their data. Because of its robustness
and its versatility to many devices, the GPm was accepted as the industry standard IEEE 488.
The parallel port.to-Gpm driver connects a GPm instrument to the PC parallel port. It has been developed by
S. Joardar in GMRT to make the parallel port reproduce the GPm protocol and some of its most important
functions.
Since the 2 interfaces have different electrical specifications and since it can be useful to control many GPm
devices with this driver, the question of electrical compatibility between the 2 sides was raised.
This document first gives a overview of the GPm and the Parallel Port interfaces. Then a second part presents
the software and hardware features of the existing parallel port-to-GPm driver, and analyzes the electrical
compatibility between the 2 interfaces. A last part finally designs an adapter box that can be included just after
the PC to improve the electrical transmission.
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2.TheGPIBinterface
2.1.GPIB messages
The GPIB carries device-dependant messages and interface messages.
Device-dependant messages, often called data or data messages, contain device-specific information
such as programming instructions, measurements results, machine status, and data files.
Interface messages manage the bus itself. They are usually called commands or commands messages.
Interface messages perfonn such tasks as initializing the bus, addressing and unaddressing devices, and
setting device modes for remote or local programming.
The tenn command as used here shouldn't be confused with some device instructions, which can also be called
commands. Such device-specific instructions are actually data messages.
2.2.GPIB devices
Controller
. Device#l
Control, talk,
listen
... ..
.
...
Talk, listen
,
I
, I
,
,
Device #n
Talk, listen
Illustration 1 : GPIB devices
GPIB devices can be talkers, listeners or controllers.
A talker sends data messages to one or more listeners. The controller manages the flow of information on the
GPIB by sending commands to all devices (like a switching center of a city telephone system). A controller is
necessary when the active or addressed talker or listener must be changed. The controller function is usually
handled by a computer.
The bus supports one system controller, usually a computer (GPIB board), and up to 14 additional instruments.
Devices are connected with a cable assembly consisting of a shielded 24-conductor cable with both a plug and
receptacle connector at each end. With this design, you can link devices in a linear configuration, a star
configuration, or a combination of the two. All devices and boards connected to the GPIB are assigned a unique
GPIB address.
2.3.GPIB Signals
The interface system consists of 16 signal lines and 8 ground return or shield drain lines. The 16 signal lines are
divided into the following three groups.
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2.3.1.Data lines
Thelines010Ithrough0108areusedtotransferaddresses,controlinfonnationanddata.Thefonnatsfor
addressesandcontrolbytesaredefinedbytheIEEE488standard.Datafonnatsare undefinedandmaybe
ASCII(withorwithoutparity)orbinary.0101istheLeastSignificant.Bit(notethatthiswillcorrespondtobit
oon mostcomputers).
2.3.2.Management lines
The5interfacemanagementlines(ATN,EOI,IFC,REN, SRQ)managetheflow ofcontrolanddatabytes
acrosstheinterface.
TheA TN(Attention)signalisassertedbytheControllertoindicatethatitisplacinganaddressorcontrol
byteonthedatabus.A TNisreleasedtoallowtheassignedTalkertoplacestatusordataonthedatabus.
TheControllerregainscontrolbyreassertingA TN;thisisnonnallydonesynchronouslywiththehandshake
toavoidconfusionbetweencontrolanddatabytes.
TheEOI(EndorIdentify)signalhastwouses.ATalkermay assertEOIsimultaneouslywiththelastbyteof
datatoindicateend-of-data.TheControllermayassertEOIalongwithATNtoinitiateaparallelpoll.
Althoughmanydevicesdonotuseparallelpoll,alldevicesshoulduseEOItoendtransfers(manycurrently
availableonesdonot).
TheIFC(InterfaceClear)signalisassertedonlybytheSystemControllerinordertoinitializealldevice
interfacestoaknownstate.AfterreleasingIFC,theSystemControlleristheActiveController.
TheREN(RemoteEnable)signalisassertedonlybytheSystemController.Itsassertiondoesnotplace
devicesintoremotecontrolmode;RENonlyenablesadevicetogointoremotemodewhenaddressedto
listen.Wheninremotemode,adeviceshouldignoreitslocalfrontpanelcontrols.
TheSRQ(ServiceRequest)lineislikeaninterrupt:itmaybeassertedbyanydevicetorequestthe
Controllertotakesomeaction.TheControllermustdeterminewhichdeviceisassertingSRQbyconducting
aserialpoll.TherequestingdevicereleasesSRQwhenitispolled.
2.3.3.Handshake lines
The3handshakelines(NRFD, NDAC,DAV)controlthetransferofmessagebytesamongthedevicesandfonn
themethodforacknowledgingthetransferofdata.Thishandshakingprocessguaranteesthatthebytesonthe
datalinesaresentandreceivedwithoutanytransmissionerrorsandisoneoftheuniquefeaturesoftheIEEE-
488bus.
TheNRFD(NotReadyforData)handshakelineisassertedbyaListenertoindicateitisnotyetreadyfor
thenextdataorcontrolbyte.NotethattheControllerwillnotseeNRFDreleased(i.e.readyfordata) until
alldeviceshavereleasedit.
o TheNDAC(NotDataAccepted)handshakelineis assertedbyaListenerto indicateithasnotyetaccepted
thedataorcontrolbyteonthedatalines.NotethattheControllerwillnotseeNDACreleased(i.e.data
accepted)untilalldeviceshavereleasedit.
o TheDAV(DataValid)handshakelineisassertedbytheTalkertoindicatethatadataorcontrolbytehas
beenplacedonthedatalinesandhas hadtheminimumspecifiedstabilizingtime.Thebytecannowbe
safelyacceptedbythedevices.
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2.4. The handshaking protocol
The handshaking process is outlined as follows. When the Controller or a Talker wishes to transmit data on the
bus, it sets the DAV line high (data not valid), and checks to see that the NRFD and NDAC lines are both low,
and then it puts the data on the data lines.
When all the devices that can receive the data are ready, each releases its NRFD (not ready for data) line. When
the last receiver releases NRFD, and it goes high, the Controller or Talker takes DAV low indicating that valid
data is now on the bus.
In response each receiver takes NRFD low again to indicate it is busy and releases NDAC (not data accepted)
when it has received the data. When the last receiver has accepted the data, NDAC will go high and the
Controller or Talker can set DAV high again to transmit the next byte of data.
Note that if after setting the DAV line high, the Controller or Talker senses that both NRFD and NDAC are
high, an error will occur. Also if any device fails to perfonn its part of the handshake and releases either NDAC
or NRFD. data cannot be transmitted over the bus. Eventually a time-out error will be generated.
The speed of the data transfer is controlled by the response of the slowest device on the bus. for this reason it is
difficult to estimate data transfer rates on the IEEE-488 bus as they are always device dependent.
ATN'"
DI0"1-8
(Compteite)
DA>or
Fi 1St byte transferred
NRFO'"
-WI /
NOAC"
JL I ~ , 1...._-J.I.LUIII
Some All Some All
ready ady accepted amepted
Illustration 2 : GPlB handshaking
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3.The parallel portinterface
3.1. The interface modes
As the design of the PC evolved, several manufacturers introduced improved versions of the parallel port. The
new port types are compatible with the original design, but add new abilities, mainly for increased speed.
);> Standard Parallel Port (SPP):
The SPP mode is the original mM PC parallel port. It was based on an existing Centronics printer interface.
SPPs can transfer 8 bits at once to a peripheral, using a protocol similar to that used by the original Centronics
interface (Compatibility mode). The SPP doesn't have a byte-wide input port, but for peripheral-ta-PC transfers,
SPPs can use a Nibble mode that transfers 4 bits at a time using the status inputs.
);> PS/2-type:
An early improvement to the parallel port was the bidirectional data port introduced on mM's model PS/2. The
bidirectional port enables a peripheral to transfer 8 bits at once to a PC. Byte mode is a 8-bit data transfer
protocol that PS/2-type ports can use to transfer data from peripheral to PC.
);> Enhanced Parallel Port (EPP):
An EPP can read or write a byte on the data port in one cycle of the lAS expansion bus (about 1 microsecond),
compared to 4 cycles for previous types. It can also switch directions quickly. So the EPP mode allows high-
speed transfer of bytes in either direction. Handshaking signals of this mode can distinguish between data and
address transfer.
);> Extended Capabilities Port (ECP):
ECPs propose the same performances than EPPs. ECPs also have support for DMA (Direct Memory Access)
transfers. A control byte can contain an address or a data-compressed information. A FIFO buffer stores bytes to
send and bytes received.
3.2. The parallel pon signals
The parallel port signals are arranged into 3 registers of 8 bits. Those registers are in a special memory area
dedicated to accessing input and output (I/O) devices.
The D-sub usual connector has 25 contacts, including 8 grounds and 17 transmitted signals. The next parts
detail the registers bits, including the ones that don't appear at the connector.
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3.2.1.The Data Register
The data register is located at the parallel port base address.
0 2 Data bit 0 no
I 3 Data bit I no
2 4 Data bit 2 no
3 5 Data bit 3 no
4 6 Data bit 4 no
5 7 Data bit 5 no
6 8 Data bit 6 no
7 9 Data bit 7 no
Table 1 : Parallel port bits of the Data Register
The data port, or data register, holds the byte written to the data output. In bidirectional data ports, when the port
is configured as input, the data register holds the byte read at the connector's data pins.
3.2.2.The Status Register
The status register is located at the parallel port base address + 1.
I : _'" ,
I ",,1. '"' c'!If .. j t.;!
c
t1 f
,I

I "...
May be timeout 0 - -
unused 1
- -
unused 2 - -
nError no 15 3
Select 13 no 4
PaperEnd 12 no 5
nAck 10 no 6
Busy yes 7 11
Table 2 : Parallel port bits of the Status Register
The status port, or status register, holds the logic states of five inputs, S3 through S7. Bits SO-S2 don't appear at
the connector. The status register is read only, except for SO, which is a timeout flag on ports that support EPP
transfers, and can be cleared by software. On many ports, the status bits have pull-up resistors.
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I
3.2.3.The Control Register
ThedataRegisterislocatedattheparallelportbaseaddress+ 2.

I
I

,.. , "" -
'7',',,' """''''.
"", J;J, ,. i I " /. :J
, "',, , " ' ,,' '" 'i!f,JJ!'lj.lf1P:t'

0 1 nStrobe yes
,
1 14 nAutoLF yes
2 16 nlnit no
3 17 nSelectIn yes
4
-
Interruptenable
-
5
-
Directioncontrolfor
bidirectionaldataports
-
6 -
unused
-
7
-
unused
-
Table 3:Parallel port bits o/the Control Register
Thecontrolport,orcontrolregister,holdsthestatesof4bits,COtoC3.
Conventionally,thesebitsare usedasoutputs.OnmostSPPs,however,thecontrolbitsareopen-collectoror
open-draintype,thatmeanstheycanalsofunctionasinputs(cf.Paragraph4.4.1).However,onmostportsthat
supportEPPandECPmodes,to improveswitchingspeed,thecontroloutputarepush-pulltypeandcan'tbe
usedasinputs.On somemulti-modeports,thecontrolbitshavepush-pulloutputsintheadvancedmodes,and
forcompatibilitytheyswitchtoopen-collector/open-drainoutputswhenemulatingaSPP.
BitsC4toC7don'tappearattheconnector.In bidirectionalports,theC5setsthedirectionofthedataport.Itis
setto0foroutput(dataoutputsenabled). 1forinput(dataoutputsdisabled).Usuallyyoumustfirstconfigure
theportforbidirectionaluse(system'sCMOSsetupscreen,accessedonboot-up), inorderforthisbittohavean
effect.ItisunusedinSPPs.
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3.3.Accessing the parallel port
Aportonasystemmotherboardhasconfigurationoptions(baseaddressandmode)inthesystemsetupscreen
(theCMOSsetup)accessibleonboot-up.Usuallytheparallelportbaseaddressislocatedat3BCh,378h,or
278h.Nowdifferentoptionsallowtoaccesstheparallelport.
3.3.1.Programming ways
TheusualwaytoaccesstheparallelportistousetheDEBUGprogramunderaDOSprompt:
- D40:00displaystheBIOSdataareacontainingtheaddressesoftheserialandparallelports
- A 100allowstoenterinstructionsinthecodesegmentatoffsetl00H,thenwrite:
TowriteOxOO totheport: Toreadtheport:
movdx,378H ;enterstheportaddress movdx,378H ;enterstheportaddress
moval,OOH ;entersthevaluetowrite inal,dx ;readthevalueattheport
outal,dx ;writethevalueattheport adressandstoresitinalregister
adress jmp100 ;resetsInstructionPointerto
jmp100 ;resetsInstructionPointerto 100H
100H
- Rcommanddisplaystheregistersandflagscontents
- Texecutesinstructionsonebyone
- U 100,107displaysthewritteninstructions
ThisDEBUGprogramworksunderWindowsOSuptoWin95.Forhigherversions,itgivesincoherentresults.
Anotherwayisto writeaprograminC,ASM,VisualBasics... withspecificfunctionstalkingtoPCports,and
torunthisprogramunderanyOS.
3.3.2.Linux direct access and results
Finally withaLinuxOS,onecandirectlyaccessYOportsundertheadministratoraccountusingtheinb<port>
andoutb<port><value>functionsinaterminal(ioport). Examples:
- inbOx37a readsbyteattheportaddressedat37aH
- outbOx37aOxOO writesOOH bytetotheportaddressedatOx37a
OntheWinclnt4PCoftheGMRT,theparallelportbaseaddressis378H(CMOSsetuporcat/prodioport).
Usingthelastmethod,experimentswithamultimeteranda+5VDCsourcegivethefollowingresults:
WriteonlywithC5=O
ReadonlywithC5=1
WriteonlywithC5=O
ReadonlywithC5=1
Readonly Write
Read
Table4:Read/ WritepossibilitiesfromPCtoitsparallelport
WritingC5=1 automaticallyputsOxFFonthedatapins.Thisconditionisrequiredwhentheparallelportopen-
collectoroutputsarenotswitchedoffforbi-directionaltransmission(cf.Paragraph5.2.1 ), andthenthistask
hasnottobe donebyanysoftwarecommand.
Whenthecontrolpinsareusedasinputs,theycomebacktotheirlastoutputvaluewhentheincomingsignal
ends.HighandLowTTLvaluescanbe readwhateverthelastoutputwas.
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4. Theexistingparallel port-to-GPIBinterface
ThischapterflIStintroducesthesoftwarepartoftheparallelport-to-GPIBinterfaceanddetailsthehybridcable
connectionsbetweenthePCandthedevices.ThesetwopointshavebeendevelopedbyShubenduJoardar.The
lowestlevelisthentoanalyzetheelectricalcompatibilitybetweentheparallelportandtheGPmport.
4.1. The parallel port-to-GPIB driver
TheparallelportdriverallowstocontrolonedevicethankstoanAssemblylanguagecode(gpib.asm)running
underLinux,Windows16orWindows32.ItreproducestheGPmprotocolandthustransmitandreceivedata
withanyGPmdevice.Thecoderesumesthefollowingbasicfunctions:
'" initializ.e. '" ioread,
'" GPIB_send, '" GPIB_SerPoll,
'" iowrite. '" GPIB_PutAdd,
'" GPIB _stat, '" GPIB_GetData.
'" GPIB_Get,
Thosefunctionsarefurtherusedinanapplicationcode(testprogram.c)inC language.Thefollowinglines
explainhowtoexecutethe2programs:
nasm1elf-0gpib.ogpib.asm:compileassemblydriverprogram
gcc-Wall-c-0testprogram.otestprogram.c:compileCapplicationprogram
gcegpib.otestprogram.o:linkthetwoobjectfiles
.Ia.out:underanaccountwhichhasnecessarypennissiontoaccessanyPCportunderLinux,forthe
finalexecution.
4.2.Cable connection between the two interfaces
TheDB-25parallelportconnectorandtheGPmconnectoraredifferent,soanhybridcablehadbeenmadeto
interfacebothsides.
Parallelport- GPmcable C]J
~ ~
[[)
14
15
16
17
18
19
20
21
22
23
24
2S
0
g
Parallelport
1
DB2S
13
2
3
cablemaleconnector
14
16
11
4 "
:5
18
i 6 19
17 :ID
21
8
22
9
23
GPm 24
10
II cablemaleconnector
12
13
,
4
6
1
8
9
10
II
12
Illustration3:Parallelport- GPIBhybridcableandconnectors
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Datastrobe
Databit1to 4
Databit5to8
Acknowledge
Busy
Paperend
Select
AutoLineFeed
Error
Initializeprinter
Selectinput
Ground
Ground
Ii:! Notes:
1
2to5
6t09
10
11
12
13
14
15
16
17
18
19to25
...
.... ...
.....
...
Notconnected
...
...
...
....
.....
...
6
1to4
13to16
9
17
5
11
10
7
8
12
18 to24
DAtaValid
Data110 1to4
Data1105to8
InterFaceClear
RemoteENable
EndOr Identify
ATtentioN
ServiceReQuest
NotReadyForData
NoDataACcepted
Shield
Ground
Table 5:Connections a/the hybrid cable
,.. Theparallelporthas25 pins,andtheGPIBconnectorhas24pins,sotheparallelportpinnumber11 isnot
connectedinthehybridcable.
,.. GroundlinesarenottwistedwithsignallineslikeinGPIDcable.If someinterferencesbetweensignals
appear,thelengthofthecablemustbereduced..
,.. Theparallelportconnectorcanhaveamaximumof12outputs(8ondataportand4oncontrolportinSPP
mode),sosomelinedirectionsoftheGPIBinterfacecannotbeprovidedwiththishybridsystem:
Bidirectionaltransmissionis necessaryfordata(dataport)andhandshakinglines(controlport).
EOI,IFCandRENarenotallowedinthePC-ta-peripheraldirection.SotheIFCandRENfunctionsare
notprovidedbythisdri....er,andtheEOIisusedonlywhenreadingfromtheperipheraldevice.
,.. REN,SRQandIFCareunidirectionallines.
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4.3.E/ectrica/ specifications
OnparallelportsandGPIBcontrollers.driversandreceiversareusedtomaketheelectricaltransitionbetween
theterminalcard(lowcurrentforICs) andthebus(highcurrentforlinetransmission).
iii Vocabularynote:
adriverisacomponentwhichcanincreaseelectricaloutputsfeatures(nottobeconfusedwiththe
softwarethatimplementsfunctionsofaport).
abufferisacomponentthatwilladaptitsoutputstothefollowingcircuit.
areceiverisabufferforaportinput(nottobeconfusedwithtalkerIreceiveroftheGPIBprotocol).
atransmitterisadriverforaportoutputs.
atransceiverisbothareceiverandatransmittercombined.
4.3.1.Parallel port electrical specifications
TheIEEE 1284standardspecifieselectricalcharacteristicsforparallel-portdriversandreceivers. Itdescribes2
typesofdevices:Levelldevicesaresimilartothedesignoftheoriginalport.whileLevel2devicesgivebetter
performanceswhileremainingcompatiblewiththeoriginalinterface.Many newerportcontrollersmeetthe
Level2specifications.
). Thevoltagespecificationsarethesameforthe2IEEE1 284levels:
Table6 : IEEE1284 voltagespecifications
). Currentspecifications:
iii Note:In usualdatasheetspecifications. anegativecurrentindicatesitgoesoutofthedevicepin. For
aTTLhighlevel, thecurrentgoesfromthetransmittertothereceiver(thetransmittersourceScurrent),
anditistheinverseforaTTL lowlevel(thetransmittersinkscurrent). Maximumorminimumthenonly
refertoabsolutevalues.
In IEEE1284level 1standard.transmittersoutputsmustbeabletosourceamaximumof-0.32mAt andtosink
amaximumof12mAo
InIEEE1 284level2standard.transmittersoutputsmustbeableto source/sinkamaximumof-/+ 12mAo
Receiversinputscansupportcurrentsupto+/.,.20mA (inputdiode).In TILhighlevel.they sinkamaximumof
afew J.IA (usually+20J.IA). In TILlowlevel.theysinkamaximumofafew uAfordatalines(usually-20J.IA),
andof-3to-5 mAforcontrolandstatuslines.
). Transmittersoutputstypes:
... Dataportconnectionsare8bidirectionalpins,withoutputsoriginallytotem-poletype (74LS374).
... Statusportpinsareinputsonly(LSTILlogicgates).
... Controlportconnectionsare4bidirectionalpins,withoutputsoriginallyopen-collectortype(7404
open-collectorinverterswith lAWpull-upresistances).
NowcomponentsforparallelportofnewPCscanvaryaccordingto thecontrollerused.Parallelportcontrollers
arenowadaysintegratedonPCmotherboardsandtheyarecomplianttothelevel2ofIEEE 1284standard.
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TheffiEE1284transceiversspecificallyusedforparallelport arethe74ACf1284,74VHC161284,
74LVX161284,and74LVXZ161284bidirectionalbuffers.
4.3.2.GPIB electrical specifications
TheffiEE488.1 standardspecifieselectricalcharacteristicsforGPmdriversandreceivers.
)j> Thevoltagespecificationsarethesameforthe2ffiEE1284levels:
Table 7: IEEE 488 voltage specifications
)j> Currentspecifications:
GPmtransmittersareabletosourceamaximumof-5.2rnA(TILhighlevel),andtosourceamaximumof48
rnA(TILlowlevel).
GPmreceiverssourceamaximumof-1.6rnA, andsinkamaximumof50J.LA.
TheffiEE488loadcurrentfortheGPmbusatthereceiversinputsisgivenbythefollowinggraphic:
4
2
1load(rnA)
o-l-_--r-
-2
-4
-6
Vinput(V)
busvoltage
- ffiEE488busloadingregion
Illustration 4 : IEEE 488 bus current according to bus voltage
)j> Transmittersoutputstypes:
fI' Dataportconnectionsare8bidirectionalpins,with3-stateoutputs.Thetransceiver(SN74160)
switchestheseoutputstoopen-collectoronesfortheparallelpollingcommand.
fI' SRQ,NDACandNRFDarebidirectionalpinswithopen-collectoroutputs(SN74162).
fI' ATN,DAV,EOI,IFCandRENarebidirectionalpinswith3-stateoutputs(SN74162).
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Parallelport1GPIBinterface 16/28
4.4.Electrical compatibility between the two interfaces
Toanalyzeinterfacescompatibility,itisfirstusefultounderstandthefunctionalofeachoutputtype.
4.4.1.0utput types
4.4.1.1.0pen-collector and open-drain
.Vee
Thepull-upresistorisexternal(typically4.7k.QwithVcc=+5V)
Theswitchingspeedisslow(resistortocharge)
ExternalRpul
OUT
Fig. 5:open-collector output
Theopen-collectorisaLSTILtechnology.InCMOS
components,theequivalentisopen-drainoutput.
Theoutputcanbeconnectedtootheropen-collectoroutputsfor IN
bidirectionallines.Withthefollowingconfiguration,onemust
firstwrite1totheoutputbeforereadingtheinput.
Vee
Aout
Open-collector
Open-collector
driver Rpull
driver
o
I---Bout o
1
Aout v-- A I
1
;:::---Bin
Ain-<J---J
Inputbuffer Inputbuffer
Bout
o
1
o
Ain,Bin
o
o
o
When1iswrittentoAout,Ainfollows
Fig. 6:bidirectional line with open-collector outputs
Bout.
4.4.1.2. Totem-poleandpush-pull
Theresistoristypically600withVcc=+5V
Vee
Theswitchingspeedishigh
Thisoutputcannotbedirectlyconnectedtootheroutputs.IfINis
HighandsomeLowsignalarriveonOUT,Vccisconnectedon
theothersidetotheGroundwithjustalowresistorbetweenthem.
Thentheresultisunpredictableandlargecurrentmaydestroy
involvedcomponents.Thisproblemissolvedwithaserialresistor
ontheline(typically330Q),buttheswitchingspeedwillbecome
low.
ItisaLSTfLtechnology.InCMOScomponents,asimilaroutput
isachieved,butwithequalcurrent-sinkingandcurrent-sourcing
abilities(push-pulltype).
Fig. 7:Totem-pole output
TIFR- NCRA- GMRT TechnicalReport
Parallelport1GPIDinterface 17/28
1
4.4.1.3. Tri-state
Theresistoristypically60QwithVcc=+sv.
Vee
Theswitchingspeedishigh.
Itrequiresanextrainput(DE)tocontroltheoutput
enablingI disabling.WhenDEisHigh,bothtransistors
areOFFandtheoutputhasnoeffectonexternalcircuit
(HighImpedancestate).
Suchcontrolonoutputallowsbidirectionallines(this
drivermustbedisabledwhentheterminationisusedas
aninput),withfasttransferrates.
Itistheusualconfigurationoncomputerbusesaccess.
Everylineterminationisdirectedsothatonlyone
outputisenableatatime.
Characteristicsofoutputsareverydifferentaccordingtotheirtype.
Thosefiguresareasimplificationoftransmitterscircuitsactuallyused.Withamorecomplicatedcircuit,open-
collectortransmitterscanalsobeenabledordisabledbya3-statecontrol.
Theoutputimpedancedefinestheswitchingspeed.Asanoutputswitches,thevoltagemustchargeordischarge
throughthecable'scapacitance,andthelowertheoutputimpedanceis,thefasterthevoltagecanchange.
Alowoutputimpedancepreventitfrombeingdirecdyconnectedtootheroutputsforabidirectional
configuration(cf.Totem-pulldescription).Aserialimpedanceora3-statecontrolmustthenbeconsidered.
Fig. 8 : Tri-state output
4.4.1.4.Conclusion
TIFR- NCRA- GMRT
TechnicalReport.
Parallelport/GPIBinterface 18/28
4.4.2.Conclusion on electrical compatibility between the two
interfaces
Bothinterfacesideshavetransceiversthatprotectinternalcircuits r o ~ thebushighcUrrents. Stilltwospecific
pointscanbecomeproblematicforinterfacingdirectlywiththehybridcablethe2interfaces:
theparallelportmaynotprovideenoughcurrenttocommunicatewithmanyGPIBdevices:GPIB
transmittersspecificationsallowcurrentsupto -5.2rnAand+48rnA whereasparallelporttransmittersallow
currentsupto+/-12rnAinlevel2standard.or-0.32rnAand 12rnA inlevel1standard.GPIB currentson
thebusareshowedinillustration4.
Solevel 1parallelportdriversarenotstrongerenoughtocommunicatewithGPIBdevices.
Level2parallelportdriversarelessstrongthanGPIBones,but GPIBsystemsaredesignedtosupportupto16
devices.Sowecanconcludethatactualparallelportscancommunicatewith-4devices(l2mA148rnA*16
devices).
Whentwooutputsaredirectlyconnectedandwhentheyarenotbothopen-collectortype.ahighcurrentcan
happen(cf.Paragraph4.3.3.1).
ThiscanbethecaseforDAVandATNlines.butonbothsides.portcontrollershaveonebittocontrolthe
directionoftheirbidirectionalpins.TheGPIB protocoldoesnotmakethecontrollerandthedevicetalkatthe
sametime, sooutputsonthesamelinearenotenabledatthesametimeandthisproblemdoesnothappenhere.
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ParallelportIGPIBinterface 19/28
GPIB
cable
GPIB
5.Furtherinterfacingsolution: theadapterbox
5.1.lntroduction
Asconcludedinthelatestpart,actualparallelportscancommunicatewithmanyOPIBdevicesthankstothe
assemblydriver.Nowifsomeuserwantstousethisdriverwithmoredevices.orwithanIEEE1284Levell
parallelportcontroller.itisnecessarytoaddnewtransmittersaftertheparallelporttomakeitoutputmore
current.
Sosomehardwaremustbeaddedbetweenthetwosides.ThiswillbeanadapterboxlocaledbetweenthePC
parallelportandtheflrstdevicealongthehybridcable.On thePCside,theadapterboot willtransmitaccording
totheparallelportspeciflcations.Onthedevicesside,theadapterboxwilltransmitaccordingtotheOPm
speciflcations.
OnlyonedevicemustbeconnectedtothePC,andfromthisdevicewhetheralinear-chainedorastar-chained
configurationcanbeformedthankstoOPIB cableswhichconnectorsarebothplugandreceptacle:
GPIBcable
GPIBcable
cable
Illustration 10: Star-chained configuration
Illustration 9:Linear-chained configuration
TIFR- NCRA- GMRT TechnicalReport
Parallelport/GPIBinterface 20/28
S.2.Adapter box Design
S.2.1.Adapter box without direction control
5.2.1.1.Presentation
ThefIrst ideaistousetransmitterswithoutdirectioncontrol,so thatoutputsarealwaysenabled.OnbothPC
anddevicesside,sometotem-poleoutputsonbidirectionallineswillthenfacetheadapterboxoutputs,sosome
serialresistanceisnecessarytoprotectthecomponentsagainsthighcurrent.
RI
To_llelport rToOPIBdevice
1-vVv-] -
R2
IUustration. 11 :Adapterboxtransceiverwithoutdirectioncontrolforbidirectionallines
5.2.1.2.Resistances not compatible with GPIB currents
Theresistancesarenecessaryto protectoutputsconnectedonthelineagainsthighcurrent.Atthesametime,
resistancesmustnotchangethevaluetransmittedbytheoutput.Thefollowingequationsresumesthose
conditionsontheGPmdeviceside("1"isTTLHighlevel,and"0"isTTLlowlevel).
Whenthedevicetalks.itoutputsonevaluethatwillfacetheadapterboxbufferwhichoutputvaluecanbe
differentforashortwhile,beforetheloopchangesit.
TX1hadset"1",TX2sets"0"
"1 "I "0"
Adapterbox GPmdevice
V
VaI- R.I=0withI< I
oH
.
nw
supportedbyTXl
(I) R> Of[
IOH.nm:
TXthadset"0",TX2sets"I"
"0" I "I"
Adapterbox GPmdevice
v
V(R - R.I=0withI < IOL.Jrw.x supportedbyTXl (2) R> Of[
IOL.rnax
WhenthePCtalks, thedevicetransmittersaredisabledbya3-statecontrolandreceiversareenabled.
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Parallelport1GPminterface 21/28
TXIsets"I",RX2mustreceive"I"
"I"
... [>
Adapterbox
RX2
GPffidevice
R< (VOH.min - VIH.min )
VOH.min -- R.l>VIH.min
(3)
IH
TXIsets"0",RX2mustreceive"0"
"0" I "0"
..
[>
Adapterbox
RX2
GPffidevice
~
R ,. TXl
R< (VOLfNlX - VILfNlX )
VOLmar + R.lL <VILfNlX
(4)
IL
WithnumericalvaluesofGPffibuffers:
Typicalvalues: VOH min=2.5 V loa max= 5.2rnA
V
OH
= 3.4 V Vmmin=2.0V] lot. max=48rnA
Li=2rnA VOL max= 0.5V
k=2rnA VII. max= 0.8V
Results:
(1) R >654Q (2)R>71n (3)R<250n (4)R<150n
Conclusion:
Withsuchvalues,resistancerequirementsarenotcompatible.Itispossibleto slightlyvarytheresultingvalues
byassumingthattypicalvalueswillbe different, butfInallythegoalistoachievehighercurrentsto
communicatewithmanyGPffidevices,andthenaserialresistanceprotectionwillchangetransmittedTfL
values.
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Parallelport1GPIBinterface 22/28
5.2.2.Adapter box with a 3-state control
S.Z.Z.l.Presentation
Agoodsolutionto designtheadapterboxistocontrolthedirectionof.eachlineinsidethebox.Thenext
analysisshowsthatonlyonebitisrequired,andthisbitcanbe controlledbyaddingafewlinesinsidethe
assemblydriver.
DI
3-statedriver
Toparallelport ToGPIBdevice
3-statedriver
Illustration. 12:Adapterboxtransceiverwitha3-statecontrolforbidirectionallines


,;- -':,

DAV
.... ....
DataIJO(8)
.... ....
IFC
.... ....
REN
.... ....
EOI
.... .....
ATN
.... ....

..... ....
.... ....
.... ....
Table8:GPIBlinesdirection
AccordingtotheGPffiprotocol,itispossible
toknoweverylinedirectionwhenafunctionis
called:
1. Acommandmessagecanhappenifthebus
needsnewmanagingtasks(newtalkerfor
nextdatamessage ...).Forthiscommand,
thetalkerisalwaysthecontroller(PC).
2. Adatamessageisthentransferedwiththe
lasttalkerdefined(PCoradevice).
Soaccordingtowhothetalkeris,010(8),
EOl,andDAVareinonedirection,andNRFD
andNDACareintheotherdirection.
ATN,IFC,REN,andSRQarealways
unidirectional,assumingthatthecontrolleris
alwaysthePC.
Tocontrolabitthatcansetthe3-statecomponentsdirection,twowayscanbeconsidered:
Thedirectionsignalcouldbe issuedfromacombinationofotherlines.TheATNlinetakesavalueto
indicateifthemessageisaconunandoradata,butitisnotsufficientto definewhoisthetalker.Otherlines
valuesalsodon'tindicatethedirection,sothismethodisnotpossible.
Theassemblycodedefinesthetalkerineverystep.Soitcanalsoassertasparelinetobe thedirectionsignal
fortheadapterboxcomponents.Unfortunatelytheparallelporthasnooutputleft.Theonlysolutionistouse
anotherportoutput(serialport).
TIFR- NCRA- GMRT TechnicalReport
Parallelport1GPIBinterface 23/28
S.2.2.2.Fina/ adapter box design
Accordingtothepreviousanalysis,theadapterboxdesignis:
Parallelport
interface
(DB25 to
DB25)
Serialport
2
2
3
10
10
GPlBinterface
(hybridcable,
~ t DB25toGPIB
connector)
_ GPIBtransmitters
_ Parallelporttransmitters
output(IX)
--Directioncontrolline
lllustration 13:Adapter box design
Componentschoice:
ThebestchoiceistousetransmittersavailableinGPmandparallelporttransceivers(SN74160,SN74162,
74ACf1284).Nevertheless.thosespecifictransceiversarenotusualandmaybedifficulttoget.
Anotherpossiblechoiceistousetheclassical74LS244octalbuffer/linedriverwith3-stateoutputs.Its
performanceswillbelessideal,butitstransmittersareabletooutputCUITents upto-15rnA.and+24mAo
Soitshouldbeabletocommunicatewith8GPmdevices.
Complementarynotes:
ThepowersupplyforICscanbetakenfromafreePCinternalpowerline.orfromanadapterlikeprinters
ones,withapowerregulator.
Groundsfrompowersupply.serialport,andICsdonotappearonthelastdesign.butofcoursetheyhave
alsotobeconnectedaltogether.
TIFR- NCRA- GMRT TechnicalReport
Parallelport/GPIBinterface 24/28
6.Multi-devicestestingandfurtherproceedings
6.1.Multi-devicestesting
Asconcludedintheparagraph4.4.2,theparallelportandtheGPIBinterfacesareinttheoryelectrically
compatibleforfewdevices.Thishasbeentestedinthefollowingconditions:
- PC:
winclnt4PC(Pentium4)underLinux
RedHat9.
- Spectrumanalysers(SPA#1 & 2):
HP8590LwithGPIBaddresssetat17
and18respectively.
- SignalGenerator(SGN):
HP8714C.
inuxP
I r-GPIBhybridcable
GPIB cable
2wayDiv
SPA#2
- Applicationprogram:
Illustration 14 : Test setting
Cfilelistedinappendix 1
"testprogram.c".
Theparallelportdriverissuccessfullyworking.Datadisplayedintheterminalshell,accordingtothe
applicationprogram,correspondateachtimetotheRFsignalsendby thesignalgeneratorandmeasuredbythe
twospectrumanalysers.
6.2.Further proceedings
This workwasthenattemptedtobeextendedtodifferenttypeof devices.
Firstconfigurationtestedonlyonevoltmeter(HP 8508A)measuringasignalvoltageonasinglechannel
directlyconnectedtoasignalgenerator.Duringthistest,writingfunctions(configuration,RST ...)wereworking
butreadingoperationsfailed.
Suchproblemcancomefromasoftwarelimitation,orsomeGPIBadditionalconfigurationforavoltmeter.No
solutionwasstraightlyfoundandthisworkthusneedsadditionalconcentratedefforts.
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Parallelport1GPIBinterface 25/28
7.Conclusion
Theparallelport-to-GPIBdriveris aprogramthatallowsaPCtobeconnectedwithGPIB programmable
instruments,tocontrolthemandtoacquiretheirdataaccordingtotheGPIB protocol.
Nowadays,PCparallelportsarecomplianttothe level2electricalspecificationsoftheIEEE1284standard,that
ensuresthattheyarepowerfulenoughtosafelycommunicatewitharound4GPIBdevices.ThedriverandaC.
applicationprogramhavesuccessfullybeentestedunderLinuxwiththeWinclnt4PC(Pentium)and2spectrum
analysers.
Forsomeweakparallelportsorformoredevices,thisreportalsogivesadesignofanadapterbox,placed
betweenthe PCandtheGPIBdevices,whichgivesabetterelectricalcompatibilitybetweenthetwointerfaces.
TheonlypossibledesignforsuchaboxrequirestouseonemorePCoutput,comingfromtheserialportfor
instance.
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Parallelport1GPIB interface 26/28
8.References
Books
1. ParallelPortComplete,Jan Axelson, Penram
2. NI-488.2UserManualforDOS,N.!. January 1996Edition, PartNumber320700-01.
3. PETandtheIEEE488bus(GPIB),Eugene Fisher- C. W. Jenson, Website
4. IBMPCAssemblyLanguageandProgramming,51bedition,Peter Abel, PearsonEducation
Datasheets
5. SN74160BISN74162BOctalGPIB transceiver,Texas Instrument, May 1995.
6. DS75160AIDS7516lAIEEE-488GPIBTransceivers,National Semiconductor, May 1999.
7. 74ACf1284IEEE1284Transceiver.Fairchild Semiconductor. November2000.
8. 74LVXZ161284(B) IEEE1284Transceiver.Fairchild Semiconductor. August2003.
9. SN74LS244bufferIlinedriverwith3-statecontrol,Motorola.
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9.Appendix
Testprogram.c
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Parallelport1GPffiinterface 28/28
File:Imisc/home/pommler/testprogram.c Page:1
iinclude<stdio.h>
iinclude<asm/io.h>
#include<time.h>
extern int initialise(int,int)i
extern int iowrite(int,char*,int)i
extern int ioread(int,char*);
long int mytime(void)
{ time_t t;
t.. time(NULL) i
return ti
} ;
main()
( char buf[3200ji
int i,n;
H(iopl(3)
( printf("\npermission denied\n");
exit(l);
n-initialise(Ox378,0);
if(n==O) printf("\ndevice initialised\n");
else
if(n==-l) printf("\ndevice not initialised\n");
else printf("\nsome handshaking problem or device not attached\n");
iowrite(18,"CF l30MZ;",9);
iowrite(18,"SP 50MZi",8);
for(i=Oii<3200;i++) buf[ij='#';
iowrite(18,"SNGLSi",6);
iowrite(18,"TS;R,3)i
iowrite(18,"TRA?i",S);
n=ioread(18,buf);
iowrite(18,CONTS;,6);
if(n<O) printf("reading ERROR\n");
if (n>O) buf[n]-'\O';
printf("\nThe dumped screen data 1 is as follows:\n\n");
printf("\n \s \n %d\n",buf,n);
iowrite(17,"CF l30MZi",9)i
iowrite(l7,"SP 50MZi",8)i
for(i=Oii<3200;i++) buf[i]-'i';
iowrite(l7,"SNGLS;",6)i
iowrite(17, "TS;",3)i
iowrite(17, "TRA?in,S)i
n=ioread(17,buf);
iowrite(l7,"CONTS;",6)i
if (n>O) buf[nj-'\O';
printf("\nThe dumped screen data 2 is as follows:\n\n");
printf("\n %s \n %d\n",buf,n);
return 0;