LG G8000 Service Manual

2.
PERFORMANCE
2. PERFORMANCE
2.1 H/W Features

Item Feature Comment
Li-Ion, 1050 mAh
Standard Battery Size: 39.5 * 67 * 5.4t (mm)
Weight: 31g
Extended Battery No Extended Battery
AVG TCVR Current Min: ?mA(Pwr Level 19), Max: ?mA(Pwr Level 5)
Standby Current < ? mA
Talk time Min : 2hr40min (2hr30min)
Max : 5hr20min(5hr)
Stand by time Up to 200 hours
Charging time 3 hours
RX Sensitivity GSM, EGSM: -108 dBm, DCS: -107 dBm
TX output power GSM, EGSM: 33(32) dBm (Level 5)
DCS: 30(29) dBm (Level 0)
GPRS compatibility Class 10
SIM card type Plug-In SIM 3V/5V
Display Main : 65535 Color-TFD(176X220)
Sub : Mono(84X40)
Status Indicator : 7-color LED
Key pad :
Status Indicator & Keypad • 0 ~ 9, #, *, Navigation Key, Up/Down Side Key
• Side Key, Confirm Key, Record Key
• Send Key, END/PWR Key,Function Key
ANT Fixed Type
EAR Phone Jack Ear-Mike connector
PC Synchronization Yes
Speech coding EFR/FR
Data and Fax Yes
Vibrator Yes
Speaker Yes
Voice Recording Yes
C-Mic Yes
Receiver Yes
Travel Adapter Yes
Options Hands-free kit, CLA, USB Cable, DTC
-7-
2. PERFORMANCE
2.2 Technical Specification

Item Description Specification
GSM
TX: 890 + n 0.2 MHz
RX: 935 + n 0.2 MHz (n = 1 ~ 124)
EGSM
1 Frequency Band TX: 890 + (n - 1024) 0.2 MHz
RX: 935 + (n - 1024) 0.2 MHz (n = 975 ~ 1024)
DCS
TX: 1710 + (n-512) 0.2 MHz
Rx: 1805 + (n-512) 0.2 MHz (n = 512 ~ 885)
RMS < 5 degrees
2 Phase Error Peak < 20 degrees
3 Frequency Error < 0.1 ppm
GSM, EGSM
Level Power Toler. Level Power Toler.
5 33 dBm 2dB 13 17 dBm 3dB
6 31 dBm 3dB 14 15 dBm 3dB
7 29 dBm 3dB 15 13 dBm 3dB
8 27 dBm 3dB 16 11 dBm 5dB
9 25 dBm 3dB 17 9 dBm 5dB
10 23 dBm 3dB 18 7 dBm 5dB
11 21 dBm 3dB 19 5 dBm 5dB
4 Power Level 12 19 dBm 3dB
DCS
Level Power Toler. Level Power Toler.
2 26 dBm 3dB 10 10 dBm 4dB
-8-
2. PERFORMANCE

GSM, EGSM
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600 ~ 1,200 -60
1,200 ~ 1,800 -60
1,800 ~ 3,000 -63
3,000 ~ 6,000 -65
5 Output RF Spectrum 6,000 -71
(due to modulation)
DCS
Offset from Carrier (kHz). Max. dBc
100 +0.5
200 -30
250 -33
400 -60
600 ~ 1,200 -60
1,200 ~ 1,800 -60
1,800 ~ 3,000 -65
3,000 ~ 6,000 -65
6,000 -73
GSM, EGSM
Offset from Carrier (kHz) Max. (dBm)
400 -19
600 -21
1,200 -21
6 Output RF Spectrum 1,800 -24
(due to switching transient)
GSM
Offset from Carrier (kHz) Max. (dBm)
400 -22
600 -24
1,200 -24
1,800 -27
Conduction, Emission Status
7 Spurious Emissions
Conduction, Emission Status
-9-
2. PERFORMANCE

GSM, EGSM
BER (Class II) < 2.439% @-102 dBm
8 Bit Error Ratio
DCS
BER (Class II) < 2.439% @-100 dBm
9 RX Level Report Accuracy 3 dB
10 SLR 8 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 0 -12
11 Sending Response 1,000 0 -6
2,000 4 -6
3,000 4 -6
3,400 4 -9
4,000 0 -
12 RLR 2 3 dB
Frequency (Hz) Max.(dB) Min.(dB)
100 -12 -
200 0 -
300 2 -7
500 * -5
13 Receiving Response 1,000 0 -5
3,000 2 -5
3,400 2 -10
4,000 2
* Mean that Adopt a straight line in between 300 Hz
and 1,000 Hz to be Max. level in the range.
14 STMR 13 5 dB
15 Stability Margin > 6 dB
dB to ARL (dB) Level Ratio (dB)
-35 17.5
-30 22.5
-20 30.7
16 Sending Distortion
-10 33.3
0 33.7
7 31.7
10 25.5
17 Side tone Distortion Three stage distortion < 10%
18 <Change> System frequency ≤ 2.5 ppm
(13 MHz) tolerance
- 10 -
2. PERFORMANCE

19 <Change>32.768KHz tolerance ≤ 30 ppm
At least 80 dB under below conditions:
20 Ringer Volume 1. Ringer set as ringer.
2. Test distance set as 50 cm
Fast Charge : < 650 mA
21 Charge Voltage
Slow Charge: < 60 mA
Antenna Bar Number Power
5 -85 dBm ~
4 -90 dBm ~ -86 dBm
22 Antenna Display 3 -95 dBm ~ -91 dBm
2 -100 dBm ~ -96 dBm
1 -105 dBm ~ -101 dBm
0 ~ -105 dBm
Battery Bar Number Voltage
0 3.62 V~
1 3.62 ~ 3.71 V
23 Battery Indicator
2 3.71 ~ 3.79 V
3 3.79 ~ 3.93 V
4 3.93 V~
3.5 0.03 V (Call)
24 Low Voltage Warning
3.62 0.03 V (Standby)
25 Forced shut down Voltage 3.28 0.03 V
1 Li-Ion Battery
Standard Voltage = 3.7 V
26 Battery Type
Battery full charge voltage = 4.2 V
Capacity: 1050 mAh
Switching-mode charger
27 Travel Charger Input: 100 ~ 240 V, 50/60 Hz
Output: 5.2 V, 1.5 A
- 11 -
3. TECHNICAL BRIEF
3. TECHNICAL BRIEF
3.1 Receiver
The receiver part consists of a dual band (GSM & DCS) antenna switch, two RF SAW filters, an
external dual RF VCO and a transceiver IC (TRF6150). All active circuits for a complete receiver
chain with the exception of RF VCO are contained in the transceiver IC (TRF6150).
The TRF6150 chip set has direct conversion structure, so the received RF signal is directly
converted to base band I and Q signal by the transceiver IC (IF frequency is 0 Hz), which contains
two LNAs and three direct conversion demodulators for E-GSM, DCS and PCS. The demodulated I
and Q signals pass two base band AGC amplifiers and a channel filter, which are on both I and Q
signal paths. The RF front-end circuit is shown Figure 3-1.
Figure 3-1. RF front-end circuit
- 12 -
3. TECHNICAL BRIEF
3.1.1 RF front end

RF front end consists of an antenna, a dual band antenna switch, two RF SAWs and two LNAs for E-
GSM, DCS band, which are contained in the transceiver IC (TRF6150).
The RF received signals (GSM 925MHz ~ 960MHz, DCS 1805MHz ~ 1880MHz) are input via the
antenna or coaxial connector. An antenna matching circuit is between the antenna and the
connector.
The antenna switch (FL103) is used to control the Rx and TX paths, which has two control signals
VC1 and VC2 that are connected to 4-Input NOR Gate (U102) to switch either TX or RX path on.
When the RX path is turned on, the received RF signal, which has passed through the dual band
antenna switch, is filtered by an appropriate RF SAW filter for better stop band rejection. The filtered
RF signal is amplified by an LNA integrated in the transceiver IC(TRF6150) and pass to a direct
conversion demodulator. This process is the same both GSM and DCS.
The logic and current is given below. Table 3-1.
Table 3-1. The logic and current
VC1 VC2
GSM TX 2.7 V 0V
DCS TX 0V 2.7 V
GSM/DCS RX 0V 0V
3.1.2 Demodulator and Baseband Processing

IF stage is not necessary in this system because the receiver is based on direct conversion
architecture. So the RX LO frequency is the same as input radio frequency. The amplified signal at
LNA stage passes to a direct conversion demodulator and is mixed down to generate I&Q BB
signals. The BB I&Q signals pass via two integrated baseband amplifiers with digitally programmable
gain and two fully integrated baseband channel filters to the baseband A/D converters which is
contained in baseband chipset. Figure 3-2 shows RX path block diagram.
3.1.3 DC offset compensation

The transceiver IC(TRF6150) is based on direct-conversion architecture. This implies that a parasitic
DC offset may appear at the output of the IQ demodulator. To reduce the static offset due to
components mismatch and LO self-mixing, the IC includes a hardware DC offset compensation
circuit on both I and Q base band paths. The transceiver IC uses a divider by 2 for LO generation in
EGSM and a multiplier by 2 in DCS to minimize the DC offset generated by self mixing and the LO
radiation. In addition, a quadrature demodulator gain mismatch calibration system is used to reduce
the signal distortion.
- 13 -
3. TECHNICAL BRIEF
Figure 3-2. RX path block diagram
Table 3-2. Gain and Noise Figure of RX path
Ant. switch RF SAW Filter I,Q demodulator (LNA+Mixer)

GSM -0.6 -2.5 26
Gain(dB)
DCS -0.7 -2.4 23
GSM 3
NF(dB)
DCS 3.5
Table 3-3. Total Gain and Noise Figure of RX path
Total Gain Total Noise Figure

GSM, EGSM 22.9 dB 7.2 dB
DCS 19.9 dB 7.4 dB
- 14 -
3. TECHNICAL BRIEF
3.2 Synthesizer
The TRF6150 includes two synthesizer parts. Two synthesizers consist of an IF synthesizer, which is
an integer-N synthesizer, and a RF synthesizer, which is a fractional-N synthesizer. The TRF6150 is
a transceiver IC suitable for GSM and DCS GPRS up to class 12 applications. So, synthesizers use
a number of techniques to improve lock time, making them well suited to GPRS.
The main fractional-N synthesizer (RF synthesizer), which includes a RF VCO with external tank
circuits, is necessary for both transmitting and receiving operation. The RF VCO works only when
the transmitting operation is on. The main fractional-N synthesizer has frequency band from 1294
MHz to 1356 MHz. Output frequency of the RF VCO is set by the factional number, prescaler and
counter. A buffer amplifier follows the RF VCO. The purpose of the buffer is to give reverse isolation
and prevent any frequency pulling of the VCO when the transceiver is powered UP and DOWN.
A dual band external VCO, which uses the PLL block of the main fractional-N synthesizer, is
necessary for transmitting and receiving operation. The dual band means that it can support GSM,
DCS frequency operation. For transmitting operation, the OPLL block of the TRF6150 directly
modulates the dual band external VCO with I and Q signals. For receiving operation, the external
VCO output frequency band is from 902 to 940MHz for DCS Rx and from 1850 to 1920MHz for GSM
Rx. The frequency of the signal from the external VCO is divided by 2 for GSM Rx and is doubled by
2 for DCS Rx operation before entering into the direct conversion mixer.
The auxiliary integer-N synthesizer (IF synthesizer), which includes an IF VCO with external tank
circuits, is necessary for transmitting operation only. The IF VCO has a frequency band from 832
MHz to 858 MHz. Output frequency of IF VCO is settled by prescaler and counter. The fractional
counter in the RF synthesizer just differs from the IF synthesizer. The IF VCO is also followed by a
buffer amplifier, which is to give reverse isolation and prevent any frequency pulling of the VCO
when the transceiver is powered UP and DOWN.
A fixed reference frequency of 1.3MHz for Rx (or 2.6MHz for Tx) is generated by a reference divider
from the external applied 13 MHz crystal oscillator.
The phase frequency detector with charge pump provides programmable output current, which could
drive the capability and the pulse width.
The counter and mode settings of the synthesizer in the TRF6150 are programmed via 3-wire
interface.
Table 3-4. 3-wire BUS of Synthesizer in the TRF6150
Pin Number Description

TSPCLK 11 Serial clock input to the synthesizer
TSPDATA 12 Serial data input to the synthesizer
TSPEN 13 Input latches the serial data transferred to the synthesizer
- 15 -
3. TECHNICAL BRIEF
Dual band VCO :

902 ~ 940MHz DCS Rx
1850 ~ 1920MHz GSM Rx
RF SYNTHESIZER
2.6/1.3MHz
13MHz
or :2 : 5/ 10
26MHz PFD
1294 ~ 1356MHz
TANK
RX : OPEN
7 bits 4 bits 4 bits 16/17
TX : CLOSED A B FN P/P+ 1
2.6MHz
IF SYNTHESIZER
Delay
PFD
6 bits 3bits 8/9

A B P/P+ 1 TANK
832 ~ 858MHz
Figure 3-3. Synthesizer internal Block Diagram
- 16 -
3. TECHNICAL BRIEF
The IF and RF output frequencies of the TRF6150 are set by programming the internal divider registers.
The frequency setting equations of the IF and RF frequencies are as follows.
is the output frequency of the IF VCO (the auxiliary integer-N synthesizer) and fRFout is the output
frequency of the RF VCO (the main fractional-N synthesizer). The frequency band of the RF VCO is from
1294MHz to 1356 MHz, and the frequency band of the IF VCO is from 832MHz to 858Mhz, which
frequency bands are only for the transmitting operation.
C116
VT 13
FL101 R107
C118
ENFVF382S18
C117 R109
57 MAINSPUP2
R110
R111
59 TXRXCP
58 R2
60
MAINSPUP14
MAINCP 5
MAIN PFD
PLL
U105
TRF 6150
R124
Interface
CLK 11
Serial
TSPCLK
R123 DATA 12
TSPDATA
TSPEN R128 EN 13
35MAINVCO
AUXCP 14
AFC C146 AUX.
R131 CRF 16 PLL
X101
VCC7 22
AUXVCOP 23
AUXVCON 24
C175 D102 C156

C142 VC-TCXO-208C
HVC369B
R140
C164 L108
C167
L105
C174
R145 C185
C176 C177
R141 L109 C184
R139
R142 R143
C178 L110
R137 C183
C179
D103
SMV 1233-074
Figure 3-4. Synthesizer circuit
- 17 -
3. TECHNICAL BRIEF
3.3 Transmitter
The Transmitter part contains TRF6150 active parts, PAM, coupler, dual schottky diode and dual
band VCO. The TRF6150 active parts consist of the vector modulator and offset phase-locked loop
block (OPLL) including down-converter, phase detector, and APC IC for power control. The VCO
feed the output frequencies into PAM and TRF6150 for Tx local frequency. The peak output power
of the PAM is controlled by means of a closed feedback loop. A dual band directional coupler is
used to control the RF output from the PAM. The PAM outputs from the directional coupler pass to
the antenna connector via an integrated dual band antenna switch module.
2.6/1.3MHZ
RFout_rx = (P*A + B + FN/13)*1.3MHz
MAINspup1
TX
LF MAINcp
:5/10 :2 CRF
RX
1294~1356 MHz
TANK MAINvco
VC1 VC2
VC1
TX 2.6V 0V
GSM
VC2
RX 0V 0V 16/17 4bits 4bits 7bits VR4in
DCS
TX 0V 2.6V P/P+1 FN B A CLK
RX 0V 0V Serial Control DATA
Logic & EN
Resisters
RESETZ
AUXcp Delay
LF
SHS-M090B
832~858 MHz
AUXvcon
TANK 8/9 3bits 6bits
AUXvcop
P/P+1 B A
DCS EGSM
APC DAC
IFout = (P*A + B)*13MHz
APCEN PA
DETD CONTROLLER RFout_tx = (P*A + B + FN/13)*2.6MHz
DETR
Vapc FILT
/2
BAT15-05W
OMIXrf
416-429MHz
LBTX
R3
IN
LF TXRXcp
PFD IP
MAINspup2
HBTX 90˚
R2
LDC15D190A0007A QN
HBRX
PF08122B ENFVF382S18 QP
HBswitch
LBswitch
TXRXswitch
Vreg3 CLARA
L.B./L.P. L.B./H.P. H.B./L.P. H.B./H.P.
TRF6150
L.B
0 0 1 1
ON/OFF
H.B 1 1 0 0
ON/OFF
RX/TX ON=0/OFF=1
1 0 1 0
SWITCH RX=1/TX=0
Figure 3-5.Transmitter Block Diagram
- 18 -
3. TECHNICAL BRIEF
3.3.1 Tx Modulator
The Tx I & Q signals from BB analog chipset are fed to the TRF6150 Tx modulator, where they are
modulated onto either a Tx of 880 MHz(for GSM-Tx) or 1710 MHz(for DCS-Tx) by the quadrature
mixer inside the U604. The Tx LO signal(1294 – 1356 MHz, 426.4 MHz) is fed from the internal main
and aux. VCO.
The modulator provides more than 40dBc of carrier and unwanted side-band rejection and produces
a GMSK modulated signal. The BB software is able to cancel out differential DC offsets in the I/Q BB
signals caused by imperfections in the D/A converters. The Tx-Modulator implements a quadrature
modulator. The frequency input signal is split into two precise orthogonal carriers, which are
multiplied by the BB modulation signal IP/IM and QP/QM. It is used as reference signal for the OPLL.
AUX PLL
N-integer
R505
18 QN
QM
R506 C502
19 QP
QP
R501 :2
20 IN
IM
R502 C501
21 IP
IP
R129
22 RESETZ
RESETCL C143
MAIN PLL
N-fractional
C123 OMIXRF
51
880 - 915MHz(TX, GSM) PFD
1710 - 1785MHz(TX, DCS)
U105
VREG3
62 TRF6150
R114 R113
TXRXCP R2 MAINSPUP2 CLK DATA EN

FL101 TXVCO L153
11 59 58 57 11 12 13
VCC
1 C110 R110 R111 R124 R123 R128
GSM_OUT
6
DCS_OUT TSPEN
GND TSPDATA
R107 C118
2,5,7 12,14 13 TSPCLK
VT
PWR_SW DCS_SW GSM_SW C117 R109

ENFVF382S18 C116
8 9 10
GSM TX DCS TX
TXRXSW 0 0
LBSW
LBSW 0 1
HBSW
HBSW 1 0
TXRXSW
Figure 3-6. Tx IF Modulator and OPLL Circuit
- 19 -
3. TECHNICAL BRIEF
3.3.2 OPLL
The down converter contained inside of the TRF6150 (U105) mixes the Tx RF frequency with the RF
VCO signal from the ENFVF382S18 (FL101) to generate a ‘feedback’ signal at 414.4MHz for
GSM,EGSM and DCS operation. The ‘feedback’ signal passes to one port of the phase detector.
The GMSK ‘reference’ signal from the Tx IF modulator passes via a second limiter to the other input
port of the phase detector. The phase detector generates an error current proportional to the phase
difference between the ‘feedback’ signal from the down-converter and the ‘reference’ signal from the
Tx IF modulator.
The error current is filtered by a second order low-pass filter to generate an output voltage, which
depends on the GMSK modulation and the desired channel frequency. This voltage controls the
transmit VCO such that the VCO output signal, centered on the correct RF channel is frequency
modulated with the original GMSK data. The center frequency of the transmit VCO is offset from the
RF VCO frequency by 414.4MHz for GSM, EGSM and DCS oper ation.
3.3.3 Power Amplifier

The PF08122B (U101) is Dual band power amplifier for EGSM (880 to 915 MHz) and DCS (1710 to
1785 MHz). The efficiency of module is the 55% at 35 dBm for E-GSM and the 50% at 32.5 dBm for
DCS for 3.5 V nominal battery use.
This module should be operated under the GSM burst pulse. To avoid permanent degradation, CW
operation should not be applied. To avoid the oscillation at no input power, before the input is cut off,
the control voltage Vapc should be control to less than 0.5 V. We have to improve thermal
resistance, the through holes should be layouted as many as possible on PCB under the module.
And to get good stability, all the GND terminals and the metal cap should be soldered to ground
plane of PCB.
C107 R138 45 DETR
C134 R117 U105

46 DETD
TRF6150
FL103
SHS-M090B VAPC FILT APC APCEN
D101 BAT15-05w 48 47 8 9
C131
R125 PA_ON
R112 R116
R126
C188 PA_LEVEL
R120 C120
C136
C135
VBAT
R119 C154 C130 C125
2 U101 PAM PF08122B
R103 Vapc +
C199 Vdd1 3 C153
N101 L150
C133 4 GSM GSM 1
C119
1 OUT IN 7
B1
L191 C191
8 4 Vdd2
6
C132 C186
3 B2 5 5 DCS DCS 8 C150 R133
C198 GND R135 R134
2,6 Bias Circuit
GND Vctl
Directional Coupler 9,10,11,12 7
LDC15D190A0007A H : GSM, L : DCS
Figure 3-7. Power Amplifier and its Control Part Circuits
- 20 -
3. TECHNICAL BRIEF
3.3.4 PA Circuit and Control

The power amplifier control circuit ensures that the RF signal is regulated to the required limits of
operation. RF power is controlled by driving the power control pins of power amplifier and sensing.
The resultant RF output power via a directional coupler (N101). The RF sense voltage is peak
detected using an schottky diode of BAT15-05W (D101). This detected voltage is compared to the
DAC voltage in the TRF6150 to control the output power.
An internal input signal (PA_LEVEL) from CALYPSO, which is digital BB chipset (U503), is applied
to the APC IC in TRF6150 during the PA_ON mode and a directional coupler near the antenna feeds
a portion of the RF output signal back to the APC IC and peak detector converts this signal to a low
frequency feedback signal that balances the amplifier when this signal is equal to the RAMP input
signal level.
3.4 13 MHz Clock

The 13 MHz clock (VC-TCXO-208C) consists of a TCXO (Temperature Compensated Crystal
Oscillator), which oscillates at a frequency of 13 MHz.
The 13MHz clock is used within the Synthesizer block of the TRF6150, BB Analog chip-set
(NAUCICA_CS), and Digital (CALYPSO). The inverter IC, TC7SZ04AFE buffers the output to
NAUCICA_CS and CALYPSO.
Pin#3@ U104
C147 R130
R913 R131 AFC

4 VCC VCONT 1
C139
C142
3 OUT GND 2
R913
R121 X101
VC-T CXO-208C
13MHz
4Y GND 3
C140
CRF@TRF6150
A2
5 VCC NC 1
U103
TC7SZ04AFE
Figure 3-8. VCTCXO Circuit
- 21 -
3. TECHNICAL BRIEF
3.5 Power Supplies and Control Signals

Three Regulators are integrated in the TRF6150 to provide DC power to the RF blocks (Regulator
R1, R2, R3). The Regulator R1 is used to provide DC power to the receiver, the transmitter and the
PA control loop of the TRF6150. The Regulator R2 is used to provide DC power to the DC offset
compensation circuit, the auxiliary synthesizer, the main synthesizer and VCOs. The Regulator R3
is used for the external Rx/Tx VCO, switchplexer control buffer. An external regulator is used to
provide DC power to the VCTCXO (X101).
Table 3-5. Regulator Specification
Regulator Voltage Powers Enable Signal

Regulator R1, R2, R3 Receiver, Transmitter,
(These are all integrated 2.8 V 0.1 V Synthesizers, VCOs
in the TRF6150)
LP3985IBPX_2.8V (U104) 2.85 V 0.1V VCTCXO TCXO_EN
TCXO_EN R132
1 VEN BYPASS 5
2 GND
2.85V_OUT VBAT_RF
3 VOUT VIN 4
U104
LP3985IBPX_2.8V
C148 C149
RADIO_TEMP
R182
PT101 R181 R183
Figure 3-9. External Regulator Circuit
- 22 -
3. TECHNICAL BRIEF
3.6 Digital Baseband (DBB) Processor
32KHz CRYSTAL
IT Alarm
RTC
MCU top-cell
Boot ROM Ck32khz
External
ARM7 MEMIF ULPD
B
Memories Memory R GSM time
protect Debug Unit I
Unit D
G
RREA bus TPU
ARM7 E
1Mbit
SRAM TSP
W
r SIM
1Mbit i
SRAM t 8K API
e cDSP PWL
1Mbit s28c128
SRAM b UART
u irda
1Mbit f
UART
SRAM DSP subchip
modrn
Figure 3-10. Top level block diagram of the Calypso G2 (HERCROM400G2)
3.6.1 General Description

CALYPSO is a chip implementing the digital base-band processes of a GSM/GPRS mobile phone.
This chip combines a DSP sub-chip (LEAD2 CPU) with its program and data memories, a Micro-
Controller core with emulation facilities (ARM7TDMIE), internal 8Kb of Boot ROM memory, 4M bit
SRAM memory, a clock squarer cell, several compiled single-port or 2-ports RAM and CMOS gates.
The chip will fully support the Full-Rate, Enhanced Full-Rate and Half-Rate speech coding.
CALYPSO implements all features for the structural test of the logic (full-SCAN, BIST, PMT, JTAG
boundary-SCAN).
- 23 -
3. TECHNICAL BRIEF
3.6.2 Block Description

CALYPSO architecture is based on two processor cores ARM7 and DSP using the generic RHEA
bus standard as interface with their associated application peripherals.
CALYPSO is composed from the following blocks:
• ARM7TDMI CPU core

• DSP subchip
• ARM peripherals:
General purpose peripherals
• ARM Memory Interface for external RAM, Flash or ROM
• 4 Mbit Static RAM with write-buffer
Application peripherals
• ARM General purposes I/O with keyboard interface and two PWM modulation signals
• UART 16C750 interface (UART_IRDA) with
- IRDA control capabilities (SIR)
- Software flow control (UART mode).
• UART 16C750 interface (UART_MODEM) with
- hardware flow protocol (DCD, CTS/RTS)
- autobaud function
• SIM Interface.
• TPU (Time Processing Unit) : Processing for GSM time base
• TSP (Time Serial Port) : GSM data interface with RF and ABB
Memory Interface : External/Internal Memory Interface

nCS0 : FLASH1, 16bit access, 3 wait state
nCS1 : Pseeudo - SRAM, 16bit access, 3 wait state
nCS2 : Not Used
nCS3 : Not Used
nCS6 : Int SRAM, 32bit access, 0 wait state
* Calypso internal 39MHz machine 3 wait state is necessary for the 80ns access because of 25ns
machine cycle. (25*4 = 100ns)
- 24 -
3. TECHNICAL BRIEF
3.6.3 External Devices connected to memory interface

Table 3-6. External Device Spec connected to memory interface
Interface SPEC
Write Read
Device Name Maker Access Access
Time Time
FLASH 1 TH50VPF5683DASB Toshiba 80ns 80ns
SRAM TH50VPF5683DASB Toshiba 70ns 70ns
3.6.4 RF Interface (TPU, TSP block)

Calypso uses this interface to control Nausica_CS (ABB Processor) and Clara (RF Processor) with
GSM Time Base
Table 3-7. RF Interface Specification
TSP (Time Serial Port)

Resource Interconnection Description
TSPDO ABB & RF main Chip Control Data
TSPEN0 ABB ABB Control Data Enable Signal
TSPEN1 RF main Chip RF Control Data Enable Signal
TPU (Time Processing Unit) Parallel Port
TSPACT00 RESET_RF RF main Chip Reset Signal
TSPACT05 PA_ON Power Amp ON signal
- 25 -
3. TECHNICAL BRIEF
3.6.5 SIM interface

SIM interface scheme is shown in (Figure 3-11).
SIM_IO, SIM_CLK, SIM_RST ports are used to communicate DBB with ABB and the Charge Pump
in ABB enables 3V/5V SIM operation.
Table 3-8. SIM Interface
SIM (Interface between DBB and ABB)

SIM_RST SIM card async/sync reset
SIM_PWCTRL SIM card power activation
SIM_IO SIM card bidirectional data line
SIM_CLK SIM card reference clock
SIM_PWCTRL SVDD
20K Naucica 20K

VDD
SIM_IO SIO3 SIO5 IO
CARD
SIM_CLK SCLK3 SCLK5 CLK
SIM_RST SRST3 SRST5 RST
Figure 3-11. SIM Interface
3.6.6 UART Interface

The model has two UART Drivers as follow :
- UART1 : Interface and Communication with Helen UART2
- UART2 : Interface and Communication With Helen UART1
Table 3-9. UART Interface Specification
UART MODEM (UART1)

Resource Name Note
TX_MODEM TXD Transmit Data
RX_MODEM RXD Receive Data
CTS_MODEM CTS Clear To Send
RTS_MODEM RTS Request To Send
GPIO 11 DTR Data Terminal Ready
GPIO 12 DCD Data Carrier Detect
UART IRDA (UART2)
TX_IRDA TX Transmit Data (UART2)
RX_IRDA RX Receive Data (UART2)
- 26 -
3. TECHNICAL BRIEF
3.6.7 GPIO map

In total 16 allowable resources, This model is using 12 resources except 4 resources dedicated to
SIM and Memory. GPIO(General Purpose Input/Output) Map, describing application, I/O state, and
enable level, is shown in below table.
Table 3-10. GPIO Map Table
I/O # Application I/O Resource Inactive State Active State

I/O (0) _HEL_SYS_RST O GPIO HIGH (Helen Reset released) LOW (Helen is reset)
I/O (1) CAL_TX_MBOX O GPIO HIGH LOW
HIGH (UART Modem LOW (UART modem
I/O (2) CAL_UART_SEL O GPIO connected to Keypad isconnected to Helen
connector) UART2)
I/O (3) MOTOR_EN O GPIO LOW HIGH
I/O (4) HEL_TX_MBOX I GPIO LOW HIGH
I/O (5) SIM_PWCTL O SIM
I/O (6) BAT_SENSE I GPIO LOW HIGH
I/O (7) DTC_SENSE I GPIO LOW HIGH
LOW (Audio out path HIGH (Audio out path is
I/O (8) HS_HF_SW O GPIO is connected to EarJack) connected to HandsFree)
I/O (9) NOT USED
HIGH (Nausica VDR is LOW (Nausica VDR is
I/O (10) MM_AUDIO_C_H O GPIO connected to Helen) connected to Calypso)
I/O (11) CAL_UART_DTR I GPIO LOW HIGH
I/O (12) CAL_UART_DCD O GPIO LOW HIGH
HIGH (Audio out is LOW (Audio out path is
I/O (13) EAR_SPEAKER_SW O GPIO connected to Speaker) connected to Earjack)
I/O (14) NBHE O MEMORY
I/O (15) NBLE O MEMORY
3.7 Analog Baseband (ABB) Processor

Nausica CS is Analog Baseband (ABB) Chip supports GSM900, DCS1800, GPRS Class 10 with
Digital Basband Chip (Calypso G2)
Nausica_CS processes GSM modulation/demodulation and power management operations.
Block Description
- Audio Signal Processing & Interface
- Baseband in-phase (I), quadrature (Q) Signal Processing
- RF interface with DBB (time serial port)
- Supply voltage regulation
- Battery charging control
- Switch ON/OFF
- 3V/5V SIM card Interface
- 4 internal & 5 external ADC channels
- 27 -
3. TECHNICAL BRIEF
3.7.2 Audio Signal Processing & Interface

Audio signal processing is divided Uplink path and downlink path.
The uplink path amplifies the audio signal from MIC and converts this analog signal to digital signal
and then transmit it to DBB Chip. This transmitted signal is reformed to fit in GSM Frame format and
delivered to RF Chip. MICBIAS is 2.5V level.
The downlink path amplifies the signal from DBB chip and outputs it to Receiver (or Speaker).
SLR = 8 +/- 3dB
620mVrms
365mVrms AUXI : 4.6dB
28.2dB
Sensitivity
-49.3dBv/Pa PGA :
MICAMP ADC UL Filter Gain 0dB +3dBm0 Full
25.6dB 2.5dB 3.5dB +12dB -12dB Scale
32.5mVrms Step 1dB
Sidetone :
1.385Vrms 1.237Vrms VREF 1.75V +1dB -23dB
EARAMP Mute
1dB
Sensitivity
106.7dBspl/Vrms
DAC & Digital PGA : Volume

AUXAMP Gain 0dB DL Filter Control : +3dBm0 Full
692mVrms Smoothing Modulator Scale
-5dB +6dB -6dB 0dB 0dB -24dB
Filter 0dB 0dB
Step 1dB +Mute
BUZZER
0V to AVDD Pulse Width
Modulation
1MHz
RLR = 2 +/- 3dB
Figure 3-12. Audio Interface Block Diagram
- 28 -
3. TECHNICAL BRIEF
Audio
3.8.3 Audio
R815
MICBIAS
1K
R849
C809
1K
0.1u
OBG-15S44-C2
MICP
C812
27p
1
C814 C854 C857
MIC801
10u
C815
27p 27p
0.1u
2
MICN
C817
R848
27p
SP17
SP18
1K
R906
R905
Nausica_CS
EARP
C523
EARN
C522
C521
AVDD
U803
B2
B4
MAX4684EBC
From Calypso
G1
V+
C2 C4
HS_HF_SW IN1 NO1 HF_SPK_P (Handsfree Speaker)
A2 A4
IN2 NO2 HF_SPK_N (Handsfree Speaker)
R814 0 C3 C1
AUXOP COM1 NC1
R812 A3 A1
AUXON 0
COM2 NC2
GND
G2
C804 C807
R813
10p 10p C808

B1
B3
10p
HEL_IO_MEM_2.8V
R824
10K
3
R823
1K
To OMAP1510 C KEY_ROW1
4
AVDD STEREOJACK_DET B Q810

DTC144EE
E
U805
2
C806
V+ B4
G1 B2
MAX4684EBC
R822
10u
1
1K
R828
R804
15
C904
1K
C2 C4 HF_MIC Q803 UMD2N

IN1 NO1 (FromHandsfree Mic) 0.1u
From Calypso
C810
220n
A2 A4
EAR_SPEAKER_SW IN2 NO2 Speaker_ 1
R871 C3 C1 Output_To_MIDI R803 0 2
AUXI COM1 NC1 3
C821
220n
470 A3 A1 C889 10uF 4

C819 COM2 NC2 R846 5
47p
GND
6
Nausica 0
G2
SMF05C
C802 C813
1
3
4
5
6
J801
B1
B3
47p 47p
SP13
SP14
SP15
R881
D1
D2
GNDD3
D4
D5
0
R816
D801
R882 0
2
R883 0
R884 0
Figure 3-13. Audio Section Scheme
- 29 -
3. TECHNICAL BRIEF
Audio Voice Mode

-Audio Voice Mode is 5 Mode.
Table 3-11. Audio Voice Mode Table
Nausica_CS in/out Port

Mode
IN OUT
Receiver Mode MICP, MICN EARP, EARN
Headset Mode AUXI AUXOP, AUXON
Speaker Phone Mode MICP, MICN AUXOP, AUXON
HandsFree Mode AUXI AUXOP, AUXON
Voice Mode controlled by Two analog switch (dual)

Headset, SpeakerPhone and HandsFree Mode is controlled by Two analog switch (dual).
Two Geneal Purpose IO Signal (HS_HF_SW, EAR_SPEAKER_SW) from calypso control
two analog switchs (U803, U805).
Table 3-12. Analog Switch Contol Mode

Uplink
HS_HF_SW EAR_SPEAKER_SW Mode

Low Low Headset
Low High SpeakerPhone
High Don’t care HandsFree
The microphone (Zebra Type) is touched to the main PCB. The uplink signal is passed to MICIP
and MICIN pins of Nausica_CS. The MICBIAS voltage is supplied from Nausica_CS (dedicated
mode only) through R815 and R849.
When the headset is inserted, STEREOJACKDET outputs High state and HS_HF_SW,
EAR_SPEAKER_SW outputs Low states.
Side Tone to Voice Downlink
MICBIAS
Bias
generator
MICIP
Microphone UPLinkIIR PGA To voice
Sigma delta SINE
amplifiter bandpass +12.....-12dB serial
Mod. 2.48dB Filter
25.6dB filter 3.52dB interface
MICIN
Fs1=1KHz Fs2=40KHz Fs3=8KHz

Auxihary
AUXI amplifier
4.6dB
28.2dB
Figure. 3-14 Uplink Path
- 30 -
3. TECHNICAL BRIEF
Downlink
The downlink signal is passed from EARP and EARN pins of Nausica_CS. When the headset is
inserted and OMAP1510 detects ‘STEREOJACK_DET’ signal (High Active), OMAP1510 informs
Calypso of inserting jack
And then, Calypso makes Nausica_CS switches the downlink path from ‘EARP’ and ‘EARN’ to
‘AUXOP’ and ‘AUXON’.
AUXOP Side Tone

Auxiliary from uplink
AUXON amplifier
-5dB
EARP
Earphone 4bit output REceive PGA DownLink Volume From voice
DAC and (-6dB -+6dB Bandpass
ampifier sigma_delta Control serial
LPF step 1dB Filter IIR
1dB modulator interface
EARN
Fs1=1KHz Fs2=40KHz Fs3=8KHz
EUZZER
PWM
BUZZOP
Figure. 3-15 Downlink Path
Speaker Phone
In speakerphone mode, Calypso makes ‘SPKER_EN’ to High state and AUXOP signal is passed to
speaker (located in upper Folder Case) through two analog switches (U803,U805) AND Melody IC
(U807).
MM (Multimedia)_Audio
In MM_Audio mode, There are two path ( Multimedia speaker and Multimedia Headset) for
multimedia audio.
OMAP1510 makes ‘MMAUDIO_CAL_HEL’ to High state and multimedia audio signal from
OMAP1510 is passed to speaker (located in upper Folder Case) or headset through MUX switches
(U555), Nausica_CS(U501) and external voice path (Speakerphone, Headset).
Table 3-13. Analog Switch Contol Mode
MMAUDIO_CAL_HEL State Mode

High Multimedia Audio Mode
Low Voice Mode
- 31 -
3. TECHNICAL BRIEF
3.7.3 Baseband Codec (BBC)

Baseband codec is composed of baseband uplink path (BUL) and baseband downlink path (BDL).
BUL makes GMSK Gaussian Minimum Shift Keying) modulated signal which has In-phase (I) com-
ponent and quadrature (Q) component with burst data from DBB. This modulated signal is
transmitted through RF section via air.
BDL process is opposite procedure of BUL. Namely, it performs GMSK demodulation with input
analog I&Q signal from RF section, and then transmit it to DSP of DBB chip with 270KHz data rate
through BSP.
6-bit Offset
from TSP Timing
DAC Reg.
Control
BULIP
Burst Cos 10-bit Low-pass
Buffer1 Table DAC Filter
GMSK
BULIM
Modulator 16X270kHz
Burst Sine 10-bit Low-pass BULQP
Buffer2 Table DAC Filter
270kHz BULQM
from BSP
6-bit Offset
DAC Reg.
Baseband Codec Uplink Block
to BSP Downlink Block

Offset
- Reg. FIR SINC Sigma-Delta Anti-aliasing BDLIP
Filter Filter Modulator Filter
M
BDLIM
+
Fs=270.8kHz Fs=1.08MHz Fs=6.5MHz
+ BDLQP
M
FIR SINC Sigma-Delta Anti-aliasing

Filter Filter Modulator Filter
- Offset BDLQM
Reg.
Figure 3-16. Baseband Codec Block Diagram
- 32 -
3. TECHNICAL BRIEF
3.7.4 Voltage Regulation (VREG)

There are 5 LDO (Low Drop Output) regulators in ABB chip.
The output of these 5 LDOs are as following table. (Figure 3-17) shows the power supply related
blocks of DBB/ABB and their interfaces.
U505
D510
0.1uF
R550
C524 X501
Figure 3-17. Power Supply Scheme
Table 3-14. LDO Output Table
Output Voltage Usage

VR1 1.8V Digital Core of DBB
VR1B 2.0V Digital Core of ABB
VR2 2.8V Memory Interface of DBB
VR2B 2.8V Digital I/Os of DBB & ABB
VR3 2.8V Analog Block
- 33 -
3. TECHNICAL BRIEF
3.7.5 ADC Channels

ABB ADC block is composed of 4 internal ADC (Analog to Digital Converter) channels and 5 external
ADC channel. This block operates charging process and other related process by reading battery
voltage and other analog values.
Table 3-15. ADC Channel Spec
ADC 9 channels
Resource Name
VCHG VCHG
VBAT VBAT Charging Management
ICHG ICHG
VBACKUP VBACKUP Backup Battery
ADCIN1 RADIO_TEMP Temperature Sensing
ADCIN2 BATT_Thermister Battery Temperature Detect
ADCIN3 Not Used
ADCIN4/TSCXP Not Used
ADCIN5/TSCYP Not Used
3.7.6 Charging
Charging block in ABB processes charging operation by using VBAT, ICHG value through ADC
channel. Battery Block Indication and SPEC is as follow.
4.2 ~ 3.93V 3.93 ~ 3.79V 3.79 ~ 3.71V 3.71 ~ 3.62V 3.62 ~ 3.5V
Figure 3-18. Battery Block Indication
Charging method : CC-CV

Charger detect voltage : 4.0V
Charging time : 3h
Icon stop current : 100mA
Charging current : 540mA
CV voltage : 4.2V
Full charge indication current (icon stop current) : 100mA
Low battery alarm
a. Idle : 3.62V
b. Dedicated : 3.50V
Low battery alarm interval :
Idle : 3 min
Dedicated:1 min
- 34 -
3. TECHNICAL BRIEF
Switch-off voltage : 3.28V

Charging temperature adc range
~ -20 °C : not charging operation.
-20 °C ~ 47 °C : charging.
47 °C~ : not charging operation.
3.7.7 Switch ON/OFF

Power State : Defined 4 cases as follow
- Power-ON : mobile is powered by main battery or backup battery.
- Power-OFF : mobile isn’t any battery.
- Switch-ON : mobile powered and waken up from switch-off state.
- Switch-OFF : mobile is powered to maintain only the permanent function (ULPD).
To enter into Switch-ON state, one of following 4 condition is satisfied.
- PWR-ON :pushed after a debouncing time of 30ms.
- ON_REMOTE : After debouncing, when a falling edgeis detected on RPWON pin.
- IT_WAKE_UP : When a rising edge is detected on RTC_ALARM pin.
- CHARGER_IC :When a charger voltage is above VBAT+0.4V on VCHG.
3.7.8 Memories
• 64Mbit/32Mbit Flash/SRAM MCP
64Mbit Flash + 32Mbit SRAM
• 16 bit parallel data bus
• ADD01 ~ ADD22
- 35 -
3. TECHNICAL BRIEF
3.8 Multimedia Processor (HELEN)
Figure 3-19. Top Level Block diagram of Helen OMAP1510

The OMAP1510 processor features 1st generation TI OMAP architecture with the OMAP3.1 gigacell
as its core building block. The OMAP1510 processor provides application developers with an open,
easy-to-use programming environment by supporting popular os and programming languages. The
OMAP1510 performs all personal communication system tasks such as PDA, PIM tasks.
The OMAP1510 device includes the MPU subsystem, the DSP subsystem, a memory interface
traffic controller, general-purpose peripherals, dedicated multimedia application peripherals, and
multiple interfaces. The MPU is the master of the platform, and it has access to the entire 16M bytes
of memory space and to the 128K bytes of I/O space of the DSP subsystem. Additionally, the MPU
and DSP share access to the internal SRAM and external memory interface.
- 36 -
3. TECHNICAL BRIEF
3.8.2 Block Description

The OMAP1510 device has the following features:
_Ability to support reduced instruction set computer (RISC) and DSP operating systems
TI925T MPU subsystem with:

Instruction cache (16K bytes) and data cache (8K bytes)
Memory management unit (MMU)
A 17-word write buffer (WB)
DSP subsystem (C55x••DSP core and subsystems) with:

Internal 32K-word dual-access RAM (DARAM), 48K-word single access RAM (SARAM), 16K-
word ROM
Software-configurable instruction cache (12K words, 128-bit line size, 2-way set-associative +
RAM set)
Hardware accelerators for video processing, pixel interpolation, and motion estimation
Six-channel DMA controller for high-speed data movement without DSP intervention
DSP MMU for address translation and access permission checks

System DMA controller with:
Six ports and nine independently programmable generic channels
An additional dedicated DMA channel tied to the liquid crystal display (LCD) controller
Ability to transfer 8-,16-, or 32-bit data between the external memory, the MPU, and peripherals
with byte alignment and packing capability
Ability to perform simultaneous transfers (single or multiple burst), if no resources conflict
Low-power design (no clocking when idle)
Two external memory interfaces, allowing glueless hookup to:

A 16-bit bus interface to external memory interface slow (EMIFS), such as
flash/SRAM/ROM/page-mode ROM/SB flash/DPRAM), with 128M bytes of memory space
A 16-bit bus interface to external memory interface fast (EMIFF), such as memory SDRAM, with
64M bytes of memory space
JTAG port for test, debug, and emulation

Clock management:
One digital phase-locked loop (DPLL) and three clock management units for MPU, DSP, and
traffic controller clock generation and management
System power management for idle mode and power-down functions
Peripherals available for the OS, general-purpose housekeeping, and application-

specific functions:
For the MPU:
Three 32-bit timers
A 16-bit watchdog timer
An interrupt handler
An LCD controller
Configuration registers
McBSP2 (multichannel buffered serial port)
Inter-integrated circuit (I2C) interface
MicroWire interface
Keyboard interface
Universal serial bus (USB) function and host interface
Camera interface
Five MPUIO general-purpose input/output signals in default multiplexing mode; five more
- 37 -
3. TECHNICAL BRIEF
available
through alternative pin multiplexing modes
32-kHz timer
Pulse-width tone (PWT) module
Pulse-width light (PWL) module
Real-time clock (RTC) module
Multimedia card (MMC), serial data (SD) card interface, or memory stick interface
HDQ and 1-Wire serial interface
Two light emitting diode (LED) pulse generator modules
Frame adjustment counter
For the DSP:

Three 32-bit timers
A 16-bit watchdog timer
An interrupt handler
McBSP1: Multichannel buffered serial port
McBSP3: Multichannel buffered serial port
MCSI1: Multichannel serial voice interface
MCSI2: Multichannel serial voice interface
Shared peripherals:
UART1: UART modem with autobaud (16C750 compatible)
UART2: UART modem with autobaud (16C750 compatible)
UART3: UART modem with IrDA (16C750 compatible)
Fourteen general-purpose input/output (GPIO)
Mailbox
3.8.3 External Device Description

Table 3-16. Helen External Memory
Interface SPEC
Device Name Maker Write Access Time Read Access Time
Flash1 TH50VPF5683DASB TOSHIBA 70ns 70ns
Flash2 TC58FVB641XB-70 TOSHIBA 70ns ` 70ns
SRAM TH50VPF5683DASB TOSHIBA 70ns 70ns
MIDI YMU762 YAMAHA
- 38 -
3. TECHNICAL BRIEF
3.8.4 GPIO Map

Helen has 8 ARMIO and 14 GPIO ports. Each port can be configured as input or output.
Table 3-17. GPIO Map Table
I/O # Application I/O Resource

State Inactive State Active State
I/O (0) USB_DETECT I USB LOW HIGH
I/O (1) CAMERA_POS_DET I GPIO LOW (Front) HIGH (Rear)
I/O (2) YMU762_IRQ I GPIO HIGH LOW
I/O (3) KEYPAD_LED_ON O GPIO LOW HIGH
I/O (4) MAIN_LCD_CD_SEL O GPIO LOW (Data) HIGH (Command)
I/O (5) Not Implemented On
Chip
I/O (6) HEL_FOLDER_DET I GPIO LOW (Close) HIGH (Open)
I/O (7) HEL_IND_LED_O O GPIO LOW HIGH
LOW HIGH
I/O (8) HSPEAKER_EN O GPIO ( 3.0V LDO OFF) ( 3.0V LDO On)
I/O (9) HEL_IND_LED_G O GPIO LOW HIGH
I/O (10) Not Implemented On
Chip
HIGH (UART3 is connected LOW (UART3 is connected
I/O (11) PC_IRDA_SEL O GPIO to Receptacle) to IrDA)
I/O (12) SUB_LCD_CD_SEL O GPIO LOW (Data) HIGH (Command)
I/O (13) HF_CALL_OFF_ON O GPIO LOW HIGH
I/O (14) EL_ONOFF O GPIO LOW HIGH
I/O (15) HEL_IND_LED_B O GPIO LOW HIGH
Table 3-18. ARMIO Map Table
Resource
I/O # Application I/O State Inactive State Active State
I/O (0) HEL_TX_MBOX O GPIO LOW HIGH
I/O (1) MAIN_LCD_RES O GPIO HIGH LOW
I/O (2) SUB_LCD_RES O GPIO HIGH LOW
I/O (3) YMU762_RST O GPIO HIGH LOW
I/O (4) MAIN_LCD_LED_ON O GPIO LOW HIGH
I/O (5) _HF_DET I GPIO LOW HIGH
I/O (6) STEREOJACK_DET I GPIO LOW HIGH
I/O (7) CAL_TX_MBOX I GPIO LOW HIGH
- 39 -
3. TECHNICAL BRIEF
3.8.5 Helen Power

There are 5 LDO (Low Drop Output) regulators and 1 DC-DC converter for Helen and Melody IC.
Fig. 3-20 shows the power supply related blocks for Helen and Melody IC. Table 3-19 shows the
output level of each power source.
VBAT 3 4.7uH
4
U808LTC1701BES5 P3 P4
5 1
D6 8 VIN SW P1 P2 HEL_CORE_1.5V
R843 R875
R842
1 2
20K
D5
1M
D4 7 L801
2 GND
D3 6 4 RUN VFB 3
5 S D2 3
R810
300K
MBRM120LT3
2.2K
D1 2 C851 C852
G
R844
100K
1 33u 47uF
D802
R811 4 NTHS5441T1
Q801 C853
C 0 330p
R821 B Q802
DTC144EE
10K VBAT
R878
12K
C888 E
0F
U812
NCP500SN18T1
1 5
VIN VOUT
2 GND LCD_1.8V
3 EN NC 4
C866
10u
VRIO
U813 U804
1A 5 1 5
2 BVCC 2 IN OUT HEL_IO_MEM_2.8V
R807 R808
200K 150K
ONNOFF_TO_BUF 3
GND
3 EN ADJ 4
GNDY 4 C831
TC7SZ08AFE MIC5219BM5
C829 C830
10u 470p 10u
U890
1 5
2 VDDVOUT HEL_PLL_1.5V
GND
3 CE NC 4 C900
10u
R1111N151B-TR
ONNOFF_BUF U809
1 5
IN
2 GND
OUT AVDD
R857 R855
270K 180K
3 4
SPEAKER_EN EN ADJ
C855
C856 MIC5219BM5 C858 10u
10u 470p
SPK_VDD
U810 LP3985IM5X-3.3
1 5
USB_PWR VIN VOUT USB_VDD
2
GND
100K 3 VEN BYPASS 4
C861
R869 C863 10u
0.01u
Figure 3-20. Helen Power sources
Table 3-19. Helen & MIDI LDO Output Level Table
Output Voltage Usage Enable Control

HEL_CORE_1.5V 1.5V Digital Core of Helen ON_nOFF
(from Nausica)
HEL_PLL_1.5V 1.5V DPLL of Helen ON_nOFF
LCD_1.8V 1.8V Main LCD Module ON_nOFF
HEL_IO_MEM_2.8V 2.8V IO pin of Helen and Melody IC ON_nOFF
ACDD or SPK_VDD 3.0V Audio analog switch, Speaker SPEAKER_EN
amp of Melody IC (Helen GPIO)
USB_VDD 3.3V USB module of Helen USB_PWR
(receptacle)
- 40 -
3. TECHNICAL BRIEF
3.8.6 Camera & Camera FPC Interface

The Camera module is connected to main board with 21-pin FPC connector (21FXL-RSM1-TB). Its
interface is dedicated camera interface port in Helen. The camera port supply 8MHz master clock to
camera module and receive 4MHz pixel clock, vertical sync signal, horizontal sync signal and 8bits
YUV data from camera module. The camera module is controlled by I2C port in Helen.
Table 3-20. Interface between Camera module and main board (in Camera Module)
PIN. SYMBOL FUNCTION I/O REMARKS

1 NC -
2 VDD_L 2.8V P
3 VDD_H 2.8V P
4 GND Ground P
5 SCL Serial Clock Signal for I2C -
6 XRST Reset Signal -
7 HSYNC Horizontal Sync Signal O
8 SDA Serial Data for I2C I
9 D6 YUV Data O
10 D7 YUV Data O
11 D4 YUV Data O
12 D5 YUV Data O
13 VSYNC Vertical Sync Signal O
14 D1 YUV Data O
15 D2 YUV Data O
16 DCK Pixel Clock Signal O
17 D0 YUV Data O
18 D3 YUV Data O
19 GND Ground P
20 CKIN Master Clock Signal I
21 NC -
3.8.7 Display & LCD FPC Interface

LCD module include devices in table 3-21.
Table 3-21. Devices in LCD Module
Device Type
Main LCD 176 x RGB 220 65K Color TFD LCD
Sub LCD 84 x 40 mono FTN LCD
Main LCD Backlight White LED
Sub LCD Backlight Deep Blue EL
- 41 -
3. TECHNICAL BRIEF
LCD module is connected to key board with 30-pin FPC connector (AXK830145J) and Speaker,
Receiver, Vibrator is connected by soldering the leads to 6 pads in LCD module.
The main LCD is controlled by McBSP2 Port(in SPI Mode) in Helen and the sub LCD is controlled by
uWire Port in Helen.
Table 3-22. Interface between LCD module and Speaker, Receiver, Vibrator

SPK TERMINAL
1 E- Ear Piece Minus O
2 S+ Loud Speaker Plus O
3 E+ Ear Piece Plus O
4 S- Loud Speaker Minus O
MOTER PAD TERNINAL
1 MB MOTOR Power O
2 MG MOTOR Ground O
- 42 -
3. TECHNICAL BRIEF
Table 3-23. Interface between LCD module and main board (in LCD Module)

1 Motor GND Ground P
2 Motor Batt MOTOR Power P
3 NC Not Connect -
4 NC Not Connect -
5 EAR PIECE+ Ear Piece Plus I Serial data transfer line
6 EAR PIECE- Ear Piece Minus I
7 LOUD SPK+ Loud Speaker Plus I
8 LOUD SPK- Loud Speaker Minus I
9 NC Not Connect -
10 NC Not Connect -
11 LED- LED cathode P
12 LED+ LED anode P
13 EN On/Off EL ON/OFF signal I
14 VDDL Power supply for internal logic (1.8V) P
15 VDD(VDDI) Power supply for system and I/O logic (2.8V) P
16 VDD(EL) Power supply for EL Driver (2.8V) P
17 GND(EL) Ground for EL & EL Driver P
18 GND(LCD) Ground for system P
19 SDA_S Sub Display data I
20 SCK_S Sub Serial Data clock -
21 RS(A0)_S Sub Serial Data command select signal I
22 XCS_S Sub Chip select signal I
23 XRES_S Sub Reset signal -
24 VDDL Power supply for internal logic (1.8V) P
25 SD0_M Main Serial data I
26 XWR_M Main Write signal I
27 A0_M Main Data command select signal I
28 XCS_M Main Chip select signal I I
29 XRES_M Main Reset signal I I
30 GND(LCD) Ground for system P
- 43 -
3. TECHNICAL BRIEF
3.8.8 Main LCD Backlight Illumination

There are 6 white LEDs in main LCD backlight circuit which are driven by ‘PWL_MAIN_LCD_BL’ line
from Calypso. PWL is used for backlight brightness control.
VBAT_2
C605
1u
R628
R629
100K
U602 SC600BIMSTR
R627 1 10
MAIN_LCD_LED+ VOUT CF2+
4.7
2 9
CF1+ CF1- C606
1u
3 8
C651 VIN GND
10u
4 7
FID0 CF2-
C612 5 6 R658 470
FID1 EN PWL_MAIN_LCD_BL
C676
1u
R647
100K
220p
Figure 3-21. Charge Pump Circuit for Main LCD Backlight
MAIN_LCD_LED+
GND
Figure 3-22. Main LCD Backlight Circuit
* R1, R2, R3 : 47ohm

* LED1, LED2, LED3 : NACW215T (Nichia)
- 44 -
3. TECHNICAL BRIEF
3.8.9 Sub LCD Backlight Illumination

A family of Deep blue EL is used for Sub LCD backlight and Citizen’s ELD-3410 is used for its driver.
GPIO_14(EL_ONOFF) in Helen does ON or OFF the ELD-3410 inverter, which include the inductor
in itself.
3.8.10 Indicator Illumination

Indicator LED illumination circuit can make 7 colors using multi-color LED. Multi-color LED consists
of orange LED, green LED and blue LED. GPIO_7 (HEL_IND_LED_O), GPIO_9 (HEL_IND_LED_G)
and GPIO_15 (HEL_IND_LED_B) in Helen do ON or OFF its own LEDs.
VBAT
R681
R682
10
10
3
3
1
1
LD603
LD602
LD601
LNJ717W80RA1
LNJ717W80RA1
LNJ717W80RA1
2
2
4
4
R626
R622
R601
150
33
56
R623
HEL_IND_LED_G
20K
6 5 4 6 5 4
VBAT
ONNOFF
R620
100
Q602 EMX1 EMX1

NC7SB3157P6X Q603 1 2 3 Q604 1 2 3
HEL_IND_LED_O 1 B1 S 6
2 GND VCC 5
R619
CHARGER 3 B0 A 4
R624 10K
10K
R661
R621
C666
2.7K
47K
0.1u
R625
HEL_IND_LED_B
20K
Figure 3-23. Indicator Illumination Circuit
In case of power off mode (ON_OFF=Low), if TA is inserted, NC7SB3157P6X multiplexer is

switched to charger and orange LED is turned-on. In other case (ON_OFF=High), Multi-color LED is
controlled by GPIO_7 (HEL_IND_LED_O), GPIO_9 (HEL_IND_LED_G) and GPIO_15
(HEL_IND_LED_B) in Helen
- 45 -
3. TECHNICAL BRIEF
3.8.11 Keypad Illumination

There are 16 Blue LEDs in key board backlight circuit, which are driven by ‘GPIO_3’ line from Helen.
GPIO_3 >>
R611
2.7K
R614
12
1 2 3
Q601
EMX18
R612
12
6 5 4
KEY_LED-
Figure 3-24. Keypad Backlight Control Circuit on Main Board
VBAT
LD13
LD14
LD15
LD10
LD11
LD12
LD16
LD3
LD1
LD2
LD4
LD5
LD6
LD7
LD8
LD9
C2
0.1u
R1
R2
R4
R3
39
39
39
39
KEY_LED-
Figure 3-25. Keypad Backlight Circuit
- 46 -
3. TECHNICAL BRIEF
3.8.12 Key pad

There are 26 key buttons and 3 side keys in Fig. 3-26 shows the Keypad Circuit .
Table 3-24. Key matrix mapping Table
KEY_ROW[4] KEY_ROW[3] KEY_ROW[2] KEY_ROW[1] KEY_ROW[0]

KEY_COL[0] Soft Option Navigate Clear Navigate•
KEY_COL[1] Function 3 Navigate OK Back
KEY_COL[2] Function 2 SEND Navigate Function 1
KEY_COL[3] # 9 3 6
KEY_COL[4] 0 8 5 2
KEY_COL[5] * 7 4 1
KEY_ROW4
KEY_ROW3
KEY_ROW2
KEY_ROW1
KEY_ROW0
V2.8
10K
10K
10K
10K
R8
R9
R7
2K
R6
R5
KB18 KB2 KB25 KB8 KB16
KEY_COL0

_END_ONOFF
KEY_COL1
KB21 KB6 KB9 KB14
KEY_COL2
KB4 KB5 KB19 KB7
KEY_COL3
KB17 KB10 KB22 KB3
KEY_COL4
KB26 KB15 KB11 KB12
KEY_COL5
Figure 3-23. Indicator Illumination Circuit
- 47 -
3. TECHNICAL BRIEF
3.8.13 Folder ON/OFF Detection

GPIO_6(HEL_FOLDER_DET) detects the folder ON or OFF.
V2.8
R11
HEL_FOLDER_DET
51K
C1
10p
A3212ELH 1
OUT 2
U1
VDD
C3
0.1u
GND
3
Figure 3-27. Folder ON/OFF Detection Circuit
3.8.14 Camera Position Detection

GPIO_1 detects the camera position (front or back).
HEL_IO_MEM_2.8V
R602
51K
R646 10K >>GPIO 1
A3212ELH 1
OUT 2
U601
VDD
SP42
R680
C602 10p
GND
3
0.1u C601
Figure 3-28. Camera Position Detection Circuit
- 48 -
3. TECHNICAL BRIEF
3.8.15 USB Interface

The universal serial bus (USB) function module supports the implementation of a full-speed device
fully compliant with the USB 1.1 standard. It provides an interface between the MPU core (TI925T)
and the USB wire and handles USB transactions with minimal TI925T intervention. The module
supports one control endpoint (EP0), up to 15 IN endpoints, and up to 15 OUT endpoints. The exact
endpoint configuration is software programmable.
The specific items of a configuration are for each endpoint, the size in bytes, the direction (IN, OUT),
the type (bulk/interrupt or ISO), and the associated number. The module also supports three DMA
channels for IN endpoints and three DMA channels for OUT endpoints for either bulk/interrupt or ISO
transactions.
Table 3-25. USB Signal Interface for Helen
UBS Funtion
UBS.DP UBS differential (+) line
UBS.DM UBS differential (-) line
UBS.PUEN UBS clock (6 MHz)
UBS.CLKO UBS pullup enable
UBS.VBUS UBS VBUS detect input
R1,R2 Value depends on transceiver

R3 1.5K Ohm+/-5%
R4,R5 Weak pulldown (optional, see text)
C1 Low ESR cap,minimum 120 uF
U1 Transient suppessor, such as SN65220, SN65240, or SN75240
Figure 3-29. USB W2FC Function Connection
- 49 -
3. TECHNICAL BRIEF
3.8.16 USB detect

USB is detected by Helen GPIO
HEL_IO_MEM_2.8V
Q809 UMC4N
R896
USB_DETECT
3
1K
USB_VDD
R802
100K
2
5
1
Figure 3-30. USB Detect Circuit
3.8.17 IrDA
This model supports SIR IrDA. Helen’s UART3 module support IrDA or UART. Uses both two mode.
During the normal operation, UART path is connected to IrDA. There is a Quad2:1 Mux to select
IrDA. If external connection by UART is needed, the quad 2:1 mux set the UART path to receptacle.
HEL_IO_MEM_2.8V
IrDA Transceiver
LEDA
1
U802SN74CBTLV3257DGVR
LEDK
16 2
VCC
1
PC_IRDA_SEL 15
S
2 3
TXD
_OE 1B1 SHIELD
5 8
2B1 RXD
4 11 4
HEL_UART_IRDA_TX 1A 3B1
14
4B1 SD
7 5
HEL_UART_IRDA_RX 2A
VCC
9 3 6
3A 1B2
6
HEL_UART_PC_TX
12
2B2
10
HEL_UART_PC_RX 7
GND
4A 3B2
4B2
13 signals To CIM-80S7B-T
8 U801
GND Receptacle
C801
0.47u
Figure 3-31. Helen UART3 IrDA Path
- 50 -
3. TECHNICAL BRIEF
3.8.18 Vibrator
Activating vibrator, Calyso makes ‘MOTOR_EN’ to High state (2,8V) and MOTOR_BATT outputs
High. And then, MOTOR_BATT signal connects with vibrator device and vibrator device is activated.
VBAT
R829
10
R827
47K
UMT2907A
Q805
R826
0
MOTOR_BATT
C
R825 B Q804
MOTOR_EN DTC144EE
C832
2K 0.1u
E
Figure 3-32. Vibrator Circuit
3.8.19 Hands Free Detect

Hands Free is detected by Helen GPIO.
HEL_IO_MEM_2.8V
R868
10K
4
HF_Detect_Signal_From_Receptacle
2
R801
100K
1
UMC4N
Q808
Figure 3-33. Handsfree Detect Circuit
- 51 -
3. TECHNICAL BRIEF
3.8.20 MELODY IC
HEL_IO_MEM_2.8V
U807 YMU762
11 1
HPOUT_R CLK1 4 HEL_CLK_12M_OUT
C848
10
_YMU762_RST
68n
_RST
HPOUT_L 30
R836 R835 C845 0.022u 12
A0
31
HEL_FADD(1)
Speaker_Output_From_Analog_Switch EQ1 _RD HEL_NFOE
29
8.2K 8.2K
13 _CS 5 HEL_NFCS_3
EQ2 NC R817
28
R837
C847 HEL_NFWE
82K
_WR 3
390p _IRQ _YMU762_IRQ
14 27 HEL_DATA[0]
HEL_DATA(0:15)
HEL_DATA(0:15)
EQ3 D0
2 26 HEL_DATA(1)
LED D1
19 25 HEL_DATA(2)
MTR D2 HEL_DATA(3)
24
D3
23 HEL_DATA(4)
R841 D4 HEL_DATA(5)
17 22
LOUD_SPKM SPOUT1 D5
21 HEL_DATA(6)
C850 0 D6
20 HEL_DATA(7)
47p D7
R840 R834 3.3K C844 1000p
LOUD_SPKP 18
SPOUT2 PLLC 6
SPK_VDD 0
C843 0.1u
VREF 9
15 SPVDD
R818 0
IOVDD 32
C846 C849
10u 0.1u VDD C828
7
0.1u
16
SPVSS VSS 8
Figure 3-34. Handsfree Detect Circuit
Table 3-25. Supply Volt. Table
Supply Voltage Usage Enable Control

HEL_IO_MEM_2.8V 2.8V Digital VDD of Melody IC ON_nOFF
(from Nausica)
SPK_VDD 3.0V Analog VDD of Melody IC ON_nOFF
- 52 -
4. Calibration S/W User Guide Ver 1.0
4. CALIBRATION S/W USER GUIDE VER 1.0
4.1 Introduction
This document describes the construction and the use of the Software used for the Calibration of
GSM/GPRS Multimedia Mobile. The Calibration menu and their results are displayed by a PC
terminal connected to the GSM/GPRS Multimedia Mobile.
This Calibration Software includes APC Calibration, AGC Calibration and *Flash File System
access (Read/Write) to apply Calibration results to the Phone. This Calibration Software is called
‘CALMON’. From now on, the Calibration Software will be called CALMON in this document.
4.2 CALMON Environment
4.2.1 H/W Environment

• PC with RS-232 Interface & GPIB card installed
• GSM/GPRS Mobile Set
• HP8960 Instrument
• Power Supply
• Etc (GPIB cable, Serial Cable, RF Cable, Power Cable)
4.2.2 S/W Environment

• National Instrument GPIB & Visa (2.60 full) Driver Install
• HP8960 Vxi driver
• CALMON Exe Files
• OS : Win98, Win2000 & WinXP
• Serial Port Configuration
(Baud rate : 115200 / Char length : 8bit / Parity : No / Bits stop : 1bit )
*Flash File System – Make a Flash the hierachy, organization and naming of files and directories.
FFS is used for storing many kinds of data and configuration parameters that should be non-volatile
across power-cycles. This includes RF calibration parameters(,and so on) adjusted and
programmed during Calibration and production test.
- 53 -
4.2.3 Configuration Diagram of Calibration Environment
PS2521G
HP8960
GPIB Cable
Power Cable
RF Cable
Serial Cable
NoteBook
Figure 4-1. Calibration Configuration
When you calibrate the Mobile, make a configuration of Calibration environment like Figure1.
For making the CALMON can control each instrument and Phone, Using GPIB cable, connect
Instrument and the PC (in fig.4-1,e.g. it’s notebook PC) and using Serial Cable, Make a connection
of the Phone and the PC, also. To supply the Phone with electricity, use Power cable from Power
supply.
When Rx Calibration (AGC) is run, connect HP8960 to the Phone’s antenna with RF cable. Thus,
CALMON can control the Instrument (HP8960) to run Rx Calibration with the Phone that received
the RF signal from the instrument controlled by CALMON.
When Tx Calibration (APC) is run, vice versa CALMON control the Phone’s operation so the
instrument receive the power signal through the RF cable and measure the signal to do the Tx
Calibration.
- 54 -
4.3 Calibration Explanation
4.3.1 Overview
In this section, it is explained calibration items in the CALMON. Also, the Explanation includes
technical information such as basic Formula of Calibration and settings for Key parameters in each
Calibration Procedure.
At first, when any of Calibration is done, the Results are displayed in the CALMON Result Window.
And in some case, as user’s choice the Result of Calibration will be stored in Flash File System for
non-volatile across power cycle.
Thus,for using Flash File System, Flash File System(From now on ‘FFS’) should be formatted
before anything else and should have hierarchy of directories in advance to be stored for calibrated
data after the Calibration is done.
Calibration Items of CALMON
• General Items
- APC Calibration
- AGC Calibration
• Item from Specific requirement
Flash File System Access
Battery Calibration
4.3.2 APC Calibration (*Auto Power Control )

APC Calibration is for adjusting voltage level that can make the wanted level output in antenna and
adjusting Ramping shape at assigned level to be able to remain in Spec. Mask. So, there are two
steps for APC calibration.
- APC DAC Calibration for each Power Index (using a Standard Channel)
- Ramp coefficients calibration for each Power Index.. (using a Standard Channel)
- APC DAC calibration for each defined Channel. (using Standard Power Level)
# Standard Channel for EGSM (channel 40) / Standard Channel for DCS (channel 700)
*Actually this is not “Automatic”, but “Pre-defined” level according to each boards.
We need to find out what voltage level can make the wanted level output in antenna.(We need to
know the DAC value for each power level in the point of layer1 software.)
- 55 -
4.3.2.1 APC DAC Calibration for each power index

The TX power levels needs to be calibrated in order to achieve the required accuracy
To calibrate the TX power levels the following steps have to be performed for both bands :
1. Setup the mobile to transmit on the channel specified in Table 4.1.
2. Setup up the power level that needs to be calibrated.
3. Calibrate the power level according to Table 4.1.
4. If output power is higher than specified in Table 4.1. then decrease the APC level.
5. If output power is lower than specified in Table 4.1. then increase the APC level.
6. Proceed with the steps above until all power levels both bands have been calibrated.
Table 4-1 EGSM900 and GSM1800 Power level settings
Power level EGSM900 @ channel 40 [dBm] GSM1800 @ channel 700 [dBm]

0 - 30
1 - 28
2 - 26
3 - 24
4 - 22
5 33 20
6 31 18
7 29 16
8 27 14
9 25 12
10 23 10
11 21 8
12 19 6
13 17 4
14 15 2
15 13 0
16 11 -
17 9 -
18 7 -
19 5 -
- 56 -
4.3.2.2 Ramp Up/Down Calibration for each Power Index

Ramp Up/Down Calibration is to adjust Ramp Template Up/Down Coefficients for Ramping shape
at assigned level to remain in Spec. Mask for defined Power Levels of both band.
There are 16 Indexes for both Up and Down Ramp Template. Each Ramp Template has 31
Coefficients (0 to 30), The Important thing of Ramp Up/Down Calibration is maintenance of Sum of
indexes’ coefficients, Up and Down separately. The sum has to be 128 exactly.
So, Special Consideration needs to maintain specific sum value ‘128’ and to make Ramping shape
in Spec.Mask at the same time.
4.3.2.3 APC DAC Calibration for Each Channel

When APC DAC Calibration is done for each Power Index, APC DAC for predefined channels
should be calibrated for both GSM and DCS to make each Channel have Wanted Transmit Power.
Standard Power Level Indexs for each band are for GSM Index is 10, for DCS Index is 5. So, At first
get the APC DAC Calibrated Value at Standard Power Level Index and based on this calibrated
value from Standard Power Level, do the calibration for each Channel in Table 4.2. In this case,
Default Channel Calibration Value is set to 128. After Channel Calibration, If output power is higher
than specified value then decrease Channel Calibration Value at lower than 128. If output power is
lower than specified value then increase Channel Calibration Value at higher than 128
Table 4.2 Specified Arfcn Limits and Test Arfcns for Apc Channel calibration
Arfcn Limit for Apc Channel Test Arfcn For Apc Channel
Calibration Calibration
EGSM900 20, 40, 62, 80, 100, 124, 992, 1023 10, 30, 51, 71, 90, 112, 983, 1007
DCS1800 558, 604, 650, 696, 742, 788, 834, 885 535, 581, 627, 673, 719, 765, 811, 857
4.3.3 AGC Calibration

The AGC block generates automatic gain control from the digital baseband signal and then feeds it
to the analog IF variable gain amplifier (VGA) to maintain a constant, in-band signal and interference
power for the A/D converters. Adjusting G_magic, make Power level received by Mobile equal to
calculated power level by itself.
- G_magic Calibration for Both Band (GSM, DCS)
4.3.3.1 G_magic Calibration

To calibrate GMagic the following steps have to be performed for both bands:
1. Setup the mobile to receive on the ARFCN specified in Table 4.3.
2. Set the AGC in the receiver to the gain specified in Table 4.3.
3. Set the generator level to TL specified in Table 4.3.
4. Write *INI_AFC value to MS
5. Set Test frequency as specified in 0 plus 67Khz.
6. Measure PM1.
7. Set Test frequency as specified in 0 minus 67Khz.
8. Measure PM2.
9. Calculate PMAV = (PM1 +PM2 )/2.
*INI_AFC value can be obtained by performing the VCTCXO Calibration procedure, if that hasn’t
already been done.
- 57 -
10. Calculate GMagic = (PMAV – AGC – TL)x2.

TL is the test signal level in dBm
PMAV is an average over the two power measurements by the DSP
AGC is the IF gain in dB
11.Download GMagic to MS.
* Note : Instead of step 5 to 8 you could also test only at the ARFCN center frequency modulated by
a pseudo–random bit sequence (PRBS).
Table 2.3 Test settings for calibrating GMagic
Receive Band Test ARFCN AGC setting [dB] TL [dBm] Test frequency [MHz]
EGSM900 40 34 ˜ -74.5 943.0
GSM1800 700 34 -74.5 1842.8
4.3.4 Flash File System

Flash File System (FFS) is used for storing many kinds of data and configuration parameters that
should be non-volatile across power-cycles. This includes RF calibration parameters and System
Configuration, Production Adjustment, Test Data, User/MMI Data — Volume, SMS, Melodies, etc -
adjusted and programmed during Calibration and production test.
Flash File System is consist of the Hierarchy of directories and files. These are lists of directories
and files using in CALMON. Mosts are for RF Calibration parameters.
/gsm/rf/ 4 GSM RF calibration and configuration.

/gsm/rf/afcdac Initial AFC DAC value.
/gsm/rf/afcparams AFC parameters
/gsm/rf/tx/ramps.900 RF Transmitter PA ramps for GSM/EGSM
/gsm/rf/tx/ramps.1800 RF Transmitter PA ramps for DCS
/gsm/rf/tx/levels.900 RF Transmitter levels table for GSM/EGSM
/gsm/rf/tx/levels.1800 RF Transmitter levels table for DCS
/gsm/rf/tx/calchan.900 RF Transmitter channel calibration for GSM/EGSM
/gsm/rf/tx/calchan.1800 RF Transmitter channel calibration for DCS
/gsm/rf/tx/caltemp.900 RF Transmitter temperature calibration for GSM/EGSM
/gsm/rf/tx/caltemp.1800 RF Transmitter temperature calibration for DCS
/gsm/rf/rx/agcglobals RF Receiver AGC global parameters
/gsm/rf/rx/agcwords RF Receiver AGC gain programming words table
/gsm/rf/rx/il2agc RF Receiver AGC il2agc tables
/gsm/rf/rx/calchan.900 RF Receiver channel calibration for GSM/EGSM
- 58 -
/gsm/rf/rx/calchan.1800 RF Receiver channel calibration for DCS

/gsm/rf/rx/caltemp.900 RF Receiver temperature calibration for GSM/EGSM
/gsm/rf/rx/caltemp.1800 RF Receiver temperature calibration for DCS
/gsm/rf/rx/agcparams.900 RF Receiver AGC parameters for GSM/EGSM
/gsm/rf/rx/agcparams.1800 RF Receiver AGC parameters for DCS
So, this is a Flash File System structure.

And Flash File System Access is for Accessing to Read and Write Control through the Flash.
*This directory contains RF calibration data and tables adjusted during production. It also contains
files that are only used during development for overriding compiled-in default data and parameters
for the RF.
4.3.5 Battery Calibration

The battery sensor uses the baseband ADC to read the battery voltage (Vbat), and the ADC internal
reference voltage is the largest contributor to measurement inaccuracy. Measuring the ADC slope
and offset makes it possible to correct this in the SW.
To calibrate the Battery Voltage the following steps have to be performed :
1. Set the Power supply Voltage to 4.2V specified in Table 4.4.
2. Read ADC value and Compare whether Adc value is in between Lower Limit and Upper Limit.
3. if it is, Save it to FactorySettingData.cc2cv_Voltage value.
4. Set the Power supply Voltage to 3.35V specified in Table 4.4.
5. Read ADC value and Compare whether Adc value is in between Lower Limit and Upper Limit.
6. if it is, Save it to FactorySettingData.shutdown_Voltage value.
7. Proceed with the steps above until two Voltage levels have been calibrated.
Table 4.4 Battery Calibration Settings
Voltage Level Lower Limit Upper Limit

4.2V (cc2cv_Voltage) 0x250 0x290
3.35V (Shutdown_Voltage) 0x1d0 0x210
- 59 -
4.4 Program Operation
4.4.1 APC DAC Calibration
Figure 4-2. APC DAC Calibration Basic Settings Window
• Basic Setting
Target Control
- Band : You can select Band either GSM900 (EGSM) or DCS1800. If change
the band, Arfcn will be changed automatically by the available value of selected Band.
- TCH : You can read current Target’s Tch Arfcn.
- Tx Power Level : You can change the Tx Power level of Target.
Usually APC Level and Ramp template Index are followed accordingly by the value of Tx
Power Level.but, You can also change these parameters’ value.
- Update all values : You can read all values of current Window’s parameter from the Target
Instrument Control
- Tx Power Level : You can change the Tx Power level of Instrument
- Cable Loss : Compensate the Cable Loss through the RF Cable
- 60 -
4.4.1.1 APC Measurement Window
Figure 4-3. APC Measurement Window
Fig4-3 is a APC Measurement Window.

In the Fig 4-3, it’s the measurement of Tx Power Level 5
• Tx Power Measurement
When click the ① Meas.start, measure the Target’s Tx Power read from the instrument by the
value of current selection of Power Level. And the value measured from the instrument is
compared with the Expected power pre-defined by the specification. So, decide whether this
compared value is in allowable Margin from specification or not. If it is, then fill Mask Test item
green and write ‘Pass’ (②). If not, it will be filled red and written ‘Fail’. Statistics for Measured
MS tx Power : it shows measured Tx Power Value. And in addition, Avg., Min / Max, Difference
between Expected Power and Measured power, Variance from Avg. etc statistical results are
displayed. ④ When you do the Measurement, you can select whether you consider Cable loss or
not. ⑤ Measured margin : to check how much margin measured power have from upper and
lower limit specified.
- 61 -
4.4.1.2 APC DAC Calibration Window
Figure 4-4. APC DAC Calibration Window
• APC DAC Calibration

APC Calibration is adjusting APC DAC that can make the wanted level output in antenna.
Standard Channel for EGSM is Traffic channel 40 and for DCS is Traffic channel 700.
Each band has different range of Power Level for Calibration. 5 to 19 for EGSM. 0 to 15 for DCS.
When click ① CAL Start, APC DAC Calibration starts, It’s working Automatically through the
levels pre-defined from the EGSM900 to the DCS1800 band.
You can just check the APC DAC Result shown from the ③ List Box and if you have more time to
check, compare the ④ Tx power by this calibrated APC DAC with ⑤ Tx Power specified and
check the accuracy of APC DAC Calibration. Or see the Progress bar is running to the 100%
end.
② Processing time is the time taken during the entire APC DAC Calibration Procedure. After all
Procedure has done, the Calibrated data has to be stored in Flash File System . Fortunately, it’s
stored automatically in flash after APC DAC Calibration is completed.
- 62 -
4.4.1.3 APC Ramp Calibration Window
Figure 4-5. APC Ramp Calibration Window
• APC Ramp Calibration

APC Ramp Calibration is for both GSM and DCS band, to adjust Ramp Template Up/Down
Coefficients for Ramping shape at assigned level can remain in Spec.Mask per each Power
Level. As you see the Red Box in the Fig 4-5, there are 16 Indexes for both Up and Down Ramp
Template each. And each Ramp Template Index has its coefficients, 31 Coefficients (0 to 30).
You can change each coefficient value, but the sum of all coefficients has to be 128.
In this Window the upper part of Figure, there is basic setting menu for parameters. But that’s
similar to APC DAC Calibration.so, section 4.1 will help you.
When click the ① Meas.start, the window will show you the ③ avg. Tx Power of current Power
Level and the plot for ② Ramping Shape from current Ramp Index’s Coefficients’ values.
They are from the instrument. And you can change the visual part of the graph as Full or Rising
edge,etc.④
- 63 -
4.4.1.4 APC Channel Calibration
Figure 4.6. APC Channel Calibration
When APC DAC Calibration is done for each Power Index, APC DAC for predefined
channels should be calibrated for both GSM and DCS to make each Channel have Wanted
Transmit Power. Standard Power Level Indexs for each band are for GSM Index is 10, for
DCS Index is 5. So, At first get the APC DAC Calibrated Value at Standard Power Level
Index and based on this calibrated value from Standard Power Level, do the calibration for
each Channel predefined in Table 4.2. In this case, Default Channel Calibration Value is set
to 128. After Channel Calibration, If output power is higher than specified value then
decrease Channel Calibration Value at lower than 128.
When click the ① Chan Cal start, it will start to run automatically from EGSM900 to
DCS1800 Band for each Arfcn predefined. So, ② Whole Results will shown in List Box. ③
is APC DAC of Standard Channel , ④ is Calibration results for each channel, APC’s
Compensated Value for each Channel.
- 64 -
4.4.2 AGC Calibration Window
Figure 4-7 AGC Calibration Parameters Control Window
• Basic Setting
Target Control
- AFC Settings : Read ① INI_AFC DAC value from the Target.and also you can write another
value you want to change. But when you try to do AGC Calibration precisely,
you should set the Calibrated INI_AFC value to the Target.
- AGC gain : ② Set the AGC gain Value to 34dB. It’s calculated based on the IL
(Input Level = -74.5) from the Target.
- AGC Algorithm : ③ To get the AGC G-Magic, Disable the AGC algorithm from L1.-
AGC Parameters : ④ ⑤ G-Magic Value will be updated automatically after the AGC Calibration is
complete. And the other AGC Parameters (LNA ~)will have appropriate value
from the definition.
- Measurement setup : ⑥ You can choose the option to see the result you want.
You can choose any of three selection (RSSI,DSP-PM and G-Magic)
and also you can choose multiple selection. And the results will be
displayed as you chose. The results will be updated moment by
moment.
Miscellaneous Control
- Cable Loss : ⑦ Compensation for loss from RF cable between the instrument and the
Tartget.You can set the value per Band. (It is defined at the every Cable)
- 65 -
4.4.2.1 AGC Calibration Measurement Window
Figure 4-8. AGC Calibration Measurement Window
• AGC Calibration Measurement

After the Basic Setting from Fig 4-6, based on the set value of AGC Calibration Parameters from
current window, CALMON (CALMON’s AGC Calibration Measurement Menu) does AGC
Measurement and displays the result. Measurement result that you already chose (⑥ from fig 4-
6) will be displayed. Figuring out from fig4-7, all of measurement options are chosen. RSSI,
DSP-PM, G-Magic results are shown. When you click the ① AGC Measurement, Measurement
start. And if you click again, it will stop. ② DSP-PM from target ③ PM mean from received PM
values. ④ RSSI, ⑤ difference between the very first Power Level from instrument transmits and
actually received Power Level that target received. only when you choose the ⑤ Îth option, you
can also check the Cable Loss consideration ⑦. ⑥ Calculated G-Magic.
- 66 -
4.4.2.2 AGC Calibration Window
Figure 4-9. AGC Calibration Window
• AGC Calibraiton
AGC calibration is for Adjusting G_magic, make Power level received by Mobile equal to
calculated power level by itself. So, you have to find out proper value of G-Magic. When you click
the
① AGC Calibration, it will start. It’s programmed to run automatically from EGSM900 to DCS1800
Band. So, after AGC Calibration, you can get the calibrated G-Magic ③ for each Band. During
the AGC Calibration, when calculate the G-Magic, DSP-PM accumulated value is used in
Program internally. So, here is selective option for the ④ count of DSP-PM accumulation. Current
Count is 10. When AGC Calibration is done, calibrated G-Magic has to be non-volatile to be
applied permanently for the Target’s Performance. So, Calibrated G-Magic value has to be
stored in Flash RF part. ⑤ you can choose this storing option. And also you can save the
calibrated data to file and load calibrated data from file. Just click the ② Save Config button or
Load Config button. Feel free to choose the File name to save or load and directory in the dialog
window.
- 67 -
4.4.3 Flash File Window•
Figure 4-10. Flash File Window
It is intended to access Flash more simply like we access and control PC files at personal
computer. ① when you click the Select File utton, following window will come.(Figure 4-9) Using
this window, you can load Flash File Data to file of PC or load the Flash file data from
PC file without difficulty. ② The content of the Red Box is the selected flash file. There are more
files’ list in fig 4-12.
Once you selet the file you want, you can read (④) or write (③)the contents of flash file data on the
ListBox (⑤), you can see the contents of /gsm/rf/tx/levels.900 file in figure 4-10.
- 68 -
Figure 4-11. Select File Save or Backup or Restore
There is a caution for you to use Flash File System.

The hierarchy of directories and files is not configured in the beginning. Flash is like blank space at
first. But downloading the Boot source and Application source, Flash has its own blueprint for the
advanced operation. First, you should do Format the Flash before using Flash File System like you
format the Floppy diskette before you use. And second, make the hierarchy of directory as Fig 4-12.
- 69 -
Figure 4.12. ‘’Diretory/directory/File” Window from Flash File System
Although you do not format flash and make any directory in it, you will access flash nevertheless.
Then following message window will come up. This window will ask you would want to format
flash and create directories in flash. You can make complete both just clicking ‘OK’ button.
Figure 4.13. Flash File Open Error Window
- 70 -
4.4.4 Battery Calibration Window.
Figure 4.14. Battery Calibration Window
If you want to measurement ADC value, first You should choose the Voltage. When you chose it,
CALMON would set the power supply voltage to the value that you’ve chosen. And
FactorySettingData.cc2cv_voltage means the value reading ADC register from Target after setting
the target’s Vbat to 4.2V. and in additiions, between Upper and Lower Limit, CALMON compare
the value with the Limits and notify it as you see the Mask Test ‘Pass’( or ‘Fai l ’). If you want
Calibration of AD, then click the Cal.stop, CALMON will do Battery Calibration for both Voltage
Level one by one.
- 71 -
5. DOWNLOAD
5. DOWNLOAD
5.1 Download Setup
5.1.1 Download Equipment

1) Data Kit
2) Desktop or Notebook PC
3) Download tools
4) Mobile phones of this model
5.2 Download Procedure
5.2.1 General Purpose

This document gives a guideline for upgrading software of this model using UART or USB port.
5.2.2 Download Environment

This model has two micro-processor, i.e., Calypso and Helen. In order to download or upgrade
Target SW* of each processor, the following working environments should be prepared:
- The model’s Data Link Kit is connected to COM1, COM2 or USB serial port in the Desktop or
Notebook PC.
- Download tools that are copied to Desktop PC or Notebook PC.
• X-monitor : Download tool for Calypso software.
• FlashRW : Download tool for Helen software.
- Target SW* downloaded to mobile phones of this model.
Warning
You must use the Data Link Kit and Download tools for each processor that are provided from the
manufacturer. Otherwise downloading process won’t properly
Note: Target SW* means any necessary software to be downloaded to the mobile phone.
5.2.3 Download Procedure for Calypso Software

A. Unzip download tool for calypso processor (x-monitor.zip) in PC.
B. Execute x-monitor.exe. And then select the “Target ” Menu shown in Figure 5-1. Then, choose
“Connect” in the Target Menu.
- 72 -
5. DOWNLOAD
Figure. 5-1
C. A table will be displayed as shown in Figure 5-2. Then press the arrow-button and choose a
correct serial port. And press “OK” button.
Figure. 5-2
D. As the following window shown in Figure 5-3. is displayed, connect the phone to Data Link Kit and
power on it. If the connection is succeeded, the following screen will show the contents as shown
in Figure 5-4.
- 73 -
5. DOWNLOAD
Figure. 5-3
Figure. 5-4
E. Click on “Flash” on the top menu and select “Get type” item as shown in Figure 5-4. and select
“Erase and Program Appli Only+Boot” item as shown in Figure 5-5.
- 74 -
5. DOWNLOAD
Figure. 5-5
F. Finally choose the target SW that you want to download. And then you can see the following
window in Figure 5-6.
Figure. 5-6
G. If the downloading procedure is succeeded, and then the following window is shown.
- 75 -
5. DOWNLOAD
Figure. 5-7
5.2.3 Download Procedure for Helen Software

A. Executable used to load the software on Helen is FlashRW.exe. It is available in FlashRW.zip.
Create directory and then unzip all files in FlashRW.zip into the directory.
B. Start FlashRW application, FlashRW opens a RS232 port automatically at startup.
FlashRW supports an USB port also. To change the attribute of serial port, click serial port
configuration button and change your serial options in following screen.
Figure. 5-8
- 76 -
5. DOWNLOAD
[ In the case of using RS232 port ]

C. Following screen will be displayed if there is no error to open RS232 port in PC. Default serial
configurations are 115200-8-N-1.
Figure. 5-9
- 77 -
5. DOWNLOAD
D. Connect G8000 phone to data link kit and power on G8000 after click “connect” button. If the
connection is succeeded, the following screen will be displayed in the log window as shown in
figure 5-9.
Figure. 5-10
- 78 -
5. DOWNLOAD
[ In the case of using RS232 port ]

Note: Please make sure that LG-USB driver is installed correctly in PC.
C. Contrary to RS232 mode, FlashRW in USB mode is waiting for a target detection automatically
when FlashRW is startup or click the connect button like as following screen. Please make sure
that data link kit is unplugged at this step.
Figure. 5-11
- 79 -
5. DOWNLOAD
D. Connect G8000 phone to data link kit and press power key until target flash writer code
isprogrammed successfully or target work manager identified correctly. If the connection is
succeeded, the following screen will be displayed in the log window as shown in figure 5-9.
Figure. 5-12
- 80 -
5. DOWNLOAD
E. Before the download, please make sure that each files are selected correctly. In order to choose
the target SW that you want to download, click each “File Select” button indicate in Fig 5-9. A
dialog open to select m0 or cp64 extension file. In case of choosing m0 extension file, this one is
compressed in a cp64 extension file.
F. Select your TargetSW using check box.
G. Click download button. Once load is finished, informations regarding loaded file are displayed like
as follow.
Figure. 5-13
- 81 -
5. DOWNLOAD
5.3 USB Driver Installation / Removal
5.3.1 Objective
This document is for installation of USB host driver when using FlashRW USB version.
It’s for Windows 2000. You never install this driver on Windows 98, Me OS. This can lead to a Blue
Screen.
5.3.2 Windows Driver Installation

* Windows Driver Installation with Care
Only one driver relative to the USB device should be installed
First of all, delete data about previous driver file or installation file in Registry and WinNT system
relative Folder. (Refer to the Removal of Driver)
- Put “ram_flashwriter_usb_v100.m0” into a flash writer code Select opening in FlashRW tool. (Refer
to the FlashRW manual in detail)
- Download FlashRW ver2.2.1 and change Serial Port Configuration from COM port to USB before
you install USB driver. Insert USB cable to PC or Notebook and cell phone. Power on the phone
then you can see the picture 1 below.
- For instance, here we install LG03_KJHusb.sys and LG_G8000_usb04.inf.
1) Copy those files into a temporary folder.
*.inf file is for installation and *.sys for driver.
2) First of all, You can use “Add new hardware” from control panel or Plug and Play function to install
the driver.
- 82 -
5. DOWNLOAD
Proceed after Picture 1.

1) Be careful the new hardware installation pop-up magic tool beforepower on the cell phone. Just
cancel it.
Figure. 5-14
2) Select “No, Select new hardware from the item”.
Figure. 5-15
- 83 -
5. DOWNLOAD
.
3) Select other device from Picture 3. This is recommended.
Figure. 5-16
4 ) Click “Select from Disk” and select LG_G8000_usb04.inf file from the folder you made.
Figure. 5-17
5) How to check whether the driver file is installed properly or not:

Go and check if G8000_usb is a new device from the control panel.
- 84 -
5. DOWNLOAD
5.3.3 Windows Driver Removal

How to remove driver information registered on Registry :
Use lg_02Cusb.sys on this document for example.
1) Let the Registry window pop on with regedt32 keyword input.
Figure. 5-18
- 85 -
5. DOWNLOAD
2) Delete the contents in the 3 folders within the square box from the picture2.
Figure. 5-19
3) Picture3 shows the contents to be deleted from the folders. Refer to the Vid and Pid in order to
delete the folders relative to the device. Vid is Vendor ID and Pid is Product ID. Only administrator
is authorized to edit registry in Windows 2000. If you see the message which tells no authority to
you, then click Security (blue colored circle in the picture 3) from the menu and terminate it.
- 86 -
5. DOWNLOAD
Figure. 5-20
Figure. 5-21
- 87 -
5. DOWNLOAD
5 ) Delete LG03_usb folder from the folders in the Service. If you delete the contents within the
Services, then you do not need to give any authority.
Figure. 5-22
6 ) Repeat from 3) to 5) for the (Controlset001, Controlser002, Currentcontrolset) folders.

Warning! Do not really care whether there are all the folders we refer here or not.
7 ) Delete *.sys file relative to the USB in the WINNT\System and drivers folders.
8 ) Delete *.inf, .pnf files relative to the USB in the WINNT\inf folder. (Mostly oem.inf/pnf files)
- 88 -
6. TROUBLE SHOOTING
6. TROUBLE SHOOTING
Figure. 6-1 shows a measurement set-up.
Figure 6-1. Measurement set-up
- 89 -
6. TROUBLE SHOOTING
TOP & BOTTOM
SW101
N101 U101
FL103
FL101
U102
D101
Fig 6-2
FL101
FL104
U105
FL105
Fig 6-3
- 90 -
6. TROUBLE SHOOTING
6.1 Rx Trouble (EGSM)
FL103 : Antenna S/W

FL105 : Rx SAW Filter
Set up Test with CalMon FL101 : Dual VCO
(62CH, Sector Power-60dB, AGC 24dB FL102 : Balun
U105 : RF Main Chip
(High Frequency Probe)
FL103 pin 2 RF signal NO

@ 947.4MHz Check FL103 or Peripheral circuit
is over -63dBm
YES
@ 947.4MHz FL105 pin 4, 6 RF signal NO

Check FL105 or Peripheral circuit
is over -66dBm
YES
FL101 pin 3 LO signal NO

is over -23dBm
YES
FL102 pin 5, 7 LO signal NO

is over -26dBm
YES
Sector Power -85dBm NO

U105 18, 19, 20, 21 Check U105
I/Q signal is over 60mV
(Oscilloscope)
R501, R502, R505, R506 NO Check R501, R502, R505, R506

I/Q signal is over 60mV or Peripheral circuit
YES
Rework Calibration
(Over G_MAGIC 170)
- 91 -
6. TROUBLE SHOOTING
6.2 Rx Trouble (DCS)
FL103 : Antenna S/W

FL105 : Rx SAW Filter
Setup Test with CalMon FL101 : Dual VCO
(700CH, Sector Power -60dBm, AGC 24dB) FL102 : Balun
U105 : RF Main Chip
(High Frequency Probe)
NO
@ 1842.8MHz FL103 pin 6 RF signal Check FL103 or Peripheral circuit
is over -63dBm
YES
FL104 pin 4, 6 RF signal NO

is over -63dBm
YES
FL101 pin 4 LO signal NO

is over -23dBm
YES FL102
FL102 pin 5, 7 LO signal NO

is over -26dBm
YES
Sector Power -85dBm

NO
U105 pin 18, 19, 20, 21 Check U105
I/Q signal is over 60mV
(Oscilloscope)
YES
R501, R502, R505, R506 NO Check R501, R502, R505, R506

I/Q signal is over 60mV or Peripheral circuit
YES
Rework Calibration
(Over G_MAGIC 170)
- 92 -
6. TROUBLE SHOOTING
6.3 Tx Trouble
U503 : CALYPSO N101 : Directional coupler

(BB Digital Main Chip) (LCD15D190A0007A)
Setup Test with CalMon U501 : NAUSICA_CS D101 : Shottky Diode
GSM:1CH, DAC value 600 (BB Analog Main Chip) (BAT 15-05W)
DCS:512CH, DAC value 700 U101 : PAM (PF08122B) D103 : Dual VaractorDiode
Power Level: GSM 5, DCS 0 U105 : RF Main Chip (TRF6150) (SMV1233-074)
Test DC Voltage : 4.0 V FL101 : Dual VCO (ENFVF382S18) D102 : Varactor Diode
FL103 : Antenna S/W (HVC369B)
(SHS-M090B)
NO
Check all VCC level of U105 Check or change U503 or U501
Are they all O.K? and peripheral circuit
YES
Check CLK, DATA, EN(pin 11, 12, 13) of NO Check or change U503 and
U105 Are the signals similar to Fig 7-13. peripheral circuit
YES
Check theTx IQ Signal level NO Check or change U501 and

of U105 (pin18~21) (R501,502,505,506). peripheral circuit
Is it the same as Fig 7-15.
YES
Check Aux VCO RF Signal NO

(pin 23 or 24) of U105. Can you observe RF Check or change U105, D103 and
Signal(GSM : 858, DCS: 832MHz)? peripheral circuit
YES
Check Main VCO RF Signal NO

(pin 35) of U105. Can you observe RF Signal? Check or change U105, D102 and
(GSM : 1319.2MHz, DCS : 1294.2MHz) peripheral circuit
YES
NO Check or change U105 and

Check the voltage level of U105 (pin59)
and FL101 (pin 9). Is it similar to peripheral circuit between U105
Fig.(GSM), Fig.(DCS)? (pin 59) and FL101 (pin 9)
Truth Table GSM DCS

YES
TXRXSW
Low Low
pin 12
NO HBSW
Check the switch pins of FL101 High Low
Check or change U105 pin 11
pin(10, 11, 12). Are they the same as the
(pin1, 2, 64) LBSW
truth table? Low High
pin 10
YES
- 93 -
6. TROUBLE SHOOTING
Is the Modulated RF signal of FL101 NO Check or change FL101 and

(GSM:pin1, DCS pin6) over 3dBm? (GSM
peripheral circuit
890.2MHz, DCS 1710.2MHz)
YES
Is the Modulated RF signal of U101 Check or change peripheral circuit

NO between output pins of FL101 and
(GSM:pin1, DCS pin8) over -2dBm? (GSM
890.2MHz, DCS 1710.2MHz) input pins of U101
YES
YES
Is the amplified RF signal of U101 NO Is the output voltage level of
(GSM:pin4, DCS:pin5) over 27dBm? (pin 48) over 1.5V?
NO
YES
NO
Is the PA_ON signal level of U105
( pin 9) high( about 2.8V)?
YES
Is the input voltage level of NO

Is the PA_Level signal voltage of U105 NO U101(pin 2) over 1.5V?
(pin 8) over 1.2V (GSM), 1.5V (DCS) ?
YES YES
Is the input power of FL103
(GSM:pin10, DCS:pin8) over 25dBm?
NO
YES
Check or change peripheral

Check calibration Check or change
Change Change Change Change circuit between
calibration D101 and
U105 U503 U501 U101 U105 (pin 48)
change FL103 peripheral circuit.
and U101(pin 2)
- 94 -
6. TROUBLE SHOOTING
6.4 Voice Function Trouble
A. Receiver
START
Connect the phone to network

Equipment and setup call.
Setup 1KHz tone out.
No
Does sine wave apper Change the Main B'D
at C523?
Yes
Does sine wave apper No

at number 3 pin in key B'd CN2 Change the Key B'D
Yes
Receiver Sodering No
Resoldering Receiver
OK?
Yes
Change the FPCB
B. Speaker
START

Equipment and setup call.
Setup 1KHz tone out.
No
Does sine wave apper Change the Main Board
at R814?
Yes
Yes
No U809
Does sine wave apper Regulator output=3.0volt? Change the Key Board
at C850?
Yes
Yes
Resoldering or Change U810
Does sine wave apper No

at number 4 pin in key B'd CN2 Change the Key B'd
Yes
No
Receiver Sodering Resoldering
OK?
Yes
Change the FPCB
- 95 -
6. TROUBLE SHOOTING
C. Microphone
START
Yes

and setup call.
Yes
Check the MIC bias level

at pad of MIC+
Yes
Is the level of MIC+ =2.0V, No

Rwsoldering of R815, R849, R848
MIC- =0.3v ?
Yes
Cheak the signal level

at C809, C815 after putting
audio signal in MIC
Yes
A fwe hundred of mV No
of sivgnal are measured? Resoldering of C809, C814, C817
and Reass the phone
Yes
Change the MIC
- 96 -
6. TROUBLE SHOOTING
6.5 Display Function Trouble
A. LCD
START
No
Is power supplied to Refer to power-on trouble
circuit ?
Yes
Check the connection between

LCD module and FPCb.
Check the connection between
FPCB and main board
No Reconnect FPCB
Connection OK ?
or LCD module
Yes
Check the data line at the

LCD connector
Does data appear No Resoldering

on the data line ? LCD connector
Yes
Change LCD module
- 97 -
6. TROUBLE SHOOTING
B. Camera
START
Check the connection of

the Camera module and
Main Board
No
Coonection OK ? Reconnect camera module
Yes
Check the signal lines at

the Camera connector
Do signals appear No
Change Camera module
on the data line ?
Yes
Any Other Problem
- 98 -
6. TROUBLE SHOOTING
6.6 Other Function Trouble
A. Vibrator
START
Enter into UI menu and

Select the vibrator
Does high level state appear No Resolding R827, R829, R826, R825
at number 3 pin of Q805? and change Q804, Q805
Yes
Does high level state appear No

Change the key board
at number 30 pin in Key B'd
Yes
No
Vibrator soldering Resolding vibrator
OK?
Yes
Change the FPCB
- 99 -
6. TROUBLE SHOOTING
B. Charger
START
Check the pin and battery

connect terminals of
I/O connector
No
Connection OK ? Change I/O connector
Yes
No
Is the TA voltage 5.2V ? Change TA
Yes
Is it charging Yes
properly after End
changing Q501 ?
No
Is it charging Yes
properly after End
changing D501 ?
No
Change the board
- 100 -
6. TROUBLE SHOOTING
C. USB
START
(Measure during the state of USB madule running)
No Check host USB port or

Input power(U801, pin1) is 5V?
USB cable
Yes
No
Output power(U810, pin5) is 3.3V? Change U 810
Yes
No
High level on USB detect(Q809, pin4)? Change Q 809
Yes
No
USB pullup(U811, pin5) is 3.3V? Resoldering R 877
Yes
Change the board
- 101 -
7. STAND ALONE TEST AND TEST POINTS
7.1 Testing Set-up
7.1.1 Received RF Level and Checks

This section shows the typical RF levels expected throughout the receiver path. A block diagram
showing the locations of the RF measurement points and levels is shown in Figure. 7-3.
Receiver Testing Set-up
To check the receiver the following conditions have to be set:
1. On a signal generator or a GSM/DCS test box, output a CW signal of amplitude = -60 dBm at
either: 947.4 MHz (CH62) when testing the GSM RX path or 1842. 6 MHz (CH699) when
testing the DCS RX path.
2. Set the DC power supply to 4.0 V.
Note: All RF values shown are only intended as a guide figure and may differ from readings taken
with other test equipment and leads. Lead and connector losses should always be taken into
account when performing such RF measurements.
Testing Receiver
Using a suitable high frequency probe measure the RF levels at the relevant points shown in Figure.
7-3 and compares your measurements with those shown in the diagram. If there are any major
difference between the readings taken and those indicated then further investigation of that particular
point will be required. It will also be necessary to ensure that all the following power supplies and
signals are present which control this part of the receiver circuit:
1. The Control Signal of Antenna switch (see Figure 7-11 )

2. Vreg 1,2,3 (see Figure 7-7 )
3. 2V85_VCTCXO (see Figure 7-8)
4. 13MHz(see Figure 7-12)
5. CLK, DATA, EN (see Figure 7-13)
6. RX IP, IN, QP, QN (see Figure 7-16,19)
7. Vtune(see Figure 7-17,18)
- 102 -
7.1.2 Transmitted RF Level and Checks

This section shows the typical RF levels expected throughout the transmitter path. A block diagram
showing the locations of the RF measurement points and levels is shown in Figure 7-5.
Transmitter Testing Set-up
To check the transmitter the following conditions have to be set:
1. Configure the testing equipments as Figure equipment setup.
2. Set the GSM/DCS test equipment to be stand-alone mode (asynchronous mode).
3. Set the BCH and TCH ARFCN ‘62’ for EGSM900 or ‘700’ for DCS1800 on GSM/DCS test
equipment.
4. Set the DC power supply 4.0volts.
5. Initialize target on service software.
6. Set TCH and BCH value to be same with GSM/DCS test equipment on service software.
7. Select GSM or DCS mode on service software.
8. Set DAC ‘600’ for EGSM900 or ‘700’ for DCS1800 on service software.
9. Click Test.
1. Set the DC Power supply to 4.0 V.

2. Power up the GSM/DCS test set and then establishing a call with an attached mobile on active
mode.
3. Select Channel, TX Level and Input Level according to which parameter is required.
Note: All RF values shown are only intended as a guide figure and may differ from readings taken
with other test equipment and leads. Lead and connector losses should always be taken into
account when performing such RF measurements.
Testing Transmitter
Using a suitable high frequency probe measure the RF levels at the relevant points shown in Fig. 7-5
and compare your measurements with those shown in the diagram. If there are any major difference
between the readings taken and those indicated then further investigation of that particular point will
be required. It will also be necessary to ensure that all the following power supplies and signals are
present which control this part of the transmitter circuit:
1. The Control Signal of Antenna Switch(see Figure. 7-9, 10)
2. Vreg 1,2,3 (see Figure. 7-7)
3. 2V85_VTCXO (see Figure. 7-8)
4. 13 MHz (see Figure. 7-12)
5. PA_ON, PA_LEVEL, Vapc (see Figure. 7-14)
6. TX IP, IN, QP, QN (see Figure. 7-15)
- 103 -
7.2 Testing Points
7.2.1 RF components
FL102 FL104
7.2.1.1 TOP Side
U105 D103 D102 FL105

Figure 7-1-1. RF components (Top side)
- 104 -
7.2.1.2 Bottom Side
SW101 N101 U101 FL101
FL103 U102 D101 U104 U103 X101
Figure 7-1-2. RF components (Bottom side)
- 105 -
Table 7-1. RF components
Reference Reference
U105 RF main chipset FL101 Dual RF VCO
FL103 Antenna Switch X101 VCTCXO
U101 PAM FL102 Balun
N101 Coupler FL105 GSM RF SAW Filter
U102 NOR Gate FL104 DCS RF SAW Filter
U103 Inverter SW101 Mobile Switch
U104 LDO D101 Dual Schottky Diode
D102 Varactor Diode D103 Varactor Diode
7.2.2 Test point of RX Levels
Figure 7-2. Test point of RX Levels
- 106 -
GSM:CH.62, -60dBm
DCS:CH.699, -60dBm
1 - 62dBm 2 - 64dBm
RXmixQp
GSMlnan RXmixQn
90 o
RXmixIp
RXmixIn
EGSM : 925~960 MHz GSMlnap
SAESD942MCL0T00 TESTvco
DECRXmix
DCSlnan
90 o
DCS : 1805~1880 MHz DCSlnap

HG42UP3
IN
3 - 63dBm 4 - 66dBm
IP
QN
x2 /2
902.5~940 MHz
1850~1920 MHz QP
2.6/1.3MHZ
RFout_rx = (P*A + B + FN/13)*1.3MHz
- 107 -
VC1 VC2
TX
TX 2.6V 0.0V CRF AFC
GSM :5/10 :2
RX 0.0V 0.0V
TX 0.0V 2.6V
DCS RX
RX 0.0V 0.0V
CLK13M
6 - 13dBm
RXLON RXLOP
VC1 16/17 4bits 4bits 7bits
LBswitch
P/P+1 FN B A
VC2 TXRXswitch
HBswitch FL102 Balun VR4in
CLK
Serial Control
LBRX DATA
Logic &
EN
Resisters
Vreg3 R3 RESETZ
SHS-M090B TXRXcp
LF
MAINspup2 CLARA
R2
TRF6150
5 - 10dBm HBRX
HBswitch
LBswitch
TXRXswitch
Vreg3
BIASref
Figure 7-3. Recevier RE Levels

7.2.3 Test point of TX Levels 5 4
12 3
9
10
11
13
1,7
2,8
Figure 7-4. Test point of TX Levels

- 108 -
GSM : Pwr Lvl 5, Ch.62, 32dBm
GSM : 32dBm
DCS : Pwr Lvl 0, Ch.700, 29dBm
DCS : 29dBm
MAINspup
1 T
X CR
LF MAINcp F
:5/10 :2
VC
1
R
VC X
2
1294~1356 MHz
1 MAINvco
-3dBm 16/17 4bits 4bits 7bits
TANK
P/P+1 FN B A
GSM : 15dBm 7
13 DCS : 18dBm
DCS EGSM
Delay
4 0dBm LF
2
BAT15-05W
2dBm 832~858 MHz
BAT15-099 6dBm
33.5dBm
3 8 8/9 3bits 6bits
6 TANK
P/P+1 B A
- 109 -
5 34dBm APC /2
OMIXrf
416-429MHz
I
ATT1 R
3 N
TXRXc I
LF p PFD P
MAINspup2
90 o
ATT2 R2 Q
LDC15D190A0007A
HBR N
X
PF08122B Q
P
9 2dBm
12 31.5dBm
11 32dBm GSM : 975CH (1.0V) ~ 124Ch (1.5V)
CLARA
-2dBm DCS : 512CH (0.6V) ~ 885Ch (1.1V) TRF6150
10
Figure 7-5. Transmitter RF Level

7.2.4 Control signal test points
Vtune
VC1
VC2
13MHz
Regulator_2.85V
LB_SW
HB_SW
Vapc
TXRX_SW
PA_LEVEL
PA_ON
CLK,DATA,EN
I/Q
Figure 7-6. Control signal test points
- 110 -
Figure 7-7. 2V85_Vreg 1, 2, 3 Output
Figure 7-8. 2V85_VCTCXO Supply Voltage
- 111 -
Figure 7-9. Antenna S/W control voltage in EGSM_TX
Figure 7-10. Antenna S/W control voltage in DCS_TX
- 112 -
Figure 7-11. Antenna S/W control voltage in RX
Figure 7-12. 13MHz Clock
- 113 -
Figure 7-13. CLK, DATA, EN
Figure 7-14. PA_ON, PA_LEVEL, VAPC (GSM Tx Level=7)
- 114 -
Figure 7-15. Tx I / Q Signal
Figure 7-16. Rx I / Q Signal
- 115 -
Figure 7-17. PA_ON, Vtune (U105pin 9, GSM 1CH)
Figure 7-18. PA_ON, Vtune (U105 pin 9, DCS 512CH)
- 116 -
Figure 7-19. RX I/Q Signal (Extended)
- 117 -
8. DiSASSEMBLY INSTRUCTION
8-1 Disassembly Instruction

1. Remove the battery cover
- push lockers at both end sides and slide down the battery cover.
Figure 8-1. Removing Battery Cover
2. Remove the battery pack and screws.
Figure 8-2. Removing Screws
- 118 -
3. Detach the rear cover

-use a thin plastic sheet to open the gap between front and rear covers, then detach them carefully
with both hands.
2
1
Figure 8-3. Disassembling Rear Cover
4. Remove the SIM connector and bracket, and detach the camera FPCB from the main PCB
2
1
3
Figure 8-3. Detaching SIM Connector and FPCB
- 119 -
5. First, remove the main PCB and lift the camera out to detach the frame shield.
Then, detach FPCB as shown in the Fig. 8-5.
1 2
Figure 8-5. Detaching Main PCB
- 120 -
6. Detach the keypad and mike.
Figure 8-6. Disassembling Keypad and Mike
7. Remove the antenna and window IrDA, and push away the antenna-bushing using a sharp awl.
Figure 8-7. Removing Antenna and Antenna-bushing.
- 121 -
8. Use a pin to remove Cap Screw and remove screws.
Figure8-8. Removing Cap Screws
9. Use a thin plastic sheet to open the gap between the cover folder upper and cover folder lower,
then detach the cover folder upper carefully with both hands
2
1
Figure8-9. Detaching Upper Cover
- 122 -
10. Use a sharp awl to remove the hinge.
Figure8-10. Removing Hinge
11. Detach the front cover from the lower cover.
Figure 8-11. Detaching Front Cover
- 123 -
12. Remove FPCB from the slit of the lower cover.
Figure 8-12. Removing FPCB
13. Detach LCD very carefully and remove FPCB from the connector of LCD Module.
Figure 8-13. Detaching LCD and FPCB
*Note:When you change FPCB, remove 'tape' and 'solder' firstly.
- 124 -
8-2. Assembly Note

14. First, insert the camera into the main FPCB before assembling them.
Figure 8-14. Assembling Camera Main PCB
15. When placing the main PCB on the frame shield, push the center of it not to override the top
button.
Figure 8-15. Assembling Main PCB
- 125 -
9. BLOCK DIAGRAM
9. BLOCK DIAGRAM
9.1 Main Board
9.1.1 Baseband Blockdiagram (Memory & Audio path)
Figure 9-1-1. Main Block diagram.
- 127 -
9. BLOCK DIAGRAM
9.1.2 Baseband Blockdiagram (UART path)
Figure 9-1-2. Main Block diagram.
- 128 -
9. BLOCK DIAGRAM
9.2 LCD Module
Figure 9-2. FPCB Block diagram.
- 129 -
9. BLOCK DIAGRAM
9.3 RF
Figure 8-3. RF Block diagram.
- 130 -
9. CIRCUIT DIAGRAM
9. CIRCUIT DIAGRAM
Main PCB Circuit (1/5)
1 2 3 4 5 6 7 8 9 10 11 12
TP505 TP521
TP503 TP501 TP502
R508
R507 0
CAL_TDO
CAL_TCK
CAL_TMS
CAL_TDI
R537 100K
DTC_SENSE VRRTC
A A
BAT_SENSE R535 UPR
R536
R527
200K
R538
120K
R533
C524
TP504
R531 VRIO
0.1u
SN74CBTLV3257DGVRU502 TP524
220K
10K
10K
10K
16 R544 100K
VCC
1 CCK13M
CCK32K
R516
S C527 C517
2 15
HEL_UART_DATA_RTS 5
1B1 _OE
VRMEM
10p 10p ONNOFF
R510
R503
R504
R521
HEL_UART_DATA_CTS 11
2B1
4
HEL_UART_DATA_TX 14
3B1 1A CAL_NTRST
4
HEL_UART_DATA_RX 4B1
7
crystalX501
_RPWON
R515
2A
0
32.768KHz
3 9 R552
PC_UART_CTS 6
1B2 3A ONNOFF_TO_BUF _END_ONOFF
PC_UART_RTS
R518
2B2 0
10 12
PC_UART_RX 13
3B2 4A VRIO
3
2
PC_UART_TX 4B2
8
C514
B GND 220n B
C505
PWL_MAIN_LCD_BL 18p
R543
R523
HEL_UART_CNTL_TX VRIO
U504 NL27WZ126US
R549 1 8
ONNOFF_BUF OE1 VCC CCK32K_CUT
0
2 7
PA_ON
CCK32K A1 OE2 TSPEN
3 6
HEL_UART_CNTL_RX Y2 Y1 TSPCLK
4 5
TSPDATA
RESETCL
R545
GND A2
TCXO_EN
CAL_TX_MBOX C528 1000p CLK13M
_HEL_SYS_RST PA_LEVEL
RADIO_TEMP
0
C HEL_TX_MBOX C
MMAUDIO_CAL_HEL HEL_MCSI_CLK
R517
HEL_MCSI_FS
HEL_MCSI_DI
HEL_MCSI_DO
R563
10K
R548
100K
R547
0
M10
N10
N11
A13
A12
A14
C13
B13
C12
P11
E13
L10
F12
VRMEM
M9
M4
M2
K8
N9
C8
D8
C7
A8
B8
B9
A9
C9
D9
K9
N3
N2
K7
P9
E8
P3
L9
L4
L7
VRIO
SDO
SDI
SCLK
NSCS0
NSCS1
TX_IRDA
RX_IRDA
TXIR_IRDA
RXIR_IRDA
SD_IRDA
TX_MODEM
RX_MODEM
RTS_MODEM
CTS_MODEM
DSR_MODEM
MCSI_TXD
MCSI_RXD
MCSI_CLK
MCSI_FSYNCH
BCLKX
BCLKR
IO2
IO3
IO0
IO1
RFEN
TCSOEN
NRESET_OUT
IDDQ
BU
LT
VSSO
OSC32K_IN
OSC32K_OUT
CLKTCXO
CLK13M_OUT
CLK32K_OUT
MOTOR_EN VBACKUP
1SS388
D551
H10
R524
TSPDI
10K
H11
EAR_SPEAKER_SW
B10
A10
TSPDO
A4
K4
F1
F2
J4
J14
TSPCLKX
H13
R556
R550
100K
TSPEN0
CK13M
TDR
TEN
OSCAS
PWON
RPWON
TESTRESETZ
H12
D H14
TSPEN1
N1
C516 D
TSPEN2 NIBOOT D515 D511 0.033u
G12
TSPEN3
M12 F10 1SS388 1SS388 D10 F10
CAL_UART_DCD M14
TSPACT0 ON_OFF
D12 F6
ON_OFF DAC
F8
CAL_UART_DSR L12
TSPACT1 RESPWRONZ
B14 R546 270 D7
RESPWRONZ AFC
F9 AFC
R561 TSPACT2 IT_WAKEUP RTC_ALARM APC
L13 M3 H4
MMAUDIO_CAL_HEL J10
TSPACT3 EXT_IRQ INT2
C9
0 TSPACT4 BULIP R502 36 IP
K11 P1 F7 C10 R501 36
TSPACT5 EXT_FIQ INT1 BULIM
C501
C502
K13 D8
270p
270p
TSPACT6 C906 U555 BULQP R506 36 QP
K12 NC7SB3157P6X VRIO C8 D9
TSPACT7 TP525 0F TEST1 BULQM R505 36
K14 D11 1 B1 6 B8 E7
TSPACT8 NBSCAN S TEST2 BDLIP
J11 2 GND VCC 5 A9 E8
J12
TSPACT9
B11 B9
TEST3 BDLIM
E9
IM
TSPACT10 NEMU0 3 B0 A 4 TEST4 BDLQP
J13 E10 E10
TSPACT11 NEMU1
D10 C7
BDLQM QM
CAL_ADD(22)
TDI TDO
CAL_ADD(21) L3 C10 A7 K8
L2
ADD21 TDO
B10 B7
TDI MICIP
J8
MICP
CAL_ADD(20)
DAI_SYNC L1
ADD20 TCK
E9 A8
TCK MICIN
K9
MICN
CAL_ADD(19)
DAI_CLK R562 J5
ADD19 TMS TMS MICBIAS
H9 MICBIAS
DAI_RX CAL_ADD(18)
ADD18 EARP R526 0 EAR_PIECEP
CAL_ADD(17) K4 L11 J5 H8 R525 0
E DAI_TX K2
ADD17 BFSR
K10 K5
BFSK EARN
J9
EAR_PIECEM E
CAL_ADD(16)
K3
ADD16 BDR
P12 G5
BDX AUXOP
J10 AUXOP
CAL_ADD(15)
ADD15 U503 BFSX BFSR U501 AUXON AUXON
CAL_ADD(14) J4 M11 H5 H7
ADD14 BOX BDR AUXI AUXI
C523
100p
J3 G8
CAL_ADD(13)
CAL_ADD(12) J2
ADD13
ADD12
XF741979BGGH VDX
P14 K7
VDR
PTWLR3012BGGM AUXGND
AGNDA1
J7
CAL_ADD(11) J1 N13 G6
ADD11 VDR VDX C521 C522
CAL_ADD(10) H5 M13 G7 B5
ADD10 VSFRX VFS ADIN1 R599 10p 10p
CAL_ADD(9) H4 N12 H6 A5
ADD9 VCLKRX VCK ADIN2
CAL_ADD(8) H2 E6
HS_HF_SW
R598
ADD8 ADIN3 10K
62K
H3 N7 J6 D6
PT501
CAL_ADD(7)
ADD7 MCUDI UDX ADIN4_TSCXP C508 1u
CAL_ADD(6) H1 M7 K6 C6
ADD6 MCUDO UDR ADIN5_TSCYP
CAL_ADD(5) G3 M8 F5 C5
ADD5 MCUEN0 UEN LCDSYNC
CAL_ADD(4) G2 P8 A6
ADD4 MCUEN1 TSCYM
CAL_ADD(3) G4 L8 R519 1M B6
ADD3 MCUEN2 TSCXM
CAL_ADD(2) G5 20K R511
ADD2
CAL_ADD(1) F2 G13 A2 CN803
CAL_ADD(1:22) F3
ADD1 SIM_IO
F13 B2
SVDD
D4 R541 0 1 G8000
ADD0 SIM_CLK SDIO3 SDIO5
G10 C4 B4 R542 0 2
SIM_RST SCLK3 SCLK5
CAL_DATA(15) B3 B3 D5 3
DATA15 VRIO SRST3 SRST5
CAL_DATA(14) A3 F14 R528 20K 4
F D4
DATA14 SIM_PWRCTRL
VBAT_2 K2 A3 C509 1u 5
F
CAL_DATA(13)
DATA13 VCC11 VAUX C541 C542
CAL_DATA(12) C4 G11 R530 10K K3 A1 C506 220n 6
DATA12 SIM_CD VCC12 VS2 0F 0F
CAL_DATA(11) B4 D2 B1 3G 3G 7
DATA11 VCC2 VS1
CAL_DATA(10) E5 C11 G9 8
DATA10 NC VCC3
SP6
SP7
SP8
SP9
CAL_DATA(9) D5 C3 9
DATA9 UPR R569
CAL_DATA(8) B5 J3 D512 1SS388 10
DATA8 UPR VBACKUP
CAL_DATA(7) C5 J1 E5
DATA7 FDBK VBAT 1K
CAL_DATA(6) E6 E4
C6
DATA6
E2
VCHG
E3
CHARGER
CAL_DATA(5)
R513
100K
DATA5 10K VR2IN ICTL
CAL_DATA(4) A6 D3
DATA4 VR2SEL C507
CAL_DATA(3) D6 R509 K10
DATA3 BUZZOP 0.022u
E7 H1 G2
5
CAL_DATA(2)
DATA2 VR1OUT NC1
D7 E1 G3 VBACKUP
S
CAL_DATA(1)
DATA1 VR2OUT NC2
G
B7 H10 G4
4
CAL_DATA(0)
DATA0 VR3OUT NC3
D1
D2
D3
D6
6 D4
D5
VDDS_MIF1
VDDS_MIF2
VDDS_MIF3
VDDS_MIF4
VDDS_RTC
C1 H2 VBAT VBAT_RF
NTHS5441T1
VDDS_1_1
CAL_DATA(0:15) VDDS_1_2 VR1BOUT NC4
VDD_PLL
7
Q501
1
2
8
VDDANG
VSSANG
VDDRTC
D1 H3 VBAT_2
VSSRTC
VSSPLL
VDDS_2 VR2BOUT NC5

VSS10
VSS11
VSS12
NFWE
REFGND
NBHE
NFOE
NBLE
KBC4
KBC3
KBC2
KBC1
KBC0
KBR4
KBR3
KBR2
KBR1
KBR0
J2
NCS3
NCS2
NCS1
NCS0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
RNW
CRS08
GRND1
GRND2
GRND3
NC6
FDP
CS4
D501
IBIAS
VREF
UPR
R512
BAT501
B2
E3
E2
F5
E4
D2
D3
C1
C3
C2
F4
M5
P5
L5
K5
N4
L6
N6
P6
M6
K6
B1
F1
K1
P2
P4
N8
P10
P13
G14
A10
A7
A2
E14
E12
C14
D1
G1
B6
A4
E1
M1
P7
N14
B12
A5
F11
N5
L14
A11
E11
D13
D14
G TP522 C503 G
K1
C2
G10
F3
G1
F4
0.2 0.1u
120K
0.1u
TP526 C504
0.1u
C519
_CAL_WR TP523
R520
VRRTC VRRTC
_CAL_RD U505
VRABB VR1B
S-817A18ANB-CUH-T2
_CAL_BHE
VOUT VIN
3 2
_CAL_BLE
1SS388
D510
VRDBB VRMEM VRIO C599 NC VSS

4 1
0.1u
_CAL_CS1
H Engineer:
H
_CAL_CS0 JS Lee COMPANY NAME
Drawn by: Address
_CAL_FDP mentor City
C520 C526 C518 C529 C525 C513 C511 C512 C515 C510
10u 10u 10u 15uF 10u R&D CHK: TITLE: Size:
0.1u 0.1u 0.1u 0.1u 0.1u
A2
DOC CTRL CHK: CALYPSO_IOTA
12 1 8 A
MFG ENGR CHK:
Changed by: Date Changed: Time Changed: QA CHK: REV: Drawing Number: Page:
mentor Tuesday, December 11, 2001 5:38:35 pm 2
1 2 3 4 5 6 7 8 9 10 11 12
- 131 -
9. CIRCUIT DIAGRAM

1 2 3 4 5 6 7 8 9 9 10 11 12
HEL_PLL_1.5V
VBAT_2
HEL_IO_MEM_2.8V HEL_IO_MEM_2.8V HEL_CORE_1.5V
A C652 C653 A
0.1u 0.1u
R602
C605
1u
R628
R629
100K
51K
R646 10K
U602 SC600BIMSTR
R627 1 10
MAIN_LCD_LED+ VOUT CF2+
A3212ELH 1
OUT 2
4.7
U601
VDD
2 9 HEL_IO_MEM_2.8V
SP42
R680
CF1+ CF1- C606 C617 C616 C608 C607 C610 C615 C609 C618
1u C602 10p 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u 0.1u
3 8
GND
3
C651 VIN GND 0.1u C601
10u R645
4 7
MAIN_LCD_BACKLIGHT
FID0 CF2-
R606
R609
C612 5 6 R658 470
FID1 EN PWL_MAIN_LCD_BL
1u
C676
10K
10K
R647
100K
USB_DETECT
HEL_IO_MEM_2.8V
220p
B USB_VDD B
USB_DP
HEL_IND_LED_O USB_DM
USB_VBUS
AA17
AA21
AA11
W20
W10
AA7
AA1
AA2
AA3
M15
R19
R18
U20
R21
K20
B18
B16
A21
A13
A11
B12
B10
U21
A19
A15
R20
B20
B13
V20
Y15
V12
Y16
E21
Y21
Y20
P12
V18
T18
F20
L21
J20
J21
W4
M2
G1
U2
N1
K2
B7
B5
B2
B1
R1
H2
C2
A7
A5
A1
A9
A3
R8
E2
Y3
V5
V2
P3
E1
Y7
Y1
P9
E5
L1
F2
CONN_21FXL_RSM_TB CN601
VBAT_2 3
VDD_H HEL_FADD(1:23)
SDA
SCL
GPIO_1
GPIO_0
GPIO_7
ARM_BOOT
VSS26
VSS28
VSS27
VSS25
VSS24
VSS23
VSS22
VSS21
VSS20
VSS19
VSS18
VSS17
VSS16
VSS15
VSS14
VSS13
VSS12
VSS11
VSS10
VSS9
VSS8
VSS7
VSS6
VSS5
VSS4
VSS3
VSS2
VSS1
VDDSHV6
VDDSHV5_7
VDDSHV5_6
VDDSHV5_5
VDDSHV5_4
VDDSHV5_3
VDDSHV5_2
VDDSHV5_1
VDDSHV4_5
VDDSHV4_4
VDDSHV4_3
VDDSHV4_2
VDDSHV4_1
VDDSHV3
VDDSHV2
VDDSHV1_6
VDDSHV1_5
VDDSHV1_4
VDDSHV1_3
VDDSHV1_2
VDDSHV1_1
VDD13
VDD12
VDD11
VDD10
VDD9
VDD8
VDD7
VDD6
VDD5
VDD4
VDD3
VDD2
VDD1
USB_DP
USB_DM
USB_CLKO
CONF
NC
2 HEL_FADD(1:23)
VDD_L
LCD_1.8V 5 R664 270
SCL
8 R665 270
SDA
HEL_IO_MEM_2.8V 17 R667 270 L19 J8 HEL_FADD(1)
D0 CAM_D_0 FADD_1
CN602 14 R668 270 K14 D3 HEL_FADD(2)
D1 CAM_D_1 FADD_2
1 15 R669 270 K15 C1 HEL_FADD(3)
D2 CAM_D_2 FADD_3
2 18 R670 270 K19 E4 HEL_FADD(4)
3
PC_UART_TX D3
11 K18
CAM_D_3 FADD_4
D2
PC_UART_RX D4 R671 270 CAM_D_4 FADD_5 HEL_FADD(5)
4 12 R672 270 J14 F4 HEL_FADD(6)
5
CAL_TMS D5
9 J19
CAM_D_5 FADD_6
E3
CAL_TCK D6 R673 270 CAM_D_6 FADD_7 HEL_FADD(7)
6 10 R674 270 J18 J7 HEL_FADD(8)
7 CAL_TDO D7
20 H19
CAM_D_7 FADD_8
F3
C CAL_TDI CKIN R675 270 CAM_EXCLK FADD_9 HEL_FADD(9)
C
8 7 R914 270 L15 G4 HEL_FADD(10)
9
CAL_NTRST HS
16 J15
CAM_HS FADD_10
G3
HEL_FOLDER_DET DCK R677 270 CAM_LCLK FADD_11 HEL_FADD(11)
10 6 R678 270 M19 G2 HEL_FADD(12)
XRST CAM_RSTZ FADD_12
11 13 R679 270 L18 K8 HEL_FADD(13)
VS CAM_VS FADD_13
12 1 V8 H4 HEL_FADD(14)
13
_END_ONOFF NC1
21
_YMU762_RST V7
ARMIO_3 FADD_14
H3 HEL_FADD(15)
14
KEY_ROW0 NC2
4 P10
COM_SPI_CLKR FADD_15
K7
SP31
SP32
SP33
SP34
SP38
SP35
SP36
SP37
SP39
SP40
SP41
HEL_FADD(16)
15
KEY_ROW1 GND1
19 W6
COM_SPI_DIN FADD_16
J2 HEL_FADD(17)
16
KEY_ROW2 GND2
22 Y6
COM_SPI_RSYNC FADD_17
J4 HEL_FADD(18)
17
KEY_ROW3 GND3
23
C604 C603 C908 C909 C910 C905 MAIN_LCD_CLK AA5
COM_SPI_CLKX FADD_18
J3 HEL_FADD(19)
18 KEY_ROW4 GND4 0.1u 0.1u 18p 18p 18p 18p MAIN_LCD_DATA W7
COM_SPI_DOUT FADD_19
J1 HEL_FADD(20)
19
MAIN_LCD_RES MAIN_LCD_CS U19
COM_SPI_XSYNC FADD_20
L8 HEL_FADD(21)
20
MAIN_LCD_CD_SEL MAIN_LCD_RES M14
ARMIO_1 FADD_21
K4 HEL_FADD(22)
21 MAIN_LCD_DATA _YMU762_IRQ V10
GPIO_2 FADD_22
K3 HEL_FADD(23)
22
SUB_LCD_RES CAL_TX_MBOX V11
MEDIA_CMD FADD_23
L7 HEL_DATA(0:15)
23
SUB_LCD_CD_SEL P11
MEDIA_CLK FADD_24
N4
HEL_DATA(0:15)
HEL_DATA(0)
24
UWIRE_SDO W11
MEDIA_CS FDATA_0
N2 HEL_DATA(1)
25 HEL_IO_MEM_2.8V
STEREOJACK_DET R11
MEDIA_DI FDATA_1
N7 HEL_DATA(2)
MEDIA_DO FDATA_2
26 P20 P2 HEL_DATA(3)
27
C MAIN_LCD_CD_SEL Y10
GPIO_4 FDATA_3
P4 HEL_DATA(4)
D 28 Q666 B
HEL_MCSI_CLK AA9
COM_PCM_CLK FDATA_4
P7
D
HEL_DATA(5)
29
LOUD_SPKP DTC144EE EL_ONOFF HEL_MCSI_DI W9
COM_PCM_DIN FDATA_5
R2 HEL_DATA(6)
30
EAR_PIECEP HEL_MCSI_DO R610 10K R10
COM_PCM_DOUT FDATA_6
R3
E HEL_DATA(7)
R663
COM_MCLK_REQ FDATA_7
10K
31 V9 R4 HEL_DATA(8)
32 MOTOR_BATT HEL_MCSI_FS P14
COM_PCM_SYNC FDATA_8
T2 HEL_DATA(9)
33
EAR_PIECEM N18
COM_SHUTDOWN FDATA_9
T3
LOUD_SPKM SUB_LCD_CD_SEL GPIO_12 U603 FDATA_10 HEL_DATA(10)
34 F18 P8 HEL_DATA(11)
35 KEY_COL0 D20
KBC_0 FDATA_11
U1
MAIN_LCD_LED+ KEY_COL1 KBC_1 OMAP1510 FDATA_12 HEL_DATA(12)
36 D19 U3 HEL_DATA(13)
37
KEY_COL2 E18
KBC_2 FDATA_13
T4 HEL_DATA(14)
38
KEY_COL3 C21
KBC_3 FDATA_14
V3 HEL_DATA(15)
39
UWIRE_SCLK KEY_COL4 C20
KBC_4 FDATA_15
M7
40
SUB_LCD_CS KEY_COL5 G18
KBC_5 NFCS_0
M3
HEL_NFCS_0
41
KEY_ROW0 F19
KBR_0 NFCS_1
M4
HEL_NFCS_1
42
MAIN_LCD_CLK KEY_ROW1 H14
KBR_1 NFCS_2
N8
HEL_NFCS_2
43
MAIN_LCD_CS KEY_ROW2 E20
KBR_2 NFCS_3
L3
HEL_NFCS_3
44
KEY_ROW3 E19
KBR_3 NFBE_0
M8
HEL_NFBE_0
45
KEY_COL0 1SS388
KEY_ROW4 P18
KBR_4 NFBE_1
U4
HEL_NFBE_1
46 KEY_COL1 R14
GPIO_3 NFOE
W2 HEL_NFOE
47
KEY_COL2 _END_ONOFF KEY_ROW0 AA15
CTS1 NFWE
H7
HEL_NFWE
E 48
KEY_COL3 D699
V14
RTS1 NFRDY
V4
HEL_NFRDY E
49 KEY_COL4 HEL_UART_CNTL_RX Y14
RX1 NFWP
W1 HEL_NFWP
50
KEY_COL5 HEL_UART_CNTL_TX L14
TX1 NFRP
L4
HEL_NFRP
51
KEY_LED- HEL_UART_IRDA_RX M18
RX NFADV
N3
HEL_NFADV
52
HEL_EMU0 HEL_UART_IRDA_TX Y5
TX FCLK
D18
HEL_FCLK
53
HEL_EMU1 HEL_UART_DATA_CTS W5
CTS2 LCD_PIXEL_0
B21
54
HEL_NTRST HEL_UART_DATA_RTS R9
RTS2 LCD_PIXEL_1
C19
55
HEL_TDI HEL_UART_DATA_RX V6
RX2 LCD_PIXEL_2
G14
HEL_TDO HEL_UART_DATA_TX TX2 LCD_PIXEL_3 TP608
TP606
TP605
TP604
TP603
TP607
TP601
TP602
56 AA13 H13
57
HEL_TCK V13
BT_PCM_BCLK LCD_PIXEL_4
A20
58
HEL_TMS HEL_UART_PC_CTS W13
BT_PCM_SYNC LCD_PIXEL_5
B19
59
PC_UART_RTS HEL_UART_PC_RTS W14
BT_PCM_DIN LCD_PIXEL_6
C18
60 PC_UART_CTS Y19
BT_PCM_DOUT LCD_PIXEL_7
D17
61 VBAT
HEL_TDI AA19
TDI LCD_PIXEL_8
D16
62
HEL_TDO V17
TDO LCD_PIXEL_9
C17
HEL_TMS W18
TMS LCD_PIXEL_10
B17
HEL_TCK Y18
TCK LCD_PIXEL_11
G13
HEL_NTRST V16
NTRST LCD_PIXEL_12
A17
HEL_EMU0 W17
NEMU0 LCD_PIXEL_13
C16
HEL_EMU1 Y17
NEMU1 LCD_PIXEL_14
D15
F N19
NBSCAN LCD_PIXEL_15
D14
F
HF_CALL_OFF_ON
R681
R682
GPIO_13 LCD_VSYNC
COM_MCLK_OUT
10
10
PCM_DATA_OUT
N21 H12
NRESETPWRON
EL_ONOFF
TI_RESERVED4
TI_RESERVED6
BT_MCLK_REQ
BT_MCLK_OUT
GPIO_14 LCD_HSYNC
PCM_DATA_IN
CLK32K_CTRL
PCM_BIT_CLK
MPU_NRESET
T20
NRESET_OUT
B15
OSC32K_OUT
CLK32K_OUT
WIRE_NSCS3
WIRE_NSCS0
HF_DET ARMIO_5 LCD_AC
WIRE_SCLK
PCM_SYNC
OSC32K_IN
PCM_CLKS
CLK32K_IN
OSC1_OUT
SDCLK_EN
WIRE_SDO
LCD_PCLK
SDATA_10
SDATA_11
SDATA_12
SDATA_13
SDATA_14
SDATA_15
WIRE_SDI
SBANK_1
SBANK_0
SDATA_0
SDATA_1
SDATA_2
SDATA_3
SDATA_4
SDATA_5
SDATA_6
SDATA_7
SDATA_8
SDATA_9
SADD_10
SADD_11
SADD_12
ARMIO_4
ARMIO_2
NSDQMU
NSDQML
OSC1_IN
GPIO_11
GPIO_15
EXT_FIQ
SADD_0
SADD_1
SADD_2
SADD_3
SADD_4
SADD_5
SADD_6
SADD_7
SADD_8
SADD_9
GPIO_8
GPIO_9
GPIO_6
NSRAS
NSCAS
SDCLK
3
NSWE
1
HEL_IO_MEM_2.8V HEL_IO_MEM_2.8V
LD603
LD602
LD601
LNJ717W80RA1
LNJ717W80RA1
LNJ717W80RA1
TP666
D10
C10
U18
w21
V19
P15
N14
H15
G20
G21
H20
H18
Y8
W8
N20
M20
T19
Y9
W12
R12
Y2
W3
W16
Y4
Y12
P19
N15
V15
G19
W15
W19
R13
Y13
P13
100K AA20
B14
C14
G12
D13
C13
H11
D12
C12
G11
D11
C11
H10
G10
B9
G9
C8
G8
B8
D8
C7
D7
B6
C6
H8
C5
D6
B4
C4
D5
D9
C9
D4
B3
A2
H9
C3
C15
HEL_CLK_12M_OUT
R613 R605
R615
R666
10K
10K
100K
10K 10K
2
R635
4
_HEL_SYS_RST
R636
HEL_IO_MEM_2.8V
TP667
G R616 G
HEL_FOLDER_DET
CCK32K_CUT
UWIRE_SDO
UWIRE_SCLK
SUB_LCD_CS
SPEAKER_EN
PC_IRDA_SEL
HEL_IND_LED_B
MAIN_LCD_BACKLIGHT
HEL_TX_MBOX
SUB_LCD_RES
HEL_FADD(1)
HEL_NFOE
HEL_NFWE
470
470
1K
1K
1K
R607 10K
R626
R622
R601
150
33
56
R640
R641
R642
R643
R644
R689
100K
R623
HEL_IND_LED_G
R611
20K
2.7K
6 5 4 6 5 4
VBAT
C671
ONNOFF HEL_IND_LED_G
R620
100
EMX1 EMX1 C672 0F R614
C613
Q602
18p
NC7SB3157P6X Q603 1 2 3 Q604 1 2 3
12 X601
C673 47p 1 2 3
HEL_IND_LED_O 1 B1 S 6
C674 47p
C614
2 GND VCC 5 Q601
18p
R619 C675 18p 97SMX
3 B0 4 EMX18 12MHz
H CHARGER A
R624 10K R612 Engineer:
H
10K SP43
Y.J. SEOK COMPANY NAME
R661
R621
C666 12
2.7K
47K
Drawn by: Address

0.1u City
Y.J. SEOK
SW601 SW602 SW603 6 5 4 R&D CHK: TITLE: Size:
2 4 24 2 4
A2
DOC CTRL CHK: OMAP1509
R625 1 3 1 3 1 3 12 1 8 A
HEL_IND_LED_B KEY_LED- MFG ENGR CHK:
20K
mentor Monday, December 10, 2001 5:25:44 pm 0 9
1 2 3 4 5 6 7 7 8 9 10 11 12
- 132 -
9. CIRCUIT DIAGRAM

1 2 3 4 5 6 7 8 9 10 11 12
A A
B B
HEL_FADD(1:23)
HEL_DATA(0:15)
HEL_DATA(0:15)
TH50VPF5781AASB U701
HEL_FADD(1) G2 J3 HEL_DATA(0)
F2
A0 DQ0
G4
CAL_DATA(0:15)
HEL_FADD(2) HEL_DATA(1)
A1 DQ1
HEL_FADD(3) E2 K4 HEL_DATA(2)
A2 DQ2
HEL_FADD(4) D2 H5 HEL_DATA(3)
A3 DQ3
HEL_FADD(5) F3 H6 HEL_DATA(4)
A4 DQ4
HEL_FADD(6) E3 K7 HEL_DATA(5)
C D3
A5 DQ5
G7
C
C3
A6 DQ6
J8
CAL_ADD(1:22)
A7 DQ7
HEL_IO_MEM_2.8V HEL_FADD(9) C7 K3 HEL_DATA(8)
A8 DQ8
HEL_FADD(10) E7 H4 HEL_DATA(9)
A9 DQ9
HEL_FADD(11) F7 J4 HEL_DATA(10)
A10 DQ10
HEL_FADD(12) C8 K5 HEL_DATA(11)
A11 DQ11
HEL_FADD(13) D8 J7 HEL_DATA(12)
A12 DQ12
HEL_FADD(14) E8 H7 HEL_DATA(13)
A13 DQ13
F8 K8 TH50VPF5683DASB U702
10K
10K
A14 DQ14
HEL_FADD(16) D9 H8 HEL_DATA(15) HEL_IO_MEM_2.8V
A15 DQ15
HEL_FADD(17) G9 HEL_IO_MEM_2.8V CAL_ADD(1) G2 J3 CAL_DATA(0)
A16 A0 DQ0
R705
F4 F2 G4
R797
HEL_FADD(18) CAL_ADD(2) CAL_DATA(1)

A17 A1 DQ1
HEL_FADD(19) E4 J5 CAL_ADD(3) E2 K4 CAL_DATA(2)
A18 VCCF1 A2 DQ2
HEL_FADD(20) D7 G5 CAL_ADD(4) D2 H5 CAL_DATA(3)
A19 VCCF2 A3 DQ3
HEL_FADD(21) E6 J6 CAL_ADD(5) F3 H6 CAL_DATA(4)
A20 VCCS A4 DQ4
HEL_FADD(22) E9 CAL_ADD(6) E3 K7 CAL_DATA(5)
A21 A5 DQ5
CAL_ADD(7) D3 G7 CAL_DATA(6)
A6 DQ6
J9 CAL_ADD(8) C3 J8 CAL_DATA(7)
VSS0 A7 DQ7
H2 G3 CAL_ADD(9) C7 K3 CAL_DATA(8)
HEL_NFCS_0 F5
_CEF1 VSS1 A8
E7 H4
DQ8
CAL_ADD(10) CAL_DATA(9)
D H3
_CEF2 C701 A9
F7 J4
DQ9 D
_OE 0.1u U703 CAL_ADD(11)
A10 DQ10 CAL_DATA(10)
C6 A1 TC58FVB641XB-70 CAL_ADD(12) C8 K5 CAL_DATA(11)
_WE NC0 A11 DQ11
H9 A10 CAL_ADD(13) D8 J7 CAL_DATA(12)
_BYTE NC1 A12 DQ12
B1 HEL_DATA(0) G3 J5 CAL_ADD(14) E8 H7 CAL_DATA(13)
NC2
B10 K3
DQ0 VDD _CAL_CS0 A13
F8 K8
DQ13
HEL_DATA(1) CAL_ADD(15) CAL_DATA(14)
NC3 DQ1 A14 DQ14
E5 C1 HEL_DATA(2) G4 CAL_ADD(16) D9 H8 CAL_DATA(15)
HEL_NFCS_1 C5
RY_BY NC4
F1 K4
DQ2
G2
A15
G9
DQ15
HEL_DATA(3) HEL_FADD(1) CAL_ADD(17)
_WP_ACC NC5 DQ3 A0 A16
D5 F6 HEL_DATA(4) K5 F2 HEL_FADD(2) CAL_ADD(18) F4
_RESET NC6 DQ4 A1 A17
F9 HEL_DATA(5) G5 E2 HEL_FADD(3) CAL_ADD(19) E4
NC7 DQ5 A2 A18
F10 HEL_DATA(6) K6 C2 HEL_FADD(4) CAL_ADD(20) D7 J5
NC8 DQ6 A3 A19 VCCF VRMEM
10K
G1 HEL_DATA(7) G6 D2 HEL_FADD(5) CAL_ADD(21) E6 J6
NC9 DQ7 A4 A20 VCCS
C4 G6 HEL_DATA(8) H3 F3 HEL_FADD(6) CAL_ADD(22) E9
HEL_NFBE_0 D4
_LB NC10
G10 J3
DQ8 A5
E3
A21
HEL_DATA(9) HEL_FADD(7)
HEL_NFBE_1 J2
_UB NC11
L1 H4
DQ9 A6
C3
_CAL_CS1 C702
R718
_CE1S NC12 DQ10 A7 0.1u
D6 L10 HEL_DATA(11) J4 D6 HEL_FADD(9) H2 J9
CE2S NC13 DQ11 A8 _CEF VSS0
K6 M1 HEL_DATA(12) H5 C6 HEL_FADD(10) H3 G3
G8
DU1 NC14
M10 J6
DQ12 A9
E6
_CAL_RD C6
_OE VSS1
DU2 NC15
H6
DQ13 A10
F6
_CAL_WR H9
_WE
DQ14 A11 _BYTE
HEL_DATA(15) J7 D7 HEL_FADD(13)
DQ15 A12
C7 HEL_FADD(14) A1
E H2
A13
E7
NC0
A10
E
HEL_FADD(15)
_CE A14 NC1
F7 HEL_FADD(16) E5 B1
A15 RY_BY NC2
C5 G7 HEL_FADD(17) C5 B10
_WE A16
D3
_CAL_FDP D5
_WP_ACC NC3
C1
HEL_FADD(18)
A17 _RESET NC4
J2 E4 HEL_FADD(19) F1
_OE A18 NC5
F5 HEL_FADD(20) F9
A19 NC6
H7 F4 HEL_FADD(21) F10
HEL_NFCS_2 C4
_BYTE A20
E5 C4
NC7
G1
HEL_FADD(22)
D5
RY_BY A21
K2
_CAL_BLE D4
_LB
G10
NC8
HEL_NFWE D4
_RESET VSS1
K7
_CAL_BHE J2
_UB
L1
NC9
G7000 EUASV
_WP_ACC VSS2 _CE1S NC10
D6 L10
HEL_NFOE K6
CE2S
M1
NC11
DU1 NC12
G8 M10
C704 DU2 NC13
0.1u
R712
HEL_NFRP
F R711 F
_HEL_SYS_RST
0
R708
R789
10K
10K
R710 0
HEL_NFWP
HEL_IO_MEM_2.8V
10K
R798
G G
HEL_NFRDY
H Engineer:
H
JS Lee COMPANY NAME
Drawn by: Address
mentor City
R&D CHK: TITLE: Size:
A2
DOC CTRL CHK: Memory
12 1 8 A
MFG ENGR CHK:
mentor Tuesday, December 11, 2001 5:53:17 pm 3
1 2 3 4 5 6 7 8 9 10 11 12
- 133 -
9. CIRCUIT DIAGRAMΩ

1 2 3 4 5 6 7 8 9 1 0 11 12
VBAT 3 4 4.7uH
HEL_IO_MEM_2.8V U808 LTC1701BES5 P3 P4
5 1
D6
8
VIN SW 1
P1 P2
2 HEL_CORE_1.5V
R875
R842
20K
1M
D5
7 L801
GND
D4
6 4 3
A 5
S D3
3
RUN VFB A
R810
300K
R843
2.2K
D2
2
2
MBRM120LT3
LEDA D1 C851 C852
1 G 1
33u 47uF
R844
100K
R811 NTHS5441T1
D802
U802SN74CBTLV3257DGVR 4
LEDK Q801 C853
16 2
VCC C 0 330p
1
R815 PC_IRDA_SEL 15
S
2 3
TXD R821 B Q802
MICBIAS _OE 1B1
5
SHIELD
8 DTC144EE
1K 2B1 RXD 10K
4 11 4 VBAT
HEL_UART_IRDA_TX
R849
R878
E
1A 3B1 C888
12K
1K
14
C809
0.1u
4B1 SD 0F
7 5
HEL_UART_IRDA_RX 2A U812
MICP VCC NCP500SN18T1
9 3 6 1 5
C812 3A 1B2
6
HEL_UART_PC_TX 2
VIN VOUT LCD_1.8V
27p 2B2 HEL_UART_PC_RX GND GND
OBG-15S44-C2
12 10 7 3 4 C866
1
C814 C854 C857 4A 3B2 EN NC
10u 13 CIM-80S7B-T 10u
27p 27p 4B2
MIC801
VRIO
C815
8 U801
0.1u
GND
2
C801
MICN 0.47u U813 U804
1 5 1 5
B C817
2
A VCC
2
IN OUT HEL_IO_MEM_2.8V B
ONNOFF_TO_BUF
R848
R808
150K
27p B GND
1K
3 3 4
SP17
SP18
R906
R905
GND Y 4 EN ADJ C831
TC7SZ08AFE MIC5219BM5
R807
200K
C829 C830
10u 470p 10u
U890
1 5
2
VDD VOUT HEL_PLL_1.5V
GND
3 4
CE NC C900
10u
VBAT R1111N151B-TR
R829
10
C ONNOFF_BUF U809 C
R827
47K
AVDD 1 5
2
IN OUT AVDD
R855
180K
GND
UMT2907A 3 4
U803 Q805
SPEAKER_EN EN ADJ
C855
MIC5219BM5
B4
B2
MAX4684EBC
R826
R857
270K
C856 C858 10u
0
MOTOR_BATT 10u 470p
V+
G1
C2 C4
HS_HF_SW IN1 NO1 HF_SPK_P
A2 A4
C SPK_VDD
IN2 NO2 HF_SPK_N R825 B Q804
R814 0 C3 C1
MOTOR_EN DTC144EE
C832
AUXOP COM1 NC1 2K 0.1u
E U810 LP3985IM5X-3.3
R812 A3 A1 1 5
AUXON COM2 NC2 USB_PWR VIN VOUT USB_VDD
GND
G2
0
2
C804 C807 GND
B1
B3
R813
10p 10p C808 100K

3 4
10p VEN BYPASS C861
R869 C863 10u
0.01u
D D
HEL_IO_MEM_2.8V
HEL_IO_MEM_2.8V
R868
10K
HEL_IO_MEM_2.8V Q809 UMC4N
R896
USB_DETECT
3
1K
R802
100K
2
2
1
R824
R801
100K
10K
R823
1
1K
C KEY_ROW1
UMC4N
Q808
AVDD STEREOJACK_DET B Q810
DTC144EE
E E
3
E
2
U805 R850
C806 DAI_TX R847 10K
B4
B2
MAX4684EBC 10u BAT_SENSE

R822
1
3
1K
R828
R804
C904
V+
G1
Q803 UMD2N
1K
15
C2 C4 HEL_IO_MEM_2.8V
IN1 NO1 HF_MIC 0.1u _RPWON C
R819
2
Q807
C810
A2 A4 B
220n
EAR_SPEAKER_SW IN2 NO2 R859 100 100

1 DTC144EE
1
R871 C3 C1 R803 0 2
AUXI COM1 NC1 E
UMC4N
Q806
10K
3
10K
470
220n
C821
A3 A1 C889 10uF 4
C819 COM2 NC2
R846
GND
5
G2
47p
6 CN802
0
R851
R862
B1
B3
25
C802 C813 VBAT_GND_1
26
SMF05C
1
3
4
47p 47p J801 VBAT_GND_2

D1
D2
D3
D4
D5
R881 0 R873 1
SP13
SP14
SP15
DAI_RX 2
BATT_ID
R816
D801
HF_MODE
GND
R882 0 R872 470 3

CAL_UART_DSR 4
DSR
F CHARGER F
2
PWR_+5V_1
R883 0 5
PWR_+5V_2
6
ON_SW1
R884 0 R888 0 7
HF_MIC 8
PCM_RXA_IN
HF_CALL_OFF_ON R870 470 PCM_CLK
R867 0 9
HF_SPK_N 10
PCM_SYNC
USB_RX
R864 0 11
HF_SPK_P 12
PCM_TXA_OUT
PWR_GND_1
R863 470 13
HEL_UART_PC_RX R861 470 14
RXD
CRS08
HEL_UART_PC_TX 15
TXD
D804
USB_TX
16
HEL_IO_MEM_2.8V
USB_PWR 17
USB_PWR
CAL_UART_DCD R860 470 DCD
18
U807 YMU762 RI_TMS
R892
R890
R889
R887
19
1 PWR_GND_2
11 R858 470 20
HPOUT_R CLK1 4 HEL_CLK_12M_OUT HEL_UART_PC_RTS RFR_RTS
C848
10 R856 21
_YMU762_RST DAI_SYNC
68n
_RST PWR_+4_2V_1
HPOUT_L 30 R854 22
R836 R835 C845 0.022u 12
A0
31
HEL_FADD(1) DAI_CLK R853 470 23
PWR_+4_2V_2
620
620
620
620
EQ1 _RD HEL_NFOE HEL_UART_PC_CTS CTS
29 24
G 8.2K 8.2K
13
_CS 5 HEL_NFCS_3 R833 0 R894 0 27
DTR G
EQ2 NC V_BAT_1
R817 28
V_BAT_2
28 29
R837
C847 _WR HEL_NFWE VBAT V_BAT_3

82K
3 30
390p _IRQ _YMU762_IRQ GND1
FB111
0
31
HEL_DATA(0:15) GND2
1000p
1000p
1000p
14 EQ3 27 U811 STF203-22
HEL_DATA(0:15)
HEL_DATA[0]
D0
2 26 HEL_DATA(1)
6 1
LED D1 USB_DP D+IC D+
R865
19 25 HEL_DATA(2)
MTR D2 C899 C867
SP10
SP11
24
SP22
SP29
SP26
SP28
SP20
SP27
SP21
SP19
SP25
SP30
5 2
33u 10u
SP2
SP4
SP3
SP1
HEL_DATA(3)
SP5
D3 VBUS GND
23
SMF05C
6
4
3
1
HEL_DATA(4)
D4
C859
C860
C862
R841
D5
D4
D3
D2
D1
17 22 HEL_DATA(5) 4 3
LOUD_SPKM SPOUT1 D5
21
USB_DM D-IC D-
HEL_DATA(6)
D803
C850 0 D6
GND
20 HEL_DATA(7)
47p D7
0
DTC_SENSE
2
R840 R834 3.3K C844 1000p
LOUD_SPKP 18
PLLC 6
0 SPOUT2
R876
R877
SPK_VDD C843 0.1u

VREF 9
15 SPVDD R818 0
IOVDD 32
USB_VDD
H C846 C849
Engineer:
H
10u 0.1u VDD 7 C828
DJ Jung COMPANY NAME
0.1u Address
16 Drawn by:
SPVSS VSS 8 City
mentor
A2
DOC CTRL CHK: AUDIO
12 1 8 A
MFG ENGR CHK:
mentor Friday, December 14, 2001 3:09:32 pm 4
1 2 3 4 5 6 7 8 9 10 11 12
- 134 -
9. CIRCUIT DIAGRAM

2 3 4 5 6 7 8 9 10 11 12
VTUNE
FL101
FL102 ENFVF382S18
L153
LDB25D500A0004A 100nH
13
C121 VREG3
1 7
4
27p
GND4
RF_1 VT
NC1
5 B1 2 8
3
G2 GND1 GND3
3 9
2
6 NC2
C122 UB1 RF_2 VCC
C110
7 4 10
LBSW
1
27p B2 G1 C103 RF_3 SW_1 10u
UB2
C102
GND5
C104 5 11
47p HBSW
FB112
GND2 SW_2
0F 0F 6 12
8
RF_4 TX_RX_SW TRXSW
14
R107 VBAT
VTUNE
47 C105
C116 C118 C117 C124 C106
47p
220p 8200p 220p 0F 0F
R110
C125 C130 C154 C153
120 470p 1000p 1000p 470u
R111
R109 1.8K
3.3K
N101
U101 18 17 3 6 16 15 14 13
L150 LDC15D190A007A
R113 PF08107B
VDD1
VDD2
C133
GND10
GND9
GND8
GND7
GND6
GND5
R106
10nH 47p 8 1
470 C191 C119 COU_OUT IN1
100nH 3G 10p 1 4 7 2
47p B_OUT1 GND1 R119
L191 GSM_1 GSM_0 6 3
C115 DCS_0 GND2 IN2 68
4.7u 3.3nH C186 18p 8 DCS_1 5 5 4
B_OUT2 TERM
GND4
GND3
GND2
GND1
VAPC
C123
VCTL
C132
10p 7p
R114 R133
C120
12
11
10
9
7
2
VREG3 R115 470 R134 30 R135 C150 27p
3G VBAT_RF 180 180 47p
C111 C129 100nH R120
4.7u 4.7u C134
C113 R136 R112 220
22p
0.1u 0
C127 C126 0
R117
0.1u 0.1u C128 82
4.7u
DETD
HBSW
VAPC
VAPC DETR
DETR
0F
C107
LBSW R116 C131
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
300K 1.5nH
HBSW 33p R103 C135
C136
TRXSW 7p
GND
LBSW
VCC5
VREG3
VBAT3
R3
TXRXCP
R2
MAIN_SPUP2
GND_TXCP
VCC6
RX_LOP
RX_LON
VCC4
OMIXRF
VBAT1
VREG1
51
C198
C199
1.2p
0F
L106 C159
1 48 47p SW101
C188 HBSW VAPC 1.5nH FL104 D101 KMS-502
C112 3G 2 47
0F TXRXSW FILT SAFSD1G84CB0T00 BAT15-05W
4.7u 3G 3 46
C114 0.1u 4
VCC10 DETD
45 R138
DETD C162
C170 2.2nH
MAIN_SPUP1 DETR DETR C160 O1 IN L152 L151
5 44 L107 0F 4 2 G1
MAIN_CP DCS_INAN 1.5nH 47p O2
ANT
6 43 6 G1 G2 G3
RF G2
VBAT_RF R105 100nH VBAT2 DCS_INAP C168 C172
C141 7 42 47p 0 OUT101
1
3
5
3G VREG2 U105 VCC3 0F 0F C109
4.7u 8 41 FL103
PA_LEVEL R126 0 APC TRF6150PAP PCS_INAN C161 0F 0F
9 40 SHS-M090B 4
PA_ON R125 1K APCEN PCS_INAP L101
10 39 15nH
ANT
VRIO R127 0 VR4IN GND_INA 15nH
R124 1K TP111 11 38 C155 0F L102
TSPCLK 12
CLK VCC2
37 3
TSPDATA R123 1K TP110 DAT GSM_INAN 8 DCS_TX GND1
R128 1K TP109 13 36 10 EGSM_TX GND2 5
TSPEN C146 1000p 14
EN GSM_INAP
35 C156 2.2p 9
CRF 15
AUX_CP MAINVCO
34 FL105 GND3
11
VR4I VCC9 VCC1 L103 C166 C171 GND4
16 33 SAFSD942MCL0T00 C192 12
C145 CRF VCC8 12nH 47p 3.9nH 47p 6 DCS_RX GND5
DECRX_MIN
AUX_VCON
AUX_VCOP
C144 13
TEST_VCO
RX_MIXQN
RX_MIXQP
2
BANDGAP
O1 IN
BIAS_REF
27p EGSM_RX GND6
RX_MIXIN
RX_MIXIP
0.1u 4 2
RESETZ
O2
6 C173
VCC7
G1 G2 G3
VC1
VC2
C158 C157 C163 C165 C169
QN
QP
0F
1
3
5
0F 47p 0F
IN
IP
0.1u 0.1u
C164 1 7
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
L108
2.2p L104
4.7nH
R129 12nH
RESETCL TP101 VC2
1K TP102 VC1
C143 QM C182 D102
12p QP C180 0.1u C138 C137
0F HVC369B
IM 27p 27p
IP C151 C152
1000p 1000p L105
3.9nH_1608
L110 L109
R140
C175 6.8nH_1608 6.8nH_1608 C167
2.2K
1.5n_1608 1.2n_1608
R141 C179
C174 0 0.1u
10n_2012 C185 U102
22p NC7WZ02K8X
R145
1K HBSW 1 A1 VCC 8 VREG3
D103 C184 2 7
SMV1233-074 C176 R139 TRXSW B1 Y1 VC2
18n_3216 VC1 3 Y2 B2 6 LBSW
12p R144 1.5K
4 5
2
C181 C189 TRXSW

A2
GND A2
9.76K_1%
CAT
0F 0F
3
1
A1
C178 C177
R137
0F 12p 680
R142 R143 RADIO_TEMP
2.2K 2.2K C183 R121
1.2n_1608
150K
C140 TP120
R132
CLK13M 4 Y GND 1000p TCXO_EN
3
A
2 CRF 0
VCC NC
5 1
U103
TC7SZ04AFE
VR4I C149
0.1u 0.01u
1 5
R122
C139 VEN BYPASS
R913 X101 2
GND
13MHz
1K 0
3 4 3 4
OUT VCC VOUT VIN VBAT_RF
R130
2 1
GND VCONT C147 U104 C148
2.2u LP3985IBPX-2.8 2.2u
C142
R131
0
1u
TP119
AFC PT101 0
RADIO_TEMP
U8000 R182
Engineer:
R181 15K COMPANY NAME
Drawn by: Address
R180 5.1K R183
City
A2
DOC CTRL CHK: GPRS
12 1 8 A
MFG ENGR CHK:
mentor Monday, December 10, 2001 3:07:35 pm 3
2 3 4 5 6 7 8 9 10 11 12
- 135 -
9. CIRCUIT DIAGRAM
Keypad PCB Circuit (1/1)

1 2 3 4 5 6 7 8 9 10 11 12
KEY_ROW4
KEY_ROW3
KEY_ROW2
KEY_ROW1
KEY_ROW0
V2.8
A A
V2.8
VBAT
V1.8
10K
10K
10K
10K
R8
R9
R7
2K
R6
R5
CN1
1
2
KEY_COL0
B 3
PC_UART_CTS B
4
PC_UART_RTS
5 HEL_TMS
6
HEL_TCK V1.8 V2.8
7
HEL_TDO
8 HEL_TDI
9
HEL_NTRST CN2
10
HEL_EMU1 1
HEL_EMU0 KB23 KB24 KB20 KB1 KB13
11 2
12
KEY_LED- 3
13
KEY_COL5 4
EAR_PIECEP _END_ONOFF
14
KEY_COL4 5
LOUD_SPKP
15
KEY_COL3 6
16
KEY_COL2 7 R15 270 KEY_COL1
17
KEY_COL1 8
EL_ONOFF
18
KEY_COL0 9
19 10 R14 270
20
MAIN_LCD_CS 11 R16 270
UWIRE_SDO
21
MAIN_LCD_CLK 12
SUB_LCD_CD_SEL
22 13 R18 270 SUB_LCD_RES
C 23
SUB_LCD_CS 14 R19 270
MAIN_LCD_DATA C
24
UWIRE_SCLK 15
MAIN_LCD_CD_SEL
MAIN_LCD_RES KB21 KB6 KB9 KB14
25 16
26 17 R21 270
27
MAIN_LCD_LED+ 18 R22 270
MAIN_LCD_CS
28 19
MAIN_LCD_CLK
29
LOUD_SPKM 20 R23 270
30
EAR_PIECEM 21 R24 270 SUB_LCD_CS KEY_COL2
31
MOTOR_BATT 22
UWIRE_SCLK
32 23
33 EAR_PIECEP 24
34
LOUD_SPKP 25
35 26
MAIN_LCD_LED+
36 27
37
EL_ONOFF 28
LOUD_SPKM
38 29
EAR_PIECEM
UWIRE_SDO KB4 KB5 KB19 KB7
39 30
40
SUB_LCD_CD_SEL MOTOR_BATT
41
SUB_LCD_RES
42
MAIN_LCD_DATA
D 43
MAIN_LCD_CD_SEL D
44
MAIN_LCD_RES KEY_COL3
45
KEY_ROW4 R17 C12 C14
KEY_ROW3 C4 C6 C8
46
47 KEY_ROW2 47p 47p 47p 10K 47p 47p
48
KEY_ROW1
49
KEY_ROW0 R20
_END_ONOFF C5 C9 C11 C13 C15
50
51 47p 10K 47p 47p 47p 47p
52 KB17 KB10 KB22 KB3
53
HEL_FOLDER_DET
54
CAL_NTRST
55
CAL_TDI
56
CAL_TDO
57
CAL_TCK
58
CAL_TMS KEY_COL4
59
PC_UART_RX
60
PC_UART_TX
61
62
E 63
E
64
KB26 KB15 KB11 KB12
KEY_COL5
F F
VBAT
V2.8
G R11 G
HEL_FOLDER_DET
51K
C1
10p
A3212ELH 1
OUT 2
LD13
LD14
LD15
LD10
LD11
LD12
LD16
LD3
LD1
LD2
LD4
LD5
LD6
LD7
LD8
LD9
C2
U1
VDD
0.1u C3
0.1u
GND
3
R1
R2
R4
R3
39
39
39
39
KEY_LED-
H Engineer:
H
Y. J . SEOK COMPANY NAME
Drawn by: Address
Y. J . SEOK City
A2
DOC CTRL CHK: KEYPADS
12 1 8 A
MFG ENGR CHK:
mentor Thursday, December 13, 2001 7:30:44 pm 10
1 2 3 4 5 6 7 8 9 10 11 12
- 136 -
9. CIRCUIT DIAGRAM
SIM PCB Circuit (1/1)
CN1
J1 1
1 6 2
VCC GND
2 5 3
RST VPP
3 4 4
CLK I_O
5
6
7
8
9
10
- 137 -
10. PCB LAYOUT
10. PCB LAYOUT
Main PCB Layout (1/2)
- 138 -
10. PCB LAYOUT
Main PCB Layout (2/2)
- 139 -
10. PCB LAYOUT
Keypad PCB Layout (1/2)
- 140 -
10. PCB LAYOUT
Keypad PCB Layout (2/2)
- 141 -
10. PCB LAYOUT
SIM PCB Layout (1/2)
- 142 -
10. PCB LAYOUT
SIM PCB Layout (2/2)
- 143 -

LG G8000 Service Manual

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LG G8000 Service Manual

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2.

2.1 H/W Features

2.2 Technical Specification

Item Description Specification

Item Description Specification

Item Description Specification

Figure 3-1. RF front-end circuit

3.1.1 RF front end

Table 3-1. The logic and current

3.1.2 Demodulator and Baseband Processing

3.1.3 DC offset compensation

Figure 3-2. RX path block diagram

Table 3-2. Gain and Noise Figure of RX path

Ant. switch RF SAW Filter I,Q demodulator (LNA+Mixer)

Table 3-3. Total Gain and Noise Figure of RX path

Total Gain Total Noise Figure

Table 3-4. 3-wire BUS of Synthesizer in the TRF6150

Pin Number Description

Dual band VCO :

6 bits 3bits 8/9

Figure 3-3. Synthesizer internal Block Diagram

C175 D102 C156

Figure 3-4. Synthesizer circuit

Figure 3-5.Transmitter Block Diagram

TXRXCP R2 MAINSPUP2 CLK DATA EN

PWR_SW DCS_SW GSM_SW C117 R109

Figure 3-6. Tx IF Modulator and OPLL Circuit

3.3.3 Power Amplifier

C107 R138 45 DETR

C134 R117 U105

Figure 3-7. Power Amplifier and its Control Part Circuits

3.3.4 PA Circuit and Control

3.4 13 MHz Clock

R913 R131 AFC

Figure 3-8. VCTCXO Circuit

3.5 Power Supplies and Control Signals

Table 3-5. Regulator Specification

Regulator Voltage Powers Enable Signal

PT101 R181 R183

Figure 3-9. External Regulator Circuit

3.6 Digital Baseband (DBB) Processor

Figure 3-10. Top level block diagram of the Calypso G2 (HERCROM400G2)

3.6.1 General Description

3.6.2 Block Description

• ARM7TDMI CPU core

Memory Interface : External/Internal Memory Interface

3.6.3 External Devices connected to memory interface

3.6.4 RF Interface (TPU, TSP block)

TSP (Time Serial Port)

3.6.5 SIM interface

Table 3-8. SIM Interface

SIM (Interface between DBB and ABB)

20K Naucica 20K

Figure 3-11. SIM Interface

3.6.6 UART Interface

Table 3-9. UART Interface Specification

UART MODEM (UART1)

3.6.7 GPIO map

Table 3-10. GPIO Map Table

I/O # Application I/O Resource Inactive State Active State

3.7 Analog Baseband (ABB) Processor

3.7.1 General Description

3.7.2 Audio Signal Processing & Interface