1

3 March 2009 1
Interconnect delay
Lumped RC model
Charge V
in
to V
DD
The transient output voltage is
|
|

\
|
=

RC
t
DD out
e V t V 1 ) (
|
|

\
|
=

RC
t
DD
DD
e V
V
1
2
|

\
|
=
2
1
ln
RC
t
dlh
RC t
dlh
69 .
3 March 2009 2
Interconnect delay
More accurate than lumped RC model
More difficult to solve for large N
Need full-scale SPICE simulation
3 March 2009 3
Elmore Delay
Single line model not useful for generalized
RC tree networks
R
1
C
1
s
R
2
C
2
R
4
C
4
C
3
R
3
C
i
R
i
1
2
3
4
5
3 March 2009 4
RC-tree property:
Unique resistive path between the source node
s and any other node i of the network path
resistance R
ii
Example: R
44
=R
1
+R
3
+R
4
R
1
C
1
s
R
2
C
2
R
4
C
4
C
3
R
3
C
i
R
i
1
2
3
4
5
Elmore Delay
3 March 2009 5
RC-tree property:
Extended to shared path resistance R
ik
:
Example: R
54
=R
1
+R
3
R
52
=R
1
)]) ( ) ( [ ( s.t. k s path i s path R R R
j j ik
=

R
1
C
1
s
R
2
C
2
R
4
C
4
C
3
R
3
C
i
R
i
1
2
3
4
5
Elmore Delay
3 March 2009 6
Assuming:
Each node is initially discharged to ground
A step input (pulse) is applied at time t=0 at node s
The Elmore delay at node i is:
It is an approximation: it is equivalent to first-order
time constant of the network
Proven acceptable
Powerful mechanism for a quick estimate

=
=
N
k
ik k Di
R C
1

Elmore Delay
2
3 March 2009 7
Elmore Delay
Examples
4 1 3 3 2 1 2 2 1 1 1 3
) ( ) ( C R C R R R C R R C R t
d
+ + + + + + =
4 4 1 3 1 2 1 1 1 4
) ( C R R C R C R C R t
d
+ + + + =
3 March 2009 8
Elmore Delay

= =
=
j
k
N
j
d
N
R
N
C
t
1 1
|

\
| +
=
+
=
N
N
RC
N N
N
R
N
C
2
1
2
) 1 (
for
RC
t
d
2
= N
3 March 2009 9
Interconnect Delay
Fanout Effects
Lines with multiple loads will have longer delays
Clocks
Data buses
Control lines
Solutions
Wider lines for special signals
Buffers
3 March 2009 10
Delay is proportional to the square of the
length
Try to avoid long lines
Interconnect Delay
2
RC
t
d
=
( ) )) ( 2 (
2
1
w l c lw c r
p a w
l
+ + =
2
2
1
l rc
a

3 March 2009 11
Interconnect resistance
Interconnect capacitance
Intrinsic load capacitance
Propagation delay
Interconnect Delay
= = 700
5 . 0
5000
07 .

R
fF C
wire
515 ) 5 . 0 5000 ( 2 044 . 5 . 0 5000 03 . = + + =
fF C
in
5
ps fF
fF
RC
RC
t
in
wire
p
184 5 700
2
515 700
2
= |

\
|
+

= + =
C
a
lw + 2C
p
(l+w)
r.l/w
3 March 2009 12
Avoid long interconnect delays using buffers
Interconnect resistance
Interconnect capacitance
Intrinsic load capacitance
Propagation delay
Interconnect Delay
= = 350
5 . 0
2500
07 .

R
fF C
wire
258 ) 5 . 0 2500 ( 2 044 . 5 . 0 2500 03 . = + + =
fF C
in
5
ps fF
fF
RC
RC
t
in
wire
p
94 5 350
2
258 350
2
2
= |

\
|
+

= + =
3
3 March 2009 13
Avoid long interconnect delays using wider lines
Interconnect resistance
Interconnect capacitance
Intrinsic load capacitance
Propagation delay
Interconnect Delay
= = 70
5
5000
07 .

R
fF C
wire
1190 ) 5 5000 ( 2 044 . 5 5000 03 . = + + =
fF C
in
5
ps fF
fF
RC
RC
t
in
wire
p
42 5 70
2
1190 70
2
= |

\
|
+

= + =
3 March 2009 14
Switching Delay
The intrinsic delay of a gate
Transistor sizing can affect the delay
Extrinsic capacitances can affect the delay
3 March 2009 15
Delay Definitions
3 March 2009 16
Switching Delay
Fall time analysis
3 March 2009 17
Saturation Mode
Fall time analysis
DS C
I I =
2
) (
2
tn DD
n
out
L
V V
k
dt
dV
C

=
out
tn DD n
L
dV
V V k
C
dt
2
) (
2

=
out
V
V V
tn DD n
L
f
dV
V V k
C
t
DD
tn DD

=
9 .
2 1
) (
2
2 1
) (
) 1 . (
2
tn DD n
DD tn L
f
V V k
V V C
t

=
3 March 2009 18
Fall time analysis
Linear Mode
DS C
I I =
(

=
2
) (
2
out
out tn DD n
out
L
V
V V V k
dt
dV
C
out
out out tn DD n
L
dV
V V V V k
C
dt
) ) ( 2 (
2
2

=
) ) ( 2 (
2
2
1 .
2
out tn DD out
out
V V
V
n
L
f
V V V V
dV
k
C
t
tn DD
DD

4
3 March 2009 19
Fall time analysis
Linear Mode
tn DD
DD
V V
V
out tn DD
out
tn DD n
L
f
V V V
V
V V k
C
t

|
|

\
|

=
1 .
2
) ( 2
ln
) (
|
|

\
|

=
DD
tn DD
tn DD n
L
V
V V
V V k
C 20 19
ln
) (
3 March 2009 20
Fall time analysis
|
|

\
|
|
|

\
|
+

=
DD
tn DD
tn DD
DD tn
tn DD n
L
V
V V
V V
V V
V V k
C 20 19
ln
) 1 . ( 2
) (
2 1 f f f
t t t + =
|

\
|
+

= ) 20 19 ln(
1
) 1 . ( 2
) (
n
n
n
V V k
C
tn DD n
L
DD
tn
V
V
n =
|

\
|
+

= ) 20 19 ln(
1
) 1 . ( 2
) 1 (
1
n
n
n
n
K
DD n
L
f
V k
C
K t =
3 March 2009 21
Fall time analysis
Fall time is proportional to load capacitance
and inversely proportional to V
DD
and k
n
Decreasing the supply voltage will increase
the fall time
Increasing the transistor width will increase
k
n
which will reduce the fall time
Changing these three parameters can cause
conflicting goals
3 March 2009 22
Rise time analysis
|
|

\
|
+

= ) 20 19 ln(
1
) 1 . ( 2
) 1 (
p
p
p
p V k
C
t
DD p
L
r
|
|

\
|
+

= ) 20 19 ln(
1
) 1 . ( 2
) 1 (
1
p
p
p
p
K
p
DD
tp
V
V
p

=
DD p
L
p r
V k
C
K t =
3 March 2009 23
Rise time analysis
For equal fall times and rise times
r f
t t =
DD p
L
p
DD n
L
n
V k
C
K
V k
C
K =
p n
K K =
|
|

\
|
= |

\
|
L
W
C
L
W
C
p
ox p
n
ox n

3 2 =
p
n
n
p
W
W

V
tn
= V
tp
3 March 2009 24
Propagation Delay
As with interconnect delay, find the
equivalent resistance and load capacitance
of the transistor
L eq pHL
C R t 69 . =
5
3 March 2009 25
Propagation delay is the time for voltage to
reach half way point - so integrate from V
DD
to V
DD
/2
For the output range we are interested in,
the transistor is always in saturation
Propagation Delay

= =
2
1 ) (
) ( 1
)) ( (
1 2
t
t
DS
DS
on eq
t I
t V
t t
t R avg R
DS
V
V
DS
DS
DD
V eq
dV
t I
t V
V
R
DD
DD DD

=
2
2 ) (
) ( 1
DS
V
V
DS DSAT
DS
DD
eq
dV
V I
V
V
R
DD
DD

=
2
) 1 (
2

3 March 2009 26
Propagation Delay
DS
V
V
DS DSAT
DS
DD
eq
dV
V I
V
V
R
DD
DD

=
2
) 1 (
2

DD
DD
V
V DS DS
SAT DD
V V
I V
2 2
)) 1 ln( (
2

+ =
DD
DD
V
V
DS DS
DS DS
SAT DD
V V
V V
I V
2
3 3 2 2
2
3 2
2
|
|

\
|
|
|

\
|
+ =

DD
DD
V
V
DS DS
SAT DD
V V
I V
2
3 2
3 2
2
|
|

\
|
+ =

|
|

\
|
+ =
24
7
8
3 2
3 2
DD DD
SAT DD
V V
I V

\
|

DD
SAT
DD
V
I
V

9
7
1
4
3
3 March 2009 27
Propagation Delay
Load capacitance
3 March 2009 28
Propagation Delay
Load capacitance
Intrinsic capacitance - sum of capacitances at
drain - C
GD
+ C
DB
3 March 2009 29
Propagation Delay
Intrinsic capacitance
C
GD
is composed solely of overlap capacitance
The transistors are either in cutoff or in saturation, so no
channel capacitance exists
The actual load capacitance relative to ground is 2C
GDO
because of Miller effect
Miller effect accounts for an increase in the equivalent input
capacitance of an inverting voltage amplifier due to amplification
of capacitance between the input and output terminals
3 March 2009 30
Propagation Delay
Extrinsic capacitance is composed of wire
capacitance and input capacitance of fanout
Input capacitance is composed of overlap
capacitance and channel capacitance
Overlap capacitance is C
GDO
+ C
GSO
(very small)
Channel capacitance is C
ox
WL. Assume worst case
) 2 2 ( 69 . 0
ext DBp DBn GDOp GDOn eq pLH
C C C C C R t + + + + =
6
3 March 2009 31
Propagation Delay
All capacitances are roughly proportional to
W
Equivalent resistance is inversely
proportional to W