MANIPAL INSTITUTE OF TECHNOLOGY

(A constituent college of Manipal University, Manipal)

Manipal Karnataka 576 104

DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGG.

COURSE PLAN (ECE 553) Department Subject Semester & branch Name of the faculty No of contact hours/week : Electronics & Communication Engg. : VLSI Testing & Testability : 2nd semester, M.Tech. : GP :4

Assignment portion Assignment no. 1 2 3 4 5 Test no. 1 2 Submitted by: Guruprasad (Signature of the faculty) Date: 17 -01-2014 Approved by: Dr. K. Prabhakar Nayak (Signature of HOD) Date: 17 -01-2014 Topics L1 L10 L11 L20 L21 L30 L31 L40 L41 L48 Test portion Topics LECTURE 1 22 LECTURE 23 44

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At the end of this course, student will be able to:

CO1: Describe the different types of testing, testing process and its significance. CO2: Discuss and analyze different types of faults and prepare models for the same. CO3: Derive test vectors for finding stuck at faults in combinational circuit using various types of structural and algebraic algorithms. CO4: Derive test vectors for finding stuck at faults in sequential circuit using structural algorithm and state table verification method. CO5: Discuss and compare various Design for Testability techniques. CO6: Derive compressed output for combinational circuit for Self test using different methods. CO7: Describe various BIST architectures for improving testability. CO8: Discuss analog testing using DSP based and Model based approaches.

Lecture no.

Topic to be covered Introduction

1 2 3 4 5

Introduction to testing and testability, Need for testing, digital and analog testing Design-for-test (DFT), Test process Controllability Observability ATE, Test economics. Fault Models

6 7 8 9

Fault modeling: Introduction to faults in digital circuits, Stuck-at faults Bridging faults Iddq faults, delay faults, intermittent faults

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Testing of Combinational Circuits 10 11 12 13 14 15 16 17 18 19 20 21 Various types of faults. Functional v/s structural approach to testing, test vector generation for a single stuck-at-fault in combinational logic Fault table method Boolean difference method Boolean difference method contd Path sensitization method D-algorithm D- Algorithm contd... FAN algorithm PODEM algorithm SOCRATES Recursive learning, Fault coverage Test optimization, Design for Testability 22 23 24 25 26 27 28 29 30 Need for enhancing controllability through the addition of DFT hardware Need for enhancing observability through the addition of DFT hardware Partitioning method Partitioning contd... Adhoc method Adhoc method contd... Various scan design approaches Scan-path testing Boundary scan.

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BIST-Test vector Generation 31 32 33 34 35 36 37 Test pattern generation for sequential circuits Exhaustive method Non-exhaustive method Pseudorandom test pattern generation, Delay fault testing Testing with random patterns. LFSR concept Random test generation and response compression BIST-Output analysis 38 39 40 41 42 43 44 Built-in self test (BSIT) Input compression Output compression Arithmetic Reed-Muller and spectral coefficients Reed-Muller and spectral coefficients contd... Coefficient test signatures Signature analysis Online self test. Analog Testing 45 46 47 48 Analog testing: DSP based analog test Model based analog test Testing techniques for Filters A/D Converters.

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References: 1. M. Abramovici, M. A. Breuer, and A.D. Friedman, "Digital Systems Testing and Testable Design", Piscataway, New Jersey: IEEE Press, 1994. 2. M. L. Bushnell and V. D. Agrawal, "Essentials of testing for digital, memory and mixed-signal VLSI circuits", Boston: Kluwer Academic Publishers, 2000. 3. Miczo, "Digital Logic Testing and simulation". New York: Harper & Row, 1986. 4. Krstic and K-T Cheng, "Delay Fault Testing for VLSI Circuits", Kluwer Academic Publishers, 1998. 5. P.K. Lala, "Fault Tolerant & Fault Testable hardware Design", BS Publications, 1998 6. Stanley L. Hurst, VLSI Testing: digital and mixed analogue digital techniques Pub:Inspec/IEE, 1999.

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