CURRICULUM VITAE of LUCA DANIEL

77 Massachusetts Ave #36-849, Cambridge, MA 02139 Email: luca@mit.edu Phone: (617) 253-2631 http://www.rle.mit.edu/cpg/

RESEARCH INTERESTS:
Model order reduction and parameterized model order reduction for linear and nonlinear dynamical systems. Mixed-signal, RF, and mm-wave analog circuit design and robust optimization in the presence of process variations. Simulation, modeling and design methodologies for noise immune analog RF, mixed-signal electronic circuits. Fast electromagnetic integral equation solvers, on-chip parasitic extraction. Simulation, modeling, design optimization and fabrication of on-chip air-core RF inductors and magnetic core inductors and transformers for power electronics converters. Application of numerical techniques to the simulation and modeling of emerging and interdisciplinary technologies (nanoelectronics, bioMEMS, epidemiology).

EDUCATION:
Ph.D. in Electrical Engineering and Computer Science at University of California, Berkeley, June 2003. Major: Computer Aided Design and Integrated Circuits. Minors: Electromagnetics, Computational Applied Mathematics. GPA 4.0/4.0 Advisor: Prof. Sangiovanni-Vincentelli. Dissertation title: Development of simulation techniques and design methodologies for Signal Integrity and Electromagnetic Interference of high-speed electronic circuits. Univ. of Illinois Urbana-Champaign. Certificate of professional development: Electromagnetic Modeling and Simulation Methodologies for High-Speed Electronics. Aug 1999. M.S. (Laurea) GPA 110/110 summa cum laude in Electronic Engineering from Universita di Padova, Italy, July 1996. Dissertation title: Design and microfabrication of on-chip magnetic core inductors for high-frequency DC/DC converters.

AWARDS AND HONORS:

ACM Outstanding Ph.D. Dissertation Award in Electronic Design Automation, 2003, for the most substantial contribution to the theory or application in the field of Electronic Design Automation. David J. Sakrison Memorial Prize from the Dept. of Electrical Engineering and Computer Science at UC Berkeley, for a truly outstanding piece of research as deemed by a faculty committee," (referring to the PhD thesis), May 2003. Best Paper Award, at the 39th IEEE/ACM Design Automation Conference, New Orleans, June 2002. SRC International Graduate Fellow, 2001. Only one international fellow chosen for that year. Bernard Friedman Memorial Prize in Applied Mathematics, from the Department of Mathematics, UC Berkeley, for demonstrated research ability in applied mathematics, May 2001. UC Berkeley Computer Aided Design Fellowship Award. December 2000. IBM Corporation Prize Paper Award at the IEEE Electrical Performance of Electronic Packages Conference, Scottsdale, AZ, October 2000. Best paper in session award, and laptop prize for best overall presentation, at the Semiconductor Research Corporation TECHCON 2000 Conference, Phoenix AZ, September 2000. IEEE Power Electronics Society 2000 Prize Paper Award for the best paper in IEEE Transactions on Power Electronics for the year 1999. University of California Regents Fellowship for distinguished academic record, 1997/98. Educational Abroad Program fellowship and tuition from UC Berkeley, 1994/95. Ing. Aldo Gini Foundation, Padova Italy one year fellowship to study abroad, 1994/95. Fellowship and tuition from University of Padova, Italy as best electrical engineering student for both academic years 1992/93 and 1993/94.

ACCEDEMIC AND RESEARCH EMPLOYMENT HISTORY:

Assistant Professor of Electrical Engineering and Computer Science at the Massachusetts Institute of Technology (M.I.T.), Cambridge, MA. 7/03-present. Lecturer of Electrical Engineering and Computer Science at M.I.T., Cambridge, MA. 1/03-5/03. Internship, Cadence Berkeley Research Labs, Berkeley, CA. 5/01 8/01. Developed a guaranteed passive fullwave Model Order Reduction algorithm for large and distributed interconnect networks (U.S. patent pending). Graduate Student Teaching Assistant at UC Berkeley, 9/98 12/98 for the graduate class on Simulation of Electronic Circuits at UC Berkeley. Internship, Hewlett Packard Research Labs, Palo Alto, CA. 5/98 8/98. Simulation of conducted interference from IC packages to match measured data. Estimation of return current paths on PCBs. Prediction of radiated electromagnetic interference. Graduate Student Research Assistant, Electronic Research Lab, UC Berkeley. 8/95 4/98. Development of a design methodology and microfabrication process for on-chip magnetic core inductors used in high frequency DC/DC power converters. Design and fabrication of a power filter for a 60 kW PWM power inverter for a hybrid-electric vehicle. Test of the control circuitry of the inverter.

PROFESSIONAL SERVICE:
Technical Program Committee ACM/IEEE Design Automation and Test in Europe Conf. Jan03 present Technical Program Committee ACM/IEEE 40th Design Automation Conf. Jan03 - Jun03 Technical Program Committee ACM/IEEE 23rd Intern. Conf. on Computer Aided Design Sept05 - present Best Paper Award Committee ACM/IEEE 40th Design Automation Conf. Jan03 - Jun03 Best Paper Award Committee ACM/IEEE Asia South Pacific Design Automation Conf. Nov04 - Jan05 Session Chair, Nonlinear Model Order Reduction, ACM/IEEE 40th Design Automation Conf. Jun03 Session Chair, Model Reduction & Variational Parasitic Analysis ACM/IEEE 41st Design Automation Conf. Jun04 Jun04 Session Chair, Interconnect EMC and Packaging Modeling ACM/IEEE Design Automation and Test in Europe Conf Mar05 - Mar05 Session Chair, Oscillator Analysis ACM/IEEE 23rd Intern. Conf. Computer Aided Design Nov05 - Nov05 Session Chair, Power Grid & Large Interconnect Analysis ACM/IEEE Design Automation and Test in Europe Conf. Mar06 - Mar06 Session Chair for the 41th ACM/IEEE Design Automation Conference, San Diego, CA, June 2004. Society Membership: The Institute of Electrical and Electronics Engineers, (IEEE) member since 1998.

TEACHING EXPERIENCE
MIT 2.096J/6.336J/16.910J Introduction to Numerical Simulation (Fall04, Fall05, Fall06) MIT 6.003 Signals and Systems (Spring03, Spring04, Spring05, Spring06) MIT 6.041 Probabilistic Systems Analysis (Fall03) MIT Model Order Reduction Seminar (Fall05, Spring06)

EXTRA CURRICULAR ACTIVITIES:

2003-present. Tenor in the MIT Renaissance Choir Meridians, Cambridge, MA. 2001-present. Member of the MIT Ballroom Dance Competition Team. 2000-2001. Co-founder of the IISA Italian International Student Association at UC Berkeley. 1995-1996. Elected Council Member for the UC Berkeley International House (600 residents). 1995-1996. Elected International Students Representative Campus Safety Committee of UC Berkeley. 1992-1994. Tenor in the choir Bach of Padova, Italy. 1988-1991. Active member of the Italian Red Cross. Ambulance service, teaching assistance in first aid classes, training and coordination with the Fire Department

JOURNAL ARTICLES AND PATENTS:

L. Daniel, C. S. Ong, S. C. Low, K. H. Lee, J. White, "A Multiparameter Moment Matching Model Reduction Approach for Generating Geometrically Parameterized Interconnect Performance Models", IEEE Transaction on Computer Aided Design, Vol 23, No 5, May 2004. J. Phillips, L. Daniel, Method and System for Modeling Distributed Time Invariant Systems. 2003, (U.S. Patent 10/326,4300.) J. Phillips, L. Daniel, L. M. Silveira, "Guaranteed Passive Balancing Transformations for Model Order Reduction", IEEE Transaction on Computer Aided Design, Vol 22, No 8, Aug 2003. L. Daniel, C. R. Sullivan and S. R. Sanders. Design of Microfabricated Inductors, IEEE Transactions on Power Electronics, Vol. 14, No. 4, July 1999. (Best journal paper for the year 1999).

CONFERENCE PAPERS:
L. Daniel, C. R. Sullivan and S. R. Sanders, "Design of Microfabricated Inductors", in Proceedings of the 27th Annual IEEE Power Electronics Specialists Conference, Baveno, Italy, June 1996. L. Daniel, A. Sangiovanni-Vincentelli, J. White, "Electromagnetic Modeling using Conduction Modes as Global Basis Functions", in Proceedings of the IEEE 9th Topical Meeting on Electrical Performance of Electronic Packages, Scottsdale, AZ, 23-25 October 2000. (IBM Corporation Prize Paper Award). L. Daniel, A. Sangiovanni-Vincentelli, J. White, "Using Conduction Modes for Efficient Electromagnetic Analysis of on-Chip and off-Chip Interconnect", IEEE/ACM 38th Design Automation Conference, Las Vegas, 18-22, June 2001. L. Daniel, A. Sangiovanni-Vincentelli, J. White, "Techniques for Including Dielectrics when Extracting Low-Order Models of High Speed Interconnect". IEEE/ACM International Conference on Computer Aided Design, San Jose, CA. November 2001. L. Daniel, C. S. Ong, S. C. Low, K. H. Lee, J. White, "Geometrically Parameterized Interconnect Performance Models for Interconnect Synthesis", IEEE/ACM International Symposium on Physical Design, San Diego, May 2002. J. Phillips, L. Daniel, L. M. Silveira, "Guaranteed Passive Balancing Transformations for Model Order Reduction", IEEE/ACM 39th Design Automation Conference, New Orleans, Jun 2002. (Best Conference Paper Award). L. Daniel, J. Phillips, "Model Order Reduction for Strictly Passive and Causal Distributed Systems", IEEE/ACM 39th Design Automation Conference, New Orleans, Jun 2002. L. Daniel, A. Sangiovanni-Vincentelli, J. White, "Proximity Templates for Modeling of Skin and Proximity Effects on Packages and High Frequency Interconnect", IEEE/ACM International Conference on Computer Aided Design, San Jose, Nov 2002. X. Hu, L. Daniel, J. White, "Partitioned conduction modes in surface integral equation-based impedance extraction," Proceedings of the IEEE Topical Meeting on Electrical Performance of Electrical Packaging, p 355-8, Oct. 2003.** L. Daniel, J. White, "Automatic generation of geometrically parameterized reduced order models for integrated spiral RF-inductors", Proceedings of the 2003 IEEE International Workshop on Behavioral Modeling and Simulation, p 1823, San Jose, CA, Oct. 2003. A. Nardi, H. Zeng, J. Garrett, L. Daniel, A. Sangiovanni-Vincentelli, "A Methodology for the Computation of an Upper Bound on Noise Current Spectrum of CMOS Switching Activity", IEEE/ACM International Conference on Computer Aided Design, p 778-85, San Jose, CA, Nov 2003. L. Daniel, J. White, Numerical techniques for extracting geometrically parameterized reduced order interconnect models from full-wave electromagnetic analysis, Proceedings of the IEEE Antennas and Propagation Society Symposium, Apr. 2004. T. Klemas, L. Daniel, and J. White, "A Fast Full-Wave Algorithm to Generate Low Order Electromagnetic Scattering Models", International Symposium on Antennas and Propagation and USNC/URSI National Radio Science Meeting, Washington, DC, June 2005.** T. Klemas, L. Daniel and J. White, "Segregation by Primary Phase Factors: A Full-wave Algorithm for Model Order Reduction", Proceedings of the ACM/IEEE Design Automation Conference, Anaheim, CA, June 2005.** J. H. Lee, D. Vasilyev, A. Vithayathil, L. Daniel, and J. White, "Accelerated Optical Topography Inspection Using Parameterized Model Order Reduction", IEEE International Microwave Symposium, Los Angeles, CA, June 2005.** X. Hu, J. White, and L. Daniel, "Analysis of Conductor Impedance Over Substrate using Novel Integration Techniques", IEEE/ACM Design Automation Conference, June 2005.** K. Sou, A. Megretski, L. Daniel, "A Quasi-Convex Optimization Approach to Parameterized Model Order Reduction", IEEE/ACM Design Automation Conference, Anaheim, CA, June 2005.** L. Daniel, "Invited paper: Krylov Subspace Moment Matching Parameterized Model Order Reduction of Large Circuit Structures," SIAM Conference on Control and its Applications, New Orleans, July 2005.

 B. Bond and L. Daniel, "Parameterized Model Order Reduction of Nonlinear Dynamical Systems", Proceedings of the IEEE Conference on Computer-Aided Design, San Jose, November 2005.**

INVITED LECTURES
June 2002, L. Daniel, J. Phillips, A. Cangellaris, K. Shepard, "Modeling Technology of High Frequency Design", invited full day tutorial, IEEE/ACM Design Automation Conference. April 2004, L. Daniel, Reduced Order Modeling of Parameterized and Distributed Systems, The Banff International Research Station for Mathematical Innovation and Discovery Workshop on Model Reduction Problems and Matrix Methods, Banff, Canada. June 2004, L. Daniel, Characterization and Design Tools for Analog Platforms, Invited Plenary Session talk, Gigascale System Research Center Workshop. October 2004, L. Daniel, Albert Ruehli, Techniques for the Partial Element Equivalent Circuit Modeling approach, Invited Tutorial, IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging. February 2005, S. Elassaad, Z. Zhu, L. Daniel, "Tutorial: Chip-Package Co-design: Signal and Power Integrity Issues, Parasitic Extraction, Parameterized Model Order Reduction", IEEE in Asia Pacific Design Automation Conference. March 2005, A. Devgan, L. Daniel, B, Krauter, L. He, "Tutorial: Modeling and Design of Chip-Package Interface", International Symposium on Quality Electronic Design, San Jose, CA.

ADDITIONAL PROJECTS AND INTERESTS:

Microwave circuit design: 2/99 5/99. Design of a Broadband Low-Noise-Amplifier (LNA) 3-9GHz in Ga-As microstrips for a receiver front-end, http://www.eecs.berkeley.edu/~dluca/lna Analog IC design: 9/97 12/97. Low-Power Low-Voltage Fully-Differential Transconductance Amplifier for a 13-Bit Switch Capacitor A/D Converter, http://www.eecs.berkeley.edu/~dluca/transamp Digital IC design: 2/95 5/95. Error-detector/Corrector CMOS and Pass Logic Circuit: design at the logic, circuit and layout level..