Practise Question:

Consider following simple in-order pipeline with no bypassing. The datapath includes a load/store unit, an adder and a multiplier. Assume that the loads and add operations have two cycle latency where as the multiplication operation has four cycle latency. Write-back for register takes one cycle. Ignore any write back conflicts.

Fetch

Decode

Issue

Load/Store Multiply Add

Write Back

a)

For the given piece of code in the following page, find out the number of cycles between the issue of the first load instruction and the issue of the final store (both inclusive). Assume that at the end of cycle zero, the first load instruction has finished decoding and is ready to enter the issue stage

This code computes the expression E = A * B + C * D, where the addresses of A, B, C, D and E are stored in R1, R2, R3, R4, R5 respectively. [10 Marks] LDR R6, [R1] LDR R7, [R2] MUL R6, R6, R7 LDR R8, [R3] LDR R9, [R4] MUL R8, R8, R9 ADD R6, R6, R8 STR R6, [R5] It would be helpful if you make a table as follows; Cycle # Decoded Instruction Issued Instruction (Enters Issue) (Enters Execute)

Write Back cycle for Issued instruction

b)

Can you reduce the cycle count using instruction rescheduling? Show the results using similar table as shown above.

Answer:

Cycle # 0 1 2 3 3 5 6 7 8 9 10 11 12 13 14 15 16 17 Answer: 18

Decoded Instruction (Enters Issue) LDR R6, [R1] LDR R7, [R7] MUL R6,R6,R7 LDR R8, [R3] LDR R9, [R4] MUL R8,R8,R9 ADD R6, R6, R8 STR R6, [R5]

Issued Instruction (Enters Execute) Stall LDR R6, [R1] LDR R7, [R7] Stall Stall MUL R6,R6,R7 LDR R8, [R3] LDR R9, [R4] Stall Stall MUL R8, R8, R9 Stall Stall Stall Stall ADD R6, R6, R8 Stall Stall STR R6, [R5]

Write Back cycle for Issued instruction 3 4

9 8 9

14

17

Can you reduce the cycle count using instruction rescheduling? Show the results using similar table as shown above.

Answer: The new code sequence will be as follows (reordered) LDR R6, [R1] LDR R7, [R2] LDR R8, [R3] LDR R9, [R4] MUL R6, R6, R7 MUL R8, R8, R9 ADD R6, R6, R8 STR R6, [R5]

Cycle #
0 1 2 3 3 5 6 7 8 9 10 11 12 13 14 Answer: 15

Decoded Instruction (Enters Issue)

LDR R6, [R1] LDR R7, [R7] LDR R8, [R3] LDR R9, [R4] MUL R6, R6, R7 MUL R8,R8,R9 ADD R6, R6, R8 STR R6, [R5]

Issued Instruction (Enters Execute)

Stall LDR R6, [R1] LDR R7, [R7] LDR R8, [R3] LDR R9, [R4] MUL R6,R6,R7 Stall MUL R8,R8,R9 Stall Stall Stall Stall ADD R6, R6, R8 Stall Stall STR R6, [R5]

Write Back cycle for Issued instruction

3 4 5 6 9 11

14