Markus SwitchingCircuitsForEngineers Text

CE-HALL
INTERNATIONAL SERIES
IN
ENGINEERS
SECOND
EDITION
Mitchell P. Marcus
clear
and concise treatment
of the design
and
simplification of combinational
and
sequential switching circuits, with

the emphasis on the practical
rather than the abstract
PRENTICE
HALL
W.
L.
EVERITT,
Editor
In the second edition of this well-
known work
covering the design
and simplification of combinational and sequential switching circuits,

the author once again presents the
material clearly and concisely, with
heavy emphasis on the practical

rather than the abstract.
New
features include: (1
Twice
as
many
end-of-chapter problems for
the reader to test his knowledge
and
understanding of the subject; (2)
Answers or solutions
to
70 per cent
of these problems at the back of the
book; (3) Extensive bibliography

of
related
literature
for
further
study; and (4) Extension of tabular method to multi-output networks.
Other outstanding features
Boolean algebra
to
is
not merely
reader.
"presented"
reader
is
the
The
shown exactly how

is
to rec-
ognize the application of the theo-
rems and
attack."
given
"methods of
An
original
method
is
given for
ex-
obtaining
flip-flop
excitation
pressions in the synthesis of pulse
input sequential circuits.
The
adflap)
(Continued on hack
MCMXCVn
Tel. 50181
S-lQO t2.-S0
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MARCUS, M.P. Switching circuits for e ngineers. 19 6? X^s>
SWITCHING CIRCUITS
FOR ENGINEERS
PRENTICE-HALL ELECTRICAL ENGINEERING William L. Everitt, Editor
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MITCHELL
P.
MARCUS
IBM Corporation
Systems Development Division
Endicott laboratory
JEndieott,
New
York
SWITCHING CIRCUITS
FOR ENGINEERS
Second
Edition
PRENTICE-HALL, INC., Englewood
Cliffs,
New
Jersey
To
El
Bunny
Glenn
Lee
and Ricky
621. 516 .5. 049
5 1962, 1967 by
PRENTICE-HALL, INC.
Englewood
Cliffs,
NJ,
All rights reserved.
No
part of this
in writing
book
from
may
be reproduced in any form or by any

the publisher.
means without permission
Current printing
10 9
8
(last digit):
Library of Congress Catalog Card No. 67-10748

Printed in the United States of America
Pref ace
Switching circuits are circuits that perform logical functions. The design of
switching circuits
is
referred to as logical design. Switching circuits can range

circuit, controlled
in complexity from a simple staircase lighting
from both
upstairs and downstairs, to a complex circuit that performs arithmetic in an

electronic digital computer.
The
interesting task of the logical designer
is
to properly interconnect
basic logical circuit elements or "logic blocks" so that the resultant circuit
performs a desired logical function. There are usually many different ways in which these logic blocks may be interconnected to realize a desired function; however,
some of
these ways require
more
logic blocks than others.
So the logical designer's task goes further than merely realizing the desired
logical function; he tries, in general, to realize the function with the
most
economical
circuit that he can.
Although switching
circuits
can usually be designed
intuitively, a circuit
requirement does not have to become very complicated before intuitive methods can fail to yield the most economical network. With the tremen-
dous growth of automatic

intuition has
digital
computers and the increasing complexity
of business machines and automatic control systems, logical design based on

the logical designer of today has at his disposal
and time consuming. Fortunately, many formalized methods for designing and simplifying switching circuits. These methods can not only
increasingly difficult
become
lead to simpler circuits, but can considerably reduce the time required to
reach a solution. Furthermore, the elimination of even a few redundant

circuit
down -time and
components can increase the reliability of circuit operation, reducing servicing; it can make the circuit easier to understand,
PREFACE
ix
ary states and the assignment of multiple secondary states to a row. The approach to secondary state assignment in this chapter is original. Chapter 17
completes the presentation of sequential circuit synthesis with a discussion of the Z-map, transient outputs, cyclic specifications, and elimination of
hazards.
The synthesis of pulse-input sequential circuits is examined in Chapters and 19 in which an original method for obtaining flip flop excitation expressions is presented. The advantage of this method is that excitation expressions for any type of flip flop can be read from a single map set. The author has tried as much as possible throughout to emphasize the practical rather than the abstract. For the reader who would like to delve
18
deeper into the subject, a bibliography of related literature for further study is included at the end of the book. The bibliography is arranged by chapter. Problems are presented at the end of most of the chapters to give the
reader an opportunity to test his knowledge and understanding of the subject. Answers to the majority of the problems are given at the back of the book;
solutions or partial solutions are also included where
it is felt
that they
would
of the end-of-chapter problems are identified by an asterisk for these problems no answers are furnished at the back of the book; these problems can be used by instructors for assignments or for testing.
be helpful.
Some
In addition to his work in switching circuit theory and its application to the logical design of IBM products, the author has taught courses in switching circuits at IBM since 1954, and this book is a development of these courses.
is indebted to many IBMers: to those in IBM Education who him to write this book in the first place; to the IBM Corporation encouraged making time and facilities available, made it possible for him to who, by IBM engineers who reviewed it and made many valuable the write it; to comments; to the IBM secretaries who, in addition to their suggestions and kindly typed it; and to the many IBM students who gave regular work, so
The author
the
errors
edition such a severe workout, helping to de-bug it by weeding out and who, by their probing questions and comments, contributed to many improvements in the second edition.
first
M.
Binghamton, N. Y.
P.
Marcus
Contents
BOOLEAN ALGEBRA
Postulates, 5
definitions, 6 Theorems, 7 Resume of simplification theorems and "method of attack," IS
Some
Additional theorems, 20
Summary of Boolean
algebra postulates and theorems, 23
SPECIAL FORMS OF
BOOLEAN EXPRESSIONS
27
Expanded sum of products, 28 Expanded product of sums, 28
"Minimum" Boolean
expressions, 30
Minimum
factored form, 33
Functions of n variables, 33
LOGICAL CIRCUITS
Logic blocks, 38 Negative logic, 41
Application of positive and negative logic, 44
36
Mixed
logic,
45
ELECTRONIC LOGIC BLOCKS

Diode
logic blocks, 48
48
Vacuum
tube logic blocks, 49
Transistor logic blocks, 51
xi
xil
CONTENTS
CONTACT NETWORKS
Implementation of and, OR, and not functions, 59
Transfer contacts, 61
57
Bridge
circuits,
63
Nonplanar networks, 63 Complementation of contact networks, 64

Multi-output contact networks, 65
TABULAR METHOD OF SIMPLIFICATION

Optional combinations, 7
71
Tabular method of simplification, 73

Optional combinations with tabular method, 79
final table, SO Weighting of prime implications, 82
Algebraic solution of
Simplification of final table, 83
Complementary approach with tabular method, 85 Iterative method for obtaining prime implicants, 87
Multi-output networks, 88
MAP METHOD OF
SIMPLIFICATION
97
Complementary approach with map method, 102 "Method of attack," 103 Optional combinations with map method, 106 Maps of more than four variables, 106 Summary, 109 Factoring on the map, 109
TREES-RELAY AND ELECTRONIC

Relay trees, 112 Minimization of partial
Electronic trees,
1
112
trees,
114
19
SYMMETRIC FUNCTIONS
Variables of symmetry, 126
1 27 Boolean operations with symmetric notations, 128 Symmetric relay contact networks, 129 Detection and identification of symmetric switching functions, 137
126
m-out-of-n functions,
10
REITERATIVE
NETWORKS
145
Design of reiterative networks, 146 Sequence representation, 150 Elimination of redundant input lines, 151
CONTENTS
xiii
1 1
NUMBER SYSTEMS; ADDERS

Number
systems, 156
56
Binary adders, 161

Binary-coded-decimal adder, 165
12
CODES, ERROR DETECTION, ERROR CORRECTION

Nonchecking numeric codes, 167 Error detection and correction, 171
Single-error detection minimum distance two codes, 174 Single-error correction
167
minimum distance three codes,
176
Single-error correction with double-error
detection
minimum distance four codes, 179
Alphanumeric codes, 179

Cross-parity, 180
13
SEQUENTIAL CIRCUITS
Concept of
Intuitive
stability,
1
182
84
circuit synthesis,
Basic sequential circuit operation, 185
approach to sequential
185
Flow
table, 190
14
SEQUENTIAL CIRCUITS
Primitive flow table, 194
II
193
Synthesis of sequential circuits, 193
"Power-on" output state, 196 Elimination of redundant stable Pseudo-equivalence, 200
states,
197
SEQUENTIAL CIRCUITS
Merged flow
Cycles, 209
table;
III
206
merger diagram, 206
Races, 210
Secondary
state
assignment and Y-map, 212
Transition map, 212
r-map, 214
16
SEQUENTIAL CIRCUITS IV
Utilization of spare secondary states, 217
217
states to a
Assignment of multiple secondary
row, 230
Utilization of spare secondary states summary, 233
xlv
CONTENTS
17
SEQUENTIAL CIRCUITS V
Z-map, 236
Transient outputs; cyclic specifications, 241
236
Hazards, 243
Most-economical
circuit considerations,
247
18
PULSE-INPUT SEQUENTIAL CIRCUITS

Flip flops, 253
352
Pulse-input sequential circuits, 256

Synthesis of pulse-input sequential circuits, 258
Flow diagram, 259 Flow table, 260
Word
statement to flow diagram and flow table, 261
Elimination of redundant states, 266
Secondary assignment, 269
19

Flip flop excitation maps, 273
II
273
Map entries,
Reading the
274
flip flop
excitation maps, 278
Sequential circuit outputs, 295
Most-economical
circuit considerations,
298
RELATED LITERATURE FOR FURTHER STUDY
301
ANSWERS AND SOLUTIONS TO PROBLEMS

INDEX
313
333
Boolean Algebra
Policy
1.
No. 22 may be issued only
if
the applicant
or
or
2.
3.
Has been issued Policy No. 19 and is a married male, Has been issued Policy No. 19 and is married and under 25, Has not been issued Policy No. 19 and is a married female,
Is Is
or 4. or
5.
a male under 25,
married and 25 or over.
From an
XYZ
Insurance
Company Manual
above? There is a great deal of redundancy in this policy statement. Using intuition only, most people will not be able to recognize all of the redundancy in as simple a statement as this one. An equivalent but simpler statement appears near the end of this
Can you
simplify the statement
chapter.
an algebra of logic, called Boolean algebra, which enables us to dispense with intuition and deductively simplify logical statements that are even much more complex. Boolean algebra is named after George
There
is
BOOLEAN ALGEBRA
Chap.
Boole who, in the middle 1800's, developed

later
it.
Almost a hundred years
Claude E. Shannon realized

if
its
application to the simplification of
logical circuits or switching circuits.
Experience has shown that

to
its
circuit implications
he does not become proficient in
one learns Boolean algebra with relation it because he
"thinks" in circuits rather than in the algebra. Experience has also

that the study of Boolean algebra
shown
is
from a purely
is
abstract point of view
not attractive to most engineers because there

for
no
practical association
Study of Boolean algebra as it relates to logical statements has been found to be the most effective initial approach and this approach is followed here. Later, it will be shown how the algebra, one of the most basic tools available to the logical designer, can be used to
to
them
"hang
their hat on."
simplify logical circuits.
x=
or else
x=
false.
Consider basic logical statements that must be either true or
For
example: The applicant
is
a male. Letter symbols are used to represent
such statements as follows.
X = the applicant a male It can now be said that X must be true or else X must be false. Carrying
is
our symbolism a step further, a

statement, and a
If the statement
is
1 is
used to represent the "value" of a true

is true,
is false,
used to represent the "value" of a false statement.

is
"The applicant
1.
a male"
X of X
of
is 1,
is
X= 0, written X = 0.
written
If the statement
we say that we say that
the "value"
the "value"
Thus
X=
There
is
or else
X=
1
no numerical
1
significance to the
and 0; there
is
only a logical
significance.
Although
prerogative
is
and
taken of saying,
represent the truth or falsity of a statement, the "X equals 1" or "X equals 0."
AND
In the reduction of
there are three key
compound
logical statements to
words of
special importance :
Boolean algebra, and, or, and not. First

basic logical statements
consider a
compound statement made up of two

The applicant
is
connected by the word and. a male
and
the applicant
is
married
Making use of symbology
Chap.
BOOLEAN ALGEBRA
X = the applicant Y = the applicant

The
entire
is is
a male married
written
compound statement can now be
Zand Y
false
is X and Y true and when is X and Y false? X may be true or and Y may be true or false. Taken together, there are four possibilities: X and Y may both be true, X may be true and Y false, X may be false and Y true, or both X and Y may be false. X and Y is true only if X is true and 7 is true. This can be tabulated
When
as follows
X
True
True
False False
Y
AND and and AND
True
False
Zand Y
True
False False False
True
False
""
is
used to symbolize and. Thus,

1,
Replacing True with

relationships
False with 0, and
X and Y is written X-Y. and with "" gives the following
X Y
1
X>Y
00Although the ""

has only the logical
to represent
= = = =
signifies multiplication in
ordinary algebra, here
it
and significance. Other symbols have and. Some of these are +, A, and n.
also been used
OR
Now consider a compound statement made up of two basic logical statements connected by the word or.
The applicant
Substituting
is
a male or the applicant
is
married
X and Y for the two statements, as before, gives

Zor Y
BOOLEAN ALGEBRA
This
Chap.
or
is
the inclusive or, that
is,
Ior F means X or Y or both.

either
(With
Unless
the exclusive or,

stated otherwise,
Ior 7 would
or
will
mean
is
X or Y but not both.)

mean
is
always be understood to
the inclusive or.
X or Y true and when X or Y false ? The same four possible combination of X and Y exist. Ior Y true when X true or when Y
When
is is is
true or
when both
are true. This
is
tabulated as follows
X
True True
False
False
Y
OR OR OR OR
True
False
Jor Y
True True True
False
True
False
A "+"
is
used to symbolize or. Thus,

1,
Replacing True with

relationships
False with 0, and
X or Y or with "+"
is
written
X+
Y.
gives the following
X Y X+ Y
T+7 =
1
1
1
1
+0 =
+ +
1
= =
Although the
the logical
"+"
signifies
addition in ordinary algebra, here
it
has only
represent NOT
or significance. Some other symbols or are , V, and u.
that have been used to
Now
consider the statement
The applicant
is
not a male
is it
When
applicant
is is
this
statement true and

is
when
false ? If the statement

is
a male"
true,
then the statement "The applicant
"The not a
male"
is false.
If the statement
is
"The applicant
is
a male"
is false,
then the
statement "The applicant

very simply by letting
not a male"
is true.
This can be tabulated

is
and
letting
not
X represent the statement "The applicant X represent the statement "The applicant not
is
a male," a male."
not
True
False
False
True
Chap.
POSTULATES
Many
not
different
X can be written as
symbols have been used to symbolize not. For instance, X, X', 1 X, or ~ X. We shall use the symbol X
is less
to represent
not X. There
chance of "losing" the "bar" than of losing
the "prime," and the bar can be applied to an expression without the need
of adding parentheses; that

or
1
is,
X+ Y
will
be used instead of
(X +
Y)'
-(X+
Y)or ~(Z +
is
7).
If
a statement
true only
versa, as in the case above, the
of each other. Thus, of X.
is
is false, and vice two statements are said to be complements the complement of X, and X is the complement
when a second statement
Using our symbology,

if if
X=l,
then
then
X = 0,
X= I = X= =
This
is
summarized
in the following table
X
1
X
1
We now have,
It also
by
definition,
1
=
I
and
0=1
1
follows that
= =
X= X
Postulates
Following
is
a summary of the results so
far.
X=
or else
X=
+
1
M1.0
0-0
= 0-1 =0 =
1
0+1=1+0=1
+ 1=1 =
1
=0
This
summary
represents the postulates of Boolean algebra. Based
on
BOOLEAN ALGEBRA
Chap.
these postulates are
many
useful theorems that enable us to manipulate
and simplify logical expressions. Boolean algebra, like any other algebra, is composed of a set of symbols and a set of rules for manipulating these symbols. However, some differences between ordinary algebra and Boolean algebra should be stressed here. In ordinary algebra the letter symbols may take on a large or even an infinite number of values; in Boolean algebra they may assume only one of two possible values, and 1. Thus, Boolean algebra is much simpler than ordinary algebra. In ordinary algebra the values have a numerical significance; in Boolean algebra, they have only a logical significance. Furthermore, the meanings of "" and "+" in Boolean algebra and and or are entirely unrelated to their meanings in ordinary algebra "times" and "plus." In one sense the choice of "", "+", 1, and is unfortunate because
of the tendency to associate them with their counterparts in ordinary

In another sense, the choice is advantageous because of the coincidental relationship that five of the six postulates involving the ""
algebra.
and
"+"
bear to their meanings in ordinary algebra.
Some
The
Definitions
different letters in a
Boolean expression are called
variables.
For
example, in the expression
A-B
or
its
+ A>C +
A>(D
+ E)
and E. Each occurrence of a variable complement is called a literal. In the expression above there are seven literals. The "" is usually omitted in writing expressions in Boolean algebra, and is implied merely by writing the literals, or factors, in
there are five variables, A, B, C, D,
juxtaposition. Thus,
A-B
would normally be written
+ A-C + A>(D + E)
E)
is
AB + AC + A(D +
The
" "
is
used only where additional clarity

if
required.
1
Two
expressions are equivalent

1,
one expression equals
only
when
the
other equals
and one equals
only
when
the other equals 0.
Two
1
expres-
sions are complements of each other if one expression equals
only
when
the other equals 0,
and vice versa. The complement of a Boolean expression
is
obtained by
" ;
Chap.
THEOREMS
changing
all 's
all
to
+'s
's
changing
changing changing
+'s to
all l's all O's
to O's
to l's
literal.
and complementing each

Thus, the complement of
\>A
is
+ BC +
i)(5
1,
(0
C).l
When
the
first
expression equals
the second equals 0, and vice- versa.

is
The
dual of a Boolean expression
obtained by
to
changing changing changing changing
all 's
+'s
's
all
+'s to
all l's all O's
to O's to
l's
literal.
but not complementing any Thus, the dual of
l-A
is
+ BC +
C)-l
(0
+ A)(B +
no general relationship between the "values" of dual expressions both may equal 1, both equal 0, or one may equal 1 while the other equals 0. Duals are of principal interest in the study of the Boolean postulates and theorems, and are also useful in simplification procedures, as we
There
that
is
is,
shall see later.
In the preceding table of postulates, the six postulates involving the " and "+" have been purposely arranged in three rows of two postulates
each.
duals of each other since
Each pair of postulates may be considered as either complements or no literals are involved. The theorems that follow
are presented in dual pairs.
Theorems
Many useful theorems, derived from the postulates, will now be studied. These theorems enable us to simplify logical expressions or transform
them
into other useful equivalent expressions.
BOOLEAN ALGEBRA
Chap.
la.
0-Z=0
In ordinary algebra
it is
lb.
+ X=
not generally possible to prove a theorem by
may be a large Boolean algebra, since the variables can have only two values, and 1, theorems can easily be proved merely by testing their validity for all possible combinations of values of the variables involved. This type of proof is called proof by perfect induction.
substituting all possible values of the variables since there
or an infinite
number of
values. In
Theorem
la
may
X=
0,
then 0-0
= 0.
be proved as follows: must equal either or 1. If If 1, then 0-1=0. Thus, no matter what the
X=
value of X,
0-Z=0
Theorem lb can be proved in an analogous manner. However, the proof can be approached differently by first writing the theorem so that it is in complementary form to Theorem la. The theorem in this form would read 1 + 1. Based on the fact that every postulate has a complementary postulate, if a theorem is valid, then its complementary theorem is valid. This is so because if a theorem is true, based on certain postulates, then its complementary theorem must be true based on the complementary postulates. Thus, Theorem la having been proved, the complementary theorem
X=
+X=
must also be
true.
is
Since the validity of a theorem

sible
based upon
its
being true for
all
pos-
combinations of values of the variables, there is no reason why the 1 in the theorem cannot be replaced by an X. Thus, if the theorem 1 Jf 1 must be true for all holds for all values of X, the theorem 1
+X=
+
1
values of X.
Therefore, inconsequential "bars"
over the variables are
omitted in the theorems. The expression

expression
JSf
is
the dual of the

its
dual theorem For this reason, it is not necessary to go through the mechanics of proving both of a pair of dual theorems to be true proving one is sufficient. The literals in a theorem may represent not only single variables but also terms or factors or longer expressions. For example, using Theorem 1,
X = 0.
valid.
Thus,
if
a theorem
is
valid,
then
must
also
be
0>(AB
The important point
+
to
C)
+ AB+C=\
1
remember about Theorem

0 anything =
is
that
and
1
+ anything =
2b.
2a.
\-X =
+ X= X
first
This pair of theorems can be proved as easily as the
pair
by sub-
Chap.
THEOREMS
stituting
both possible values for X. The important point to remember

is
about Theorem 2
that
multiplication
by
or
addition
1
o/O
does not affect an expression. For example,
1>(AB
3a.
C)
= AB + C
XX = X
An
(ABB
+ AB+C = AB+C 3b. X + X = X

C)(AB
literals
example of the application of Theorem 3 follows.
C)(AB
+ C+
C)
= (AB +
C)
= AB + C
may
expressions.
This example stresses again that the
in these theorems
represent not only single variables but also

4a.
more complex
1
XX = If X =
4b.
1,
then
X = 0;
if .T
= 0,
then
0,
X+ X= X = In
1. is
either case,
Theorem
4a represents the product of 1 and represents the sum of 1 and 0, which
which
0,
whereas Theorem 4b
says that
is 1.
Theorem 4
complement
complement
anything multiplied by
its
and
anything added to
its
1
Some
simple exercises on Theorems
through 4 follow. These exercises
should be tried before reading the solutions that follow.

Simplify
(a)
(c) (e)
AAB AA + B A+A +B
Solutions
(b)
(d)
(f)
AAB
A+A+B
(A
A)B
(a)
(c)
AAB = AB
(b)
AAB =
AA+ B = + B = B
+
J
(o)A
A+B=l+B=l
is
(&)A
(f)
0-5 = +A+B=A+B (A + A)B - -B = B

1
The prerogative
present the
is
and
()
operation and
taken of using the terms "multiplication" and "addition" to reor (+) operation respectively. The term "product"
used to represent the result of the and operation. Thus, XYZ is called the product of X, Y, and Z; (A B)(C + D) is called the product of A + B and C + D. The term "sum" is used to represent the result of the or operation. Thus, + Y + is called the sum of X, Y, and Z; AB + CD is called the sum of AB and CD. Furthermore, an expression such as (A + B){C + D) is called a "product of sums," and an expression such as AB CD is called a "sum of products."
10
BOOLEAN ALGEBRA
Chap.
5a.
XY = YX
Example:
5b.
X+ Y= Y+ X
AB +
6a.
C=BA + C=C + AB=C+BA

(XY)Z
6b.
XYZ =
X{YZ)
X+ Y + Z=X+{Y + Z)
= {X+ Y) + Z Z+ F+...+Z = AT...Z
7a.
XY...Z= X + Y+... + Z
. .
7b.
Tîs theorem is known as DeMorgan's theorem. Theorem 7a can be proved as follows: If X, Y. and Z all equal 1,
,
l-l- ... -1
I
= + + =I =
1 1
...
If X,
and
do not
all
equal
1,
then one or more of these

equals 0,
1
literals
must equal
0. If
even one of the

0.1. ... -1
literals
= 0+ + 0= +0 + =
1 1
... ...
+ +
Theorem 7a states that a product of literals may be complemented by changing the product to a sum of the literals and complementing each literal. Theorem 7b states that a sum of literals may be complemented
by changing the sum to a product of the
each
literal.
literals
and complementing
Examples:
ABCDE = A + B + C + D + E A + B + C + D + E= ABCDE
Note
that
Theorems 7a and 7b and the above examples represent
equivalences.
For example, but ABCDE and A +

This pair of theorems
B+C+D + E
may be
ABCDE is
equivalent to
A-\-B-\-C-\-D
+ E,
as in
are complements of each other.
written in a
more general form

Z,
Theorem
8.
8.
f(X, Y,...Z,., +) =f(X, Y,
+,
This theorem is read as follows. Given an expression containing literals and +. To comsuch as X, Y, and Z, and occurrences of the operators plement this expression, signified by the /, each literal is complemented,
each
is
changed to +, and each
is
changed to
simple example
follows.
Chap.
THEOREMS
11
C + AB = C{A +
B)
Note the importance of the parentheses. In the original expression, C is added to the product AB. Therefore, the complement C must be multiplied by the sum {A + B). Now for a more complex example
{AB
C)D
+E=
[(A
+ B)C +
D]E
brackets.
The product Again note the importance of parentheses and was originally product AB, when complemented, becomes (A + B). This C. by The sum multiplied (A now added to C; therefore, the sum + B) is {A product therefore, the + B)C {AB + C) was originally multiplied by D; {AB C)D there+ is now added to D. Finally, E was originally added to B)C [(i giving + + Z>]. fore, E is now multiplied by {A + B)C + D,
;
Some important
9a.
simplification theorems
9b.
now
follow.
XY+XZ=X{Y + Z)
(Z+
F)(X
+ Z) = X + YZ
Theorem 9a is like factoring in ordinary algebra. The operation repreTheorem 9b is not permitted in ordinary algebra, but the procedure is analogous to that in Theorem 9a. The procedure may be better understood if Theorem 9a is first considered in a little different way. The X is common to both terms XY and XZ. X is multiplied by Y, and X is multiplied by Z. Therefore, X will be multiplied by the sum of the remainders of each term, namely ( Y + Z), giving X{ Y + Z). Now, Theorem 9b can be thought of in a similar way. X is common to
sented by
both factors {X
Therefore,
namely
+ Y) and {X + Z). Z added to 7, and X acWerf to Z. X will be affcfed to the product of the remainders of each factor, YZ, giving X + YZ.
is
is
Examples:
(a)
AB +
04
^CZ)
(b)
B){A
+ A{E + F) = A{B + CD + E + F) + C + D)G4 + EF) = ^ + 5(C + )F

that the
practice
similarity of the dual operations

will
The examples have purposely been presented in dual pairs so can be more easily seen. This
be maintained throughout the study of theorems. In example (a), A is common to all three terms. In each case A is multiplied by the remainder of the term. Therefore, the A will be multiplied by the sum of what remains in each term: A is multiplied by the sum {B CD E F). E F does not require additional parentheses (see
+
A
Theorem
6).
In example
(b),
is
common
to every factor. In each case,
is
added
to the remainder of the factor. Therefore, the
of what remains in each factor: A is does not require additional parentheses (see Theorem
be added to the product D)EF. Again, EF added to B{C

will
6).
12
BOOLEAN ALGEBRA
Chap.
Now for two

(a)
slightly
more involved examples
ABCD + ABCE + ACF = AC(BD + BE + F) = AC[B{D + E) + F]

(A
(b)
+B+ C+
D)(A
B+C + E){A + C + F)
= A + C+(B + D)(B + E)F = A + C+{B + DE)F
In example (a), AC is common to all three terms and is multiplied by the remainder of a term in each case. Therefore, AC is multiplied by the sum of the remainder of each term, namely (BD BE F). Furthermore,
within the parentheses,
is
common
is
to
two terms;
therefore,
is
similarly
factored out to obtain the final expression.
In example
(b),
A+ C
common
to all three factors
the remainder of the factor in each case. Therefore,
A + C is
and is added to added to the
product of the remainder of each factor, namely (B D)(B more, B is common to two of the factors, leading to the
10a.
+ E)F. Furtherfinal expression.
XY + XY = X
may appear to be
10b.
(X + Y)(X +
f)
=X
In Theorem
This theorem
10a,
a special case of Theorem
9.
XY + XY = X{Y+Y) = X-l = X
In
Theorem
10b,
(X
However,
Y)(X
+?) =
X+
YY
this
theorem has further implications. In a sum of 2 m
w-variable terms, or in a product of 2 m -variable factors, if variables occur in all possible combinations (represented by and Y in the theorem),
while the remaining n
m
3
variables are constant (represented
by
X in the
theorem), the
expression.
m variables
are redundant
and the n
m variables
define the
m = 2 is as follows XYZ + XYZ + XYZ + XYZ = X- = X Here, in 2" = 2 = 4 terms, m = 2 variables (F and Z) occur in all possible combinations, while n m = variable (Z) is constant; thus, Y and Z are redundant and X defines the expression. Another example with n = 4 and m = 2 is as follows (JF + X + f + Z)(JF + X + F + Z)
An
example with n
and
(W+ X+ Y+Z){W+ X+
Y+Z)=W+X+0=W+X
Chap.
THEOREMS
13
Y and Z
occur in
all
possible combinations, whereas
W and X are conin
stant; thus the expression reduces to
W + X.
such
a
there are 2 m
Note that the number of terms or factors involved simplification must be a power of two (2, 4, 8, 16, etc.), since
combinations of m variables.
This theorem
is
the basis of other simplification methods which will be

7.
taken up in Chapters 6 and

11a.
X + XY = X
lib.
as follows:
X(X+
Y)
=X
Theorem 11a can be proved
X+ XY= X(\ +
Y)
X-\
=X
Although Theorem lib can be considered proved once Theorem 11a is proved, since the theorems are duals of each other, Theorem lib can also be proved as follows
X(X +
Y)
= XX + XY = X + XY
as in the proof of
and the rest of the steps will be the same Another proof is as follows
Theorem
11a.
x{x +
Y)
= (x + oxz +r) = x + o.r=z + o = x

may be
applied in the following way. If a
This simplification theorem
smaller term (or factor) appears in a larger term (or factor), then the larger appears in the larger term (or factor) is redundant. 2 In Theorem 11a,
term XY. Therefore, the term XY is redundant and the expression reduces to X. Similarly, in Theorem lib, ^ appears in the larger factor (X+ Y); therefore, the factor (X + Y) is redundant and the expression reduces to X.
Examples:
(a)
AB + ABC + AB{D +
(A
In example
(b)
B)(A
the
+B+
term
C){A
= AB + B + DE) = A + B
E)
appears in the second and third terms; therefore, the second and third terms are redundant and the expression E) appears in the reduces to AB. In example (b), the first factor {A
(a),
first
AB
second and third factors; the second and third factors are therefore
re-
dundant and
12*.
this expression reduces to
A+
12b.
B.
X+ XY= Z+
X(X
10
= XY
A few interesting ways to prove Theorem

2
12a follow:
The smaller term
(or factor)
is
is
the larger term (or factor)
the one containing
defined as the one containing fewer literals; conversely, more literals. The larger is said to
subsume the smaller.
14
BOOLEAN ALGEBRA
Chap.
X + XY = (X + X)(X + = 1-(X+ Y) = X+ Y
or
Y)
(Theorem 9b
in reverse)
X+XY= X+ XY+XY
= X+ Y
(Theorem 11a (Theorem 10a)
in reverse)
Theorem 12b can be proved in the same manner. Proofs of the type just shown represent interesting manipulations of the algebra. However, a straightforward method of proof that can always be used is called the "truth table" proof, which is a means of applying the method of perfect induction. In a proof by perfect induction, it is shown
that
an equality of expressions
exists for all possible

is
combinations of values
of the variables. This type of proof
especially adaptable to
Boolean
algebra where the variables can have only two values,
or
1.
A truth table
proof of Theorem 12a follows
Y
1
X
1 1
XY
1
X+ XY
1 1
X+
1
1 1
1 1
1
First,
every possible combination of the values of the variables are
listed.
combinations, 00, 01, 10, and 11. These combinations are listed in columns 1 and 2. Since an will be needed, the complementary values of column 1 are written in column 3. Next, the product is required; this is placed in column 4, and is obtained by the multiplication of columns 2 and 3. In column 5 is written the values of the sum XY, which is obtained by the addition of columns 1 and 4. Finally, in column 6, is written the sum Y, which is obtained by the addition of columns 1 and 2. It is now found that the values in columns 5 and 6 agree for every possible comY, there are four possible
In this case, with two variables,
X and
XY
X+
X+
bination of the variables
In practice
it is
X and Y, thus proving the theorem. found helpful to think about Theorem 12 in a
shown
in
slightly
more general way,

12a'
lib'
as
Theorem
12'.
ZX + ZXY =ZX + ZY (Z + X){Z + X + Y) = (Z +
X){Z
Y)
The reason
for presenting this modification of
Theorem
12
is
that the
Chap.
THEOREMS
15
application
is
usually encountered in the

is
form of Theorem
12'.
The way of
applying this theorem

in a larger
factor)
as follows: if a smaller term (or factor) appears
term (or factor) except that one variable in the smaller term (or and the corresponding variable in the larger term (or factor) are complements, then that variable in the larger term (or factor) is redundant. In Theorem 12a', the smaller term ZX, appears in the larger term ZXY, except for the complementary X and X. Therefore, the X in the larger term is redundant, and the expression reduces to ZX -\- ZY. A similar relationship exists in Theorem 12b'. It does not matter where the "bar" actually appears; it is always the variable in the larger term of factor that
is
redundant.
Example:
WX + WXY =WX+WY
The
X in the larger term

difference
if
:
is
redundant because
it is
the complement of the
X in the smaller term.

Note the Theorem 11
term (or
between the application of Theorems 11 and 12'. a smaller term (or factor) appears exactly "as is" in a larger
factor), the entire larger term (or factor) is redundant.
Theorem
12':
if a smaller term (or factor) appears in a larger term (or factor) except for one complemented variable, only that variable in the larger term (or factor) is redundant. If a smaller term (or factor) appears in a larger term (or factor) with two or more variables complemented, no simplification of this
sort
is
possible.
Now for some examples involving Theorems 11 and 12'. AB + ABC + ABD + ABE + ABF = AB + BD + AE + ABF (a) (A + B)(A + B + C)(A + B + D)(A + B + E)(A + B + F) (b) = (A + B)(B + D)(A + E)(A + B +
F)
In example (a), the first term appears in the second with no complementation; therefore, the entire second term is redundant. In the third and fourth terms, one variable appears in complemented form: A in the third, and B in the fourth; these two variables are therefore redundant. In the
fifth
term, two variables are complemented and therefore
of
this sort is possible.
possible
ways if same reasoning can be made throughout. The following pair of theorems can be thought of as the "included term" and "included factor" theorems, respectively.
13a. 13b.
no simplification The final expression may be factored in one of two desired. Example (b) is the dual of example (a) and the
XY + XZ + YZ = XY + XZ (X+ Y)(X + Z)(Y-{-Z) = (X +
Y)(X
+ Z)
16
BOOLEAN ALGEBRA
Chap.
An
interesting
proof of Theorem 13a
is
as follows.
XY+XZ+ YZ= XY+XZ + YZ{X + X) = XY+XZ+ XYZ + XYZ = XY+XZ

Theorem 13b may be proved
Following
is
in a similar
manner.
13a.
a truth table proof of
Theorem
XYZ
1 1 1 1
X
1 1
XY
XZ
1
YZ
XY+XZ
1
XY + XZ +
1
YZ
1 1
1
1
1 1 1 1
1
1 1
1 1
The last two columns have the same value for all possible combinations of values of the variables, proving the equivalence. However, more can be learned from this truth table. Examination of the YZ column and the
XY
+ XZ
column
will
show
that
XY + XZ
equals
for four of the eight
YZ equals 1 for two of the eight possible combinations. Furthermore, the two combinations for which YZ equals 1 are included among the four combinations for which equals 1
possible combinations, whereas
XY + XZ
that
is,
the expression
XY + XZ "includes"
the term YZ.
Hence the name
included term (and included factor) theorem.
Now for the recognition of the application of this pair of theorems. In the application of Theorem 13a, two terms are looked for: one that contains a variable, and the other that contains the complement of this same
variable. For instance, the first term in the theorem contains an and the second term contains an X. If two such terms are found, the remainders of each term, exclusive of this variable and its complement, together form
a product that is included by the first two terms. In Theorem 13a, the first term contains an and the second term contains an X. The remainders of these two terms are Y and Z, respectively, and together they form a product YZ which is included by the first two terms. An included term may lead to the elimination of redundancy in the expression. For example, in the theorem, the third term YZ is redundant: there is no need to add the term YZ to the terms XY + XZ, since the term YZ is already included. In a sense, Theorem 13a is first applied in reverse to obtain the included term. The included term may then be used to eliminate redundancy in the
Chap.
THEOREMS
17
expression,
following which,
Theorem 13a
Theorem
13b.
is
applied to eliminate the
included term.
Similar reasoning applies in
Two
factors are looked for:
one that contains a variable, and the other that contains the complement of this variable. If two such factors are found, the remainders of each factor, exclusive of this variable and its complement, together form a sum that is included by the first two factors. An included factor may be used
to eliminate redundancy in the expression.
as
(a)
Theorem 13 can often be used in conjunction with other theorems, such Theorems 10, 11, and 12'. Some examples follow:
The
the
first
two terms,
AB + AC + BCD = AB + AC noting the A and A, include a term

the
BCD is Therefore the expression reduces to AB + AC.

included term BC,
term
BC. Because of redundant (Theorem 11a).
(b)
(A
first
+ B)(A +
C)(B
+ C+
D)
(A
+ B){A +
C)
The
(B (B
two
factors, again noting the
and A, include a factor (B
C).
+ C) appears in the third factor (B + C + D); therefore, + C + D) redundant (Theorem lib). (c) AB+ AC+ BCD = AB+AC+CD = AB+ C(A + D)
is
the factor
The
first
BCD
B
is
two terms include the term BC. BC appears in the third term B in the third term is complemented. Therefore, the redundant (Theorem 12a') and the expression reduces to AB + AC
except that the
is
+ CD (which may be factored).

The next example
(d)
the dual of example
(c).
(A
+ B)(A +
C)(B
+C+D) = (A + B)(A +
C){C
D)
(e)
= (A + B){C + AB + AC + BC = AB + C
C
AD)
The first two terms include BC. BC and BC reduce to C (Theorem 10a). The expression at this point reads AB + AC + C. The AC term is
redundant because of the
term. Therefore, the expression reduces to
AB +
(f)
C.
is
The next example

(A
the dual of example
(e).
(g)
+ B)(A + C){B +C) = (A + B)C ABC + ABD + BCDE = ABC + ABD

BCDE redundant.
For example,
lead to other included terms.
The
(h)
first
two terms include BCD, which makes
Included terms
may
AB + AC + BD + CD - AB + AC + BD
18
BOOLEAN ALGEBRA
Chap.
The
first
CD
(i)
therefore
two terms include BC. BC and BD include CD. The fourth term is redundant, and the expression reduces to AB + AC + BD.
Additional examples are given for analysis.
{A
(j)
+ B){A + C)(B + D)(C + D) = (A + B){A + C)(B + D) AB + AC + BD + DE + CE = AB + AC + BD + DE

A
or
AB + AC + BD + DE + C = AB + ^C +
-#
+ -D
(k)
(^
+ B){A +
(1)
+ E)(C + ) = (A + 5)(i + C)(5 + AB+ AC + AC iC + ^C + C

C)(
>)(
D)(D
+ E)
v45
If the
term ^45
is
eliminated, the term
BC
cannot be eliminated since
it
would no longer be included by
AB +
AC.
Resume of Simplification Theorems and "Method of Attack"

While no hard and fast rules can be given for the best "method of attack" any Boolean expression, the following approach is given as
in simplifying
a guide.
Chap.
RESUME OF SIMPLIFICATION THEOREMS
19
Resume of Simplification Theorems

la.
0-X=0
\-X= X
lb.
2a. 3a. 4a.
2b.
3b.
XX = X XX =
4b.
+ X= + X= X X+ X= X X+ X=
1 1 1
Z7 + ZZ = Z(7 + Z) 9b. (Z + F)(Z + Z) = X+ FZ 10a. Z7 + Zf = X 10b. (Z + F)(Z + Y) = X 11a. Z + ZF = X lib. Z(Z+ 7) = X 12a. J+JF= Z + r 12b. X(X + Y)= XY 12a'. ZX + ZXY =ZX + ZY 12b'. (Z + X)(Z + Z + Y) = (Z + Z)(Z + T) 13a. zy + xz + yz = zr + xz 13b. (Z + Y){X + Z)(7 + Z) = {X + 7)(Z + Z)
9a.
Theorems
thought
factor or
is
to 4 are, of course, applied whenever possible; however,
their application
becomes almost "second nature," and more deliberate

is
usually directed toward the other less obvious theorems. It
stressed again that
X may represent not
only a variable but also a term or
more complex expression. Theorems 10, 11, and 12' should be applied exhaustively. Then Theorem 13 should be applied. Theorems 10 through 12' may further be applied in
conjunction with or following the application of Theorem 13. If a "factored" form, rather than a sum of products or product of sums form, is desired, then Theorem 9 may be applied. Theorem 9 generally
should not be applied until there

the other theorems; if
is
no longer any possible application of

is
Theorem 9
applied too early, the application
of the other theorems
may be
obscured.
There is a tendency for the beginner to prefer to work with the sum of products form, rather than the product of sums form. To this end he may (1) "multiply out" a product of sums expression (that is, apply
in reverse) to obtain an equivalent sum of products expression complement the product of sums expression to obtain a complementary sum of products, and after simplification, recomplement or;
Theorem 9a
or; (2)
(3)
obtain the dual of the product of sums expression and, after simplifying,
obtain the dual of the dual.
This
tial
is an undesirable practice Every additional operation adds a potensource of error. Also, multiplying out generally adds additional redun!
20
BOOLEAN ALGEBRA
Chap.
dancy which must be removed. There is no need for this practice: each sum of products theorem has its dual product of sums theorem, and both can be used with equal facility.
Additional Theorems
The
pair of theorems that follow are not simplification theorems but
rather transposition theorems.

14a. 14b.
XY + XZ = (X + Z)(X + Y) (X + Y)(X + Z)= XZ+ XY
to look for in the possibility of making a transposition of two terms or factors, one that contains a variable, and the other that contains the complement of this same variable. In Theorem 14a, the first term contains an X and the second term contains an X; therefore, the transposition shown can be made by adding the X to the remainder of the term containing the X, and adding the X to the remainder of the term containing the X, these two sums being multiplied together. Conversely, in Theorem 14b there are two factors, one that contains an X, and the other that contains an X. The transposition shown can be
The key point
this type is
made by
by the remainder of the factor containing the multiplying the X, and multiplying the X by the remainder of the factor containing the X, and then adding these two products together.
Example:
ABC + A(D +
E)
{A
+ D + E)(A +
BC)
In making the transposition, the A is added to the remainder of the term E, and the A is added to the remainder of containing the A, namely D the term containing the A, namely BC, the two sums being multiplied
together.
For a second example, the transposition will be made in the other (A + D + E)(A + BC). Here the A is multipliedby the remainder of the factor containing the A, namely BC, and the A is multiplied by the remainder of the factor containing the A, namely D + E, the two products being added together. The result is the original expression
direction, starting with
ABC + A(D +
When
is
E).
the relationship between Boolean algebra

later,
and switching
circuits
taken up
Two
the desirability of such transpositions will be apparent. special cases of the application of this theorem are given because of
the frequency with which they are encountered in practice.
Chap.
ADDITIONAL THEOREMS
21
XY + XY = (X + Y)(X + Y) AT XY=(X + F)(Z+f)

-{-
The first case describes the "exclusive or" function (one or the other but not both), sometimes symbolized by F or Y. Another useful form of the expression is (X Y)XY. The second case describes the complement of the "exclusive or": the "neither or both" or "if and only if"
XY
function,
sometimes symbolized by expression is (X + Y) + XY.

15a. 15b.
X=
Y.
Another useful form of the
X.f(X,X, Y,...,Z)=X-f(l,0, Y,...,Z)
X+f(X, X,Y,...,Z)= X+f(0,

1
1,
Y,
is
,Z)
Theorem
replaced by
5a states that
if
a variable
X
all
multiplied by an expression
containing occurrences of
l's,
X or
X, then
X's in the expression
may
be
and
all
may be
replaced by
O's.
This
can be seen to be permissible since
X-X=
and
X-l
=X = X is
Z-Z=
Theorem
1
^-0
5b
states that if a variable
added to an expression con-
taining occurrences of
X replaced by O's, and all X

since
and X, then
all

l's.
may
be
's
may be
replaced by
Again
this is permissible
Z+ X= X+0= X
and
X+X= X+
Examples:
(a)
A-[AB
+ AC +
(A
(b)
A-{AB
+ AC+
this
D)
+ E)] = A-[l-B + 0-C+ (1 + D)(0 + E)} = A[B + 0+ \>E\ = A(B + E) = A>(0'B + \-C + D) = A(C + D)
D)(A
simplification, but
it is
Not only
16a. i6b.
is
theorem useful for
partly the basis
of the following theorem.
/(*,*, r,...,Z)=X./(l,0, y,..,,Z)

f(x,x, 7,...,z)
^-/(0,
1,
r,...,Z)
fz+/(o,i, r,...,z)][z+/(i,o, y,...,z)]
This pair of theorems can be proved using Theorem 10 in reverse, along
22
BOOLEAN ALGEBRA
In Theorem 16a an expression
multiplied
Chap.
with Theorem
15.
is
first
by
and also by X, the two products being added together.
f(X,X, Y,...,Z)=X.f(X,X, Y,...,Z)

It
X.f(X,X, Y,...,Z)
can be seen that these two expressions are equivalent since the latter can be reduced to the former by the application of Theorem 10. Now, by the application of Theorem 15 the Z's and Jf's can be replaced with l's and 0's, respectively, when the expression is multiplied by X, and
they can be replaced by 0's and
multiplied
l's,
respectively,
when
the expression
is
by X. Theorem 16b can be similarly proved. Theorem 16 has the following application: given an expression containing any number of occurrences of some variable and its complement, say X
and X, the expression can be rewritten using only one occurrence of one occurrence of X, at most.
X and
Example:
AB + AC +
occurrence of A, at most.
(A
D)E
(i
+ F)G
A
and one
Find an equivalent expression with only one occurrence of
A[AB
AB + AC + {A + D)E + {A + F)G + AC + (A + D)E + {A + F)G]
+ AC + {A + D)E + {A + F)G\ F)G\ + (1 + + (0 + A[0-B + 1-C + (0 + D)E + (1 + F)G] = A[B + + >E + FG\ + A[0 + C + DE + >G] = A[B + + K7] + ^[C + 2XE + G] +
A[AB
= A[\ >B + 0-C +

1
D)E
The application of Theorem 16b

While itself and
this pair
its
is
analogous.
of theorems reduces one variable to one occurrence of complement at most, it may introduce multiplicity of other
variables. Circuit requirements, however,
may make this a desirable operation.
be further applied to each bracketed expression independently, thereby reducing a selected second variable to two octhird selected variable currences of itself and its complement, at most.
16
Theorem
may
may
be reduced to four occurrences of itself and its complement, etc. Boolean algebra will now be applied to the simplification of the XYZ
Insurance
Company Manual
statement at the beginning of this chapter.
Let
A = B= C=
Applicant has been issued Policy No. 19 Applicant Applicant Applicant

is
is is
married
a male
D=
under 25
Chap.
BOOLEAN ALGEBRA POSTULATES AND THEOREMS
23
Policy No. 22
1.
may
be issued only
if
or or
2.
3.
ABC ABD
ABC CD BD
or
or
4.
5.
which can be written
ABC + ABD + = ^5C + AB + = AB + = AB +
=
Policy
1.
iC + CD ABC + CD BC + CD B + CD B +CD
if
+ Z) + #D + BD + BD
(Theorem
12a')
12a')
(Theorems 11a,
(Theorems 13a, 10a)
(Theorem 11a)
No. 22 may be issued only

Is
the applicant
married,
or
2.
Is
a male under 25.
Summary
of Boolean Algebra Postulates
and Theorems
Postulates
X = or else X = 1-1 = 1.0 = 0-1 =0 0-0 = I =

1 1
0+1=1+0=1
+ = 0=
1
+ =
1 1
Theorems
la.
0-Z=0
1>X= X
lb.
2a. 3a.
4a. 5a.
2b. 3b. 4b.

5b.
XX = X XX =
+ X= + X= X X+ X= Z
1 1
XY= YX
XYZ = (XY)Z =
X{YZ)
X+ X=l
6a.
6b.
7a.
8.
XY ...Z= X
-\-
Y+
...
+Z
7b.
,
X+ 7= Y+ Z X + f + Z = (X + F) + Z = *_+(F + Z) at + r+...+z=jff...z
+,
)
f{X, Y,...,Z, .,+)=/(*,?,. 9a. ZF + JTZ = Z(F + Z)
z,
9b.
(Z+
F)(X + Z)
= Z + FZ
24
BOOLEAN ALGEBRA
Chap.
10a.
11a. 12a.
Z+ XY= X+ Y 12a'. ZX + ZXY=ZX + ZY

12b'.
XY + XY = X X + XY= X
10b. lib. 12b.
(X + Y)(X + 7)
=X
X(X+ Y) = X X(Z + 7) = XY
(Z + Z)(Z + X + Y) = (Z + X){Z + 7) X7 + XZ + 7Z = XY + ZZ 13b. (AT + Y)(X + Z)(7 + Z) = (X + 7)(X + Z) 14a. X7 + XZ = (X + Z)(JT + Y) 14b. (*> 7)(Z -\-Z) = XZ + XY 15a. X-f(X,X, 7,...,Z) = X./(1,0, r,...,Z) ,Z) 15b. X + f{X,X, Y,...,Z) = X +/(0, 1, 7, ,Z) ,Z) + X-f(0, 7, ,Z) = Z./(l, 0, 7, 16a. /(Z, Z, 7, 16b. /(*,*, 7,...,Z) = [Z+/(0,1, 7,...,Z)][X+/(1,0, 7,...,Z)]
13a.
.
1,
PROBLEMS
1.
Simplify:
(a)
(b)
(c)
(d)
(e)
(f)
^ + 5 + i5 + (^ + 5)15 (A + B + AB)(A + 5)^5 A + 5 + AB + C (^ + 5 + ^5)C (^ + 5)i5 + C (^ + 5)i5C B and AS are complements. Hint: A
-\-
2.
Complement:
(a) [(ii?
(b)
*(c)
*(d)
3.
+ C)D + ]F ^[^ + 7(r+C)] + if F\R{I+DA)_+Y] t/+[(F+ W)X+Y]Z

to
Reduce
(a)
minimum number of literals.
(b)
(c)
(d)
(e)
(f)
*(g)
*(h)
*(i)
+ A)F + (A + E)BC + 5F+ C + E)(D + E + FB) ^5C(Z> + ) + F( + D)(G + #)5 (A + C + 5 + iO(Z> + <?# + F + C) ^5(C + D)(E + F) + G(D + C)HA (^5 + C + D + F)(G + FE + C + ##) BC{D + iO(G + H) + /(F + 5)X5 (L + M+NP+ QR)(RQ + S+M+ T) A{B + C)D + EF{C + 5)(G + #)
CD(E
04
Chap.
PROBLEMS
25
*G)
(FR
+ I+D + AYXYA + Q + U + /)
4. Simplify:
(a)
(b)
(c)
ABC + ^5CD + CA ,4C + ACD + CU
(d)
(e)
(f)
*(g)
*(h)
+ CD)(i + B)(A + B + E) + EGH + HE+ HFE + /# (K + L + P)(L + M + P)(g + P + )(L + P)(P + JV + Z) (^ + BC)(A + + C + Z>)(i + C + )(i + B + C + F) (A + BC+ G) 7M + KIM + MI+ MIG + MM (/ + C + B + M)(/ + M)(M + / + L)(M + / + Z)(F + / + M
B (^ Z>77
)
5. Simplify:
(a)
(b)
(c)
+ ACDE + Ci5 ^5CD + BCE + ,4

,45
(d)
(e)
(f)
(g)
(h)
6.
+ B)(A + C + D)( +C+D) + B + C)(fi + C + 5)04 + D) i5C + ^4Z) + BCD i5C + ABD + CD (i + B + C)(C + D)(A +B + D + E) (i + B + C)(i + 5 + D + )(C + D)
(A
(i
J
Simplify:
(a)
(b)
(c)
(p
AC + BA + DCJ + C + 5CF + 5GC + A + T)(P + E + T)(P+0 + T){P+ U+T)(P + I)(i+T) iC + CE + 5CZ> + Z)

(i
(d)
(e)
+ 5)(C + A)(B + C +
)(
/>
(f
(g)
(h)
*(i)
*(j)
*(k)
*0)
7.
L + LM + i0/ +GM+ GHJ Izr + f^z + fzx + zrz + zf {A + B)(A + C + B)(B + A + C){B + C + A)(C + B + A) ( + ^ + Z>)(5 + E:+ D)CB + /+ !>)(+ /+) (5 + 0)(0 + 70 / + / + AIO + 0 ABC + DE + ACF+ AD + ABE (* + y)(^+z + y)(7+z+z)(r+z+z)(z + f + z)
J
J
ABD + ^CD + A BE +_AF + EF
D)
Transpose to a product of two expressions

(a)
(b)
*(c)
*(d)
+ ADE + Z>CF + G) + C{EF + G) fU(V +W) + (XY + Z)U

A(B
BC)D (^ {A +_ )CZ)
+ +
C)
26
BOOLEAN ALGEBRA
Transpose to a
(a)
Chap.
8.
sum
of two expressions
(b)
*(c)
*(d)
9.
+ BC)(A + D + E) + C + 5] [D +-(E + F)G\ [04 + )C + ^[FG + D + E] [Jlftf+fl+flKg + JfyS+O]

(A
[AB
as a product of
(a)
Reduce the following to a single occurrence of A and two expressions and as a sum of two
Express each
expressions.
AG +
(^
(b) 10.
{A + 5)C + iD + (i + F)E + B)(A + C)( + + ^F)(G + H +
A/)
Find twelve ways to express with six literals, complementing variables only, i.e., without complementing products or sums.
AC + AB + AC + ^5
Special Forms
of Boolean Expressions
Four forms of Boolean expressions that
are of particular interest are:
Expanded sum of products Expanded product of sums
"Minimum" sum of products "Minimum" product of sums

The expanded sum of products and expanded product of sums forms and their associated
will
are useful for the analysis of Boolean expressions

circuits and, also, they are
which
be taken up
a starting point for other methods of simplification later. The "minimum" sum of products and
are of interest because circuits are
directly
"minimum" product of sums forms

most frequently implemented
from
these expressions.
27
28
SPECIAL FORMS OF
BOOLEAN EXPRESSIONS
Chap. 2
Expanded Sum of Products

In the expanded
either
sum
of products, each term contains every variable,
uncomplemented or complemented. To obtain the expanded sum of products from a sum of products, the missing variables are supplied in
possible combinations to each product. Actually, in so doing,
is
all
Theorem
10a
used in reverse.
X= XY + XY
As an example,
the
sum
of products
ACD + ABD-\- AC
will
be expanded. The first term, ACD, has one missing variable B which is supplied in both its uncomplemented and complemented form; ACD thus expands into two terms: ABCD and ABCD. The term AB D also
expands into two terms:

variables
ABCD
and
ABCD. The AC
term has two missing
and D.
Two
variables can occur in four possible combinations.
Therefore, the term
and
is
ABCD.
AC expands into four terms: ABCD, ABCD, ABCD, The ABCD term has already been obtained by the expansion
term and
is
of the
ABD
not repeated. The expanded
sum of products
therefore
(1)
ABCD + ABCD + ABCD + A BCD + ABCD + ABCD + ABCD

Note, in this example, that the expanded
sum of products
contains seven
of the sixteen possible combinations of the four variables. Although the
"+"
stands for the "inclusive or," the nature of an expanded

is
sum of
products
such that
1,
all
terms are mutually exclusive; that
is, if
one of the
terms equals
C=
1,
and
D = 0,
all
equalling 1;
must equal 0. For instance, if A = 0, B 0, expanded product, ABCD, is the only one the other expanded products will have one or more variables
all
others
first
equalling 0, and thus

in
all
other products will equal

all
0.
Of course
0.
it is
possible,
an expanded sum
of products, for
terms to equal
Expanded Product of Sums

The expanded product of sums can be obtained from a product of sums a similar manner. For example, the product of sums
(A
expands into
(2)
in
+B+
C){A
+C+
D){A
C){A
D)
(A
(A
(A
+ B + C + D)(A + B + C + D){A + B+C + D){A + B + C + D) + B + C + D){A + B+C+ D)(A + B + C + D){A + B + C + D) + B + C + D)
Chap. 2
EXPANDED PRODUCT OF SUMS
29
Here again, the missing variables are supplied in

tions, this
all
possible combina-
time to each sum.
The product of sums

(A
above,
is
+B+
C){A
+C+
D)(A
C)(A
D)
equivalent to the
sum of products
ACD + ABD + AC
used in the previous example. Equivalent expressions were purposely chosen
for these examples to illustrate an important
complementary relationship
which
will
now be
explained.
(1)
The expanded sum of products

combinations of four variables.
(3)
contained seven of the sixteen possible
A sum of the other nine combinations A BCD + ABCD + ABCD + ABC 5 + ABCD + ABCD + ABCD + ABCD + ABCD
sum of products.
definition,
represents the complementary expanded
two expressions are complementary if, whenever one expression equals 1, the other equals and vice versa, both expressions never both equalling 1 or both equalling 0. Of the sixteen possible combinations of four variables, one and only one combination will equal 1 at a
given time, the other fifteen combinations equalling
0.
By
Since
all
of the
(1)
and is must equal 1 and no combination included in both, one of the sums (3), and the other must equal at all times. Thus, the two expanded sums of
combinations are included in the two expanded
products are complementary.
sum of products
For example, if A = 1, B = 1, C = 1, and D = 1, the first term in the expanded sum of products equals 1, and the other six terms equal 0. Also, the nine terms in the complementary expanded sum of products equal 0. Thus, in this case the original sum equals 1 and the complementary sum
original
equals
0.
If the
complementary expanded sum of products
(3) is
complemented
(2),
using DeMorgan's theorem, the expanded product of sums

to the original expanded
equivalent
sum of products
(1), is
obtained. Each
sum
in the
expanded product of sums (2) is the complement of a combination (product) missing from the original expanded sum of products (1). The expanded product of sums can therefore be obtained from the expanded sum of products by the complementation of the sum of all the missing products. Also, the expanded sum of products can be obtained from the expanded product of sums by the complementation of the product of
all
the missing sums.
Note that the number of products in the expanded sum of products plus the number of sums in the expanded product of sums equals 2", the total number of combinations of n variables. In the preceding example, for
30
SPECIAL FORMS OF
BOOLEAN EXPRESSIONS
Chap. 2
instance, there were seven products in the
expanded sum of products and
nine sums in the expanded product of sums; seven plus nine equals sixteen,
the total
number of combinations of four variables. The expanded sum of products is also referred to
as the "standard
sum," a
"canonical sum," "disjunctive normal form," and "minterm canonical form"
each product in the expanded
sum of
products
is
also referred to as
is
"minterm." Similarly, the expanded product of sums
referred to as the
"standard product," "canonical product," "conjunctive normal form," and
"maxterm canonical form"; each sum

is
in the
expanded product of sums
referred to as a "maxterm."
"Minimum" Boolean Expressions
A
(1)
defined in several different ways.
"minimum" sum of products form of a Boolean expression may be Some definitions follow.
A A
minimum sum
minimum sum
of products of products
is
one that contains the minimum

one that contains the minimum
number of literals.
(2)
is
(3)
number of terms (products). A minimum sum of products is one in which the number of literals plus the number of terms minus the number of one-literal terms is a minimum.
defined in terms of
"minimum" product of sums can be analogously

and
will
literals
factors (sums).
type of minimum dependent upon the type of logical circuitry being used. For instance, if relay circuits are being used, the criterion may be
As
be seen
later, in logical circuit design, the
expression desired
is
the
minimum number of literals. For transistor circuits, the minimum number of terms or factors may be desired. For diode circuits, the third definition would give the minimum number of logic block inputs.
1
Often, but not always, the expression that satisfies one definition will
satisfy all definitions.
For
of
instance, in
one case an expression containing

contain the
the
minimum number
literals will also
terms; in another case, an expression with the

will contain
literals.
minimum number of minimum number of literals
more terms than another equivalent expression with more

is
Frequently, in the design of logical circuits a choice
made between
minimum sum
J
of products and a
minimum product
of sums no matter
is
Except for the special case of a single product, in which case the one term
not
counted.
Chap. 2
"MINIMUM" BOOLEAN EXPRESSIONS

criterion
31
what the
a
is
for the
minimum. For example,

a
if
an expression with
sum of products with the minimum number of literals and a product of sums with the minimum number of literals are compared, and the expression with the smaller number of
of
literals is desired,
minimum number
literals is
chosen for
circuit implementation.
As an example,
the
minimum sum of products
ACD + ABD + AC
would probably be chosen
equivalent
for circuit implementation in preference to the
minimum product
of sums
{A
+B+
C)(A
+C+
D)(A
C){A
+ D)
A minimum sum of products can be obtained from a sum of products by the application of the simplification theorems. A minimum product of sums can be similarly obtained from a product of sums. In practice, if the expression is quite complex it may not be easy to obtain a minimum by
algebraic manipulation, or, even if a
minimum
7,
is
obtained, one
may
not
be sure that
it is
a minimum. However, other methods of simplification,

lead
which
will
be taken up in Chapters 6 and
more
systematically to
a minimum.
sum of products can be obtained from an expression not already in form by simply "multiplying out" the expression, that is, applying Theorem 9a in reverse. A product of sums can be similarly obtained by the dual operation of "adding out," that is, applying Theorem 9b in reverse. However, since "multiplying out" is a more familiar operation than "adding out" (it being permissible in ordinary algebra), the following method for obtaining a product of sums form may be preferred.
this
(1)
Obtain a sum of products form by multiplying out.
(2)
Complement
complement
this
expression,
using
DeMorgan's theorem. This

will
(3)
be in a product of sums form. Multiply out this complement. The complement sum of products form.
will
now be
in a
(4)
Complement this complemented sum of products form, using DeMorgan's theorem. Since the complement of a complement is equivalent to the original, a product of sums form equivalent to the
original expression
is
obtained.
The procedure may be modified by utilizing the dual rather than the complement. Starting with a sum of products form, obtain the dual expression. The dual will be in a product of sums form. Multiply out the dual to get it in a sum of products form. Finally, obtain the dual of the dual to get a product of sums equivalent to the original. By using the dual, rather
32
SPECIAL FORMS OF
BOOLEAN EXPRESSIONS
Chap. 2
than the complement,

in the procedure.
it is
not necessary to complement

will
all literals
twice
For an example, a product of sums

products,
be obtained from the
sum of
ACD + ABD + AC
Obtain the dual
(i
process.):
+ C+
D){A
+B+
D){A
C)
Multiply out the dual (Some obvious simplifications can be
made
in the
ABC + ACD + AC + AD + CD
Obtain the dual of the dual to get the product of sums
(A
If a
+B+
C)(i
+C+
Z>)04
is
+
it
C)(A
)(
+ C+
)
is
minimum product
redundant.
It is
of sums
desired, the
is
above expression
ex-
amined for further

last factor is
simplification,
and
found that
either the first or
suggested that the reader verify this for practice.
There are thus two
minimum product
of sums
(A {A
+ B + C)(A + C + D){A + C){A + + C + D){A + C)(A + D)(B + C +

in the dual
D) D)
Application of the simplification theorems can, of course, be

the expression
is still
made
while
sum of products form.
By the judicious selection of pairs of factors to multiply together, the amount of work involved in the multiplying out process can be considerably
reduced. In general,
in
it is
desirable to multiply together factors with variables
common, complemented
For example,
{A
or not.
in the expression
+B+
C){D
+ E){A + B + F)(D +
factors,
G)
last
multiplying together the
first
two
and multiplying together the
two
factors, gives as a first step
(AD
+ AE + BD + BE + CD +
CE)(AD
first
+ AG + BD + BG + DF-\-FG)
A and B
(variable
whereas, multiplying together the
common), and multiplying together D common), gives as a first step

(A
Earlier in the chapter,
first
the second
and third factors (variables and fourth factors
+B+
CF)(DG
+ DE)
from the
an expanded product of sums (2), was obtained of sums above. It is suggested that for practice the reader expand the second minimum product of sums, and verify that the same expanded product of sums is obtained.
of the two
minimum product
Chap. 2
FUNCTIONS OF
n VARIABLES
33
Minimum Factored Form
A minimum sum of products or a minimum product of sums can generally

minimum factored form is minimum number of literals. This form is
be factored. The
implementation.
that expression with the absolute
often desirable for relay circuit
form.
no formal method for always obtaining the minimum factored of products or minimum product of sums can be factored in all possible ways, and the solution with the minimum number of literals selected. However, it may be possible to add redundancy before factoring, and obtain an expression with fewer literals.
There
is
minimum sum
Example:
If the expression
VW+VX+WY+WZ + XYZ
is
factored in
is
all
possible ways, the expression with the
minimum number
of literals
found to be
However,
if
X{V + YZ) + redundant Y is

factored
W(V+ Y + Z) (8 literals) added to the WZ term, giving VW + VX + WY + WYZ + XYZ

form
the
minimum
(X + W)(V + YZ)
is
+ WY
(7 literals)
obtained.
Functions of n Variables
With n
variables there are 2 n possible combinations,

"
}
nations can form 2 (2
different functions.
and these combiFor example, with two variables
X and
Y, there are four possible
combinations
XY
XY
XY
XY
and these combinations can form sixteen different functions. These functions are shown, arranged in two columns so that each row contains a complementary pair.
34
SPECIAL FORMS OF
BOOLEAN EXPRESSIONS
Chap. 2
Sixteen Functions of Two Variables
XY=XY
XY
Xf+XY+XY + XY= XY+XY+XY =X +?

1
XY
XY
= XY = XY = XY + XY= + XY = XY + XY
XY + XY= X
XY
XY
XY + XY + XY= X + Y XY +XY + XY=X +Y XY + XY + XY = X + Y XY + XY =X XY =Y + XY XY+XY =XY + XY

"
}
The table below gives a few corresponding values of n, 2n and 2 (2 Note that if the number of variables is increased by one, the number of
,
.
functions
is
squared.
Number of
Variables
Number of
Combinations
Number of
Functions
2<2">
2n
1
4
16
2
3
4
8
256
65,536
4,294,967,296
4
5
16
32
PROBLEMS
1.
Minimum sum
(a)
of products
+ 5C.
Express as
usfc
(b)
(c)
minimum product of sums (making expanded sum of products.

expanded product of sums.
of dual).
2.
Express
(a)
A(B
C)
+ D as:
(b)
(c)
minimum sum of products. minimum product of sums. expanded sum of products.

of products:
(d) *3.
Minimum sum
(a)
AC + AD +
BD. Express
as:
minimum product
of sums.
Chap. 2
PROBLEMS
35
(b)
(c)
expanded sum of products. expanded product of sums.
*4. Express
(a)
BC + BD + AC -f AD
as:
(b)
(c)
minimum sum of products. minimum product of sums. expanded sum of products.

(d)
Logical Circuits
Boolean variables have been related to basic statements that false. If a basic statement were true, its corresponding variable was equal to 1 if a statement were false, the corresponding variable was equal to 0. An entire Boolean expression was related to a compound statement that was either true or false. If the Boolean expression equalled 1,
So
far,
could be either true or
the
compound statement was compound statement was false.

~~"
true;
if
the
expression
equalled
0,
the
Now,
Switching
circuit
the
relationship
of
Boolean
thought
-*
Outputs
algebra to switching circuits will be discussed.
Inputs
switching circuit
may be
of in terms of the schematic diagram in

Figure 3-1
given time. For instance, a line
Each input and output line must be in one of two possible states at any may be "on" or "off," "high" or "low,"
Fig. 3-1.
"+"
or
" ,"
"conducting" or "not conducting."

time, the discussion will be limited to combinational
For the present
36
Chap. 3
LOGICAL CIRCUITS
37
circuits, in
which the
state of
an output
is
determined solely by the states
of the inputs.
Switching circuits having only a single output will be
discussed at this time.

logical circuit is a function of its inputs. Boolean a function of its variables. The output conditions of a logical circuit can thus be represented by a Boolean expression, each input being
The output of a
is
expression
represented by a variable. Simplification of a Boolean expression

related to the simplification of the corresponding logical circuit.
is
thus
Switching circuits are

blocks." Five
in
made up of
interconnections
of basic
"logic
common
functions that are performed by logic blocks used
computers and other similar equipment are the and, or, not, nand, and nor functions. These functions will now be presented, and a diagram symbol and logic truth table shown for each.
and Function
The function
equal
0.
(Fig. 3-2) equals
only
Conversely, the function equals
only
when all of the variables equal 1 when one or more of the variables
it
simplicity, a two-variable and function is used for illustration, but should be recognized that the function also applies to more than two
For
variables.
The same
applies to the or,

Logic truth toble
nand, and nor functions.
A-
B
C C
AND
AB
00
01
B
*
OR
-+c
tJ
Log ic truth toble
AB
00
01
10
11
C
1
A AND B
AB
AND
Function
10
11
1
C C
/1
OR
A + B
OR Function
Figure 3-3
Figure 3-2
or Function
The function
equal
equal
1.
(Fig. 3-3) equals
only
when one or more of the only when all of the
variables
variables
0.
not Function
The function
(Fig. 3-4) equals
only only
when the (single) variable when the (single) variable
equals
0.
1.
equals
38
LOGICAL CIRCUITS
Chap. 3
A
C
=
-
NOT ~** 6
Logic truth toble
Logic
NAND
truth toble
A
1
C
1
AB
00
Q1 10
11
C
1
NOT A
C
|
= =
NOT (A AND 5)
T.
1
A
NOT Function
Figure 3-4
AB-
A+B
NAND Function
Figure 3-5
NAND Function
This
only
is
"nand" is when all of the variables equal 1. Conversely, the function equals 1 only when one or more of the variables equal 0. The nand function is also called the Sheffer Stroke function, and its For example, A\B is equivalent to AB. Boolean symbol is
|.
and or not and function: not (A and B). "not and." The function (Fig. 3-5) equals a contraction of
a complemented
nor Function
This
is
is
a complemented or or not or function: not (A or B).
NOR
a contraction of "not or."

Lo lie
truth toble
A-
B
C
NOR
The function (Fig. 3-6) equals only when one or more of the variables equal
1.
AB
00
C
1
only
the
NOT (A
ORB)
C=
A+B=AB
NOR Function
Figure 3-6
01 10
11
when all of the variables equal 0. The nor function is also called
Pierce
.
Arrow function, and its Boolean For example, A { B is symbol is [

equivalent to
A +
B.
Logic Blocks Logic blocks that perform the functions just described will now be discussed, the discussion being limited, at this time, to how the blocks behave logically. What is in the blocks and why they behave as they do will
be considered in the next chapter.
For purposes of
reference, consider the .input
and output
lines
of the
logic blocks as being at
one of two possible voltage levels. The actual value important here; "+" will be used to represent the is not of the two levels " " to represent the more negative. more positive of the two levels, and
Chap. 3
LOGIC BLOCKS
39
An
input
may
be related to
its
corresponding variable in either of
two ways:
input: input:
+ = corresponding variable: = corresponding variable:

= corresponding variable: + = corresponding variable:
its
or
input:
input:
1
An
output can be similarly related to
corresponding Boolean expres-
sion in either of two ways
output:
output
or
+ = corresponding expression: = corresponding expression = corresponding expression: + = corresponding expression:

is
output: output:
circuit
output requirement
usually specified in terms of the condi1,
tions for
which the corresponding Boolean expression equals convention will be used throughout. For the time being, consider only the
and
this
+= - =0
1
is
assignment at both the output and inputs. With this assignment, a circuit said to use "positive logic." It is customary to name logic blocks according
to the function they perform with positive logic; hence, the nomenclature
of the blocks to be discussed.
and
Circuit
The first logic block has the following characteristic: the output is + when all of the inputs are + conversely, the output is only when one or more of the inputs are The "voltage truth table" for this logic block is shown in Fig. 3-7.
only
;
.
Voltage truth table
-+*c
AB
-+ +++
Positive logic truth table
AB
00
+
01 10
11
C'AB
AND
Circuit
Figure 3-7
Figure 3-8
40
LOGICAL CIRCUITS
Chap. 3
The positive logic truth table for this block is shown in Fig. 3-8. It can be seen from the truth table (Fig. 3-8) that, with positive logic, this block performs the and function; such blocks are therefore called and circuits.
or Circuit
The next logic block has the following characteristic: the output is + when one or more of the inputs are + conversely, the output is only when all of the inputs are The voltage truth table and positive logic truth table for this logic block are shown in Fig. 3-9. It can be seen from
only
;
.
Voltage
truth table
-*-c
AB
--+ +++
OR
C
-
AB
00
01
C-A+B
1 1 1
+ + +
10
11
Circuit
Figure 3-9
the positive logic truth table that, with positive logic, this block performs the
or function; therefore, these blocks are called or The naming of the next two logic blocks follows
nand
circuits.
the
same reasoning.
Circuit
The output
output
is
is
only
when
all
of the inputs are

are
only when one or more of the inputs
+ conversely, (Fig. 3-10).

;
the
Voltage truth table
**c
AB
C
+ + + -
AB C-AB'A+B
00
01 10
1
-+ +++
NAND
1 1
Circuit
3
Figure
10
nor
Circuit
The output
the output
is
is
only
only
when one or more of the inputs are + when all of the inputs are (Fig. 3-11).
conversely,
Chap. 3
NEGATIVE LOGIC
Voltage truth table
41
AB
-+ +++
NOR
C
+ -
AB C=A+B = AB
00
01 10
11
1
Circuit
Figure 3-11
not Circuit Inverter
when
This logic block (Fig. 3-12) has only a single input. The output is the input is ; conversely, the output is only when the input
only
is
Although
function,
this
it is
block performs logical complementation, that

referred to as
is,
the
+. not
commonly
an
inverter.
*~c
voltage truth table
A
+ NOT
c
+
A
1
C--A
1
Circuit
inverte
Figu re 3- 12
Negative Logic
If the opposite assignment,
= + =0
1
made, a circuit is said to use "negative logic." Referring to the logic blocks previously described, with negative logic:
is
an and circuit performs the or function an or circuit performs the and function
a
nand
circuit
performs the
and a nor
circuit
performs the
nor nand
function
function
not
circuit
negative logic
performs the not function regardless of whether positive or is used. The functions of these logic blocks will now be
logical circuits, the practice followed here
is
examined in more detail. In the diagramming of
that
42
LOGICAL CIRCUITS
Chap. 3
the
name of
the function performed, rather than the
name of
the logic
block
itself, is
written in the diagram symbol. Negative logic assigned to

circle
an input or output line is identified by a small of the line and the symbol.
drawn
at the junction
and
Circuit
Reference to the negative logic truth table (Fig. 3-13) shows that, with negative logic, an and circuit performs the or function. Note that the
voltage truth table for a particular logic block remains fixed;
it is
the
assignment of the
"+" and " "
that prescribes the function that the logic
block performs.
Voltage
truth table
Negative logic
truth table
AB
AB
00
01 10
1
C--AB
AB C--A+B
1
1
-+ +- ++ +
1
1
10
01
1
00
0-
AND Function
^'
A
OR Function
^ A$ *S_x"**'
AND
Circuit
Figure 3-13
Example
(a)
An and circuit is used to perform the and function AB. Positive logic must be used. The expression AB equals 1 if A equals 1 and B equals 1.
The output
is
+
AND
if
is
and B
is
(Fig. 3-14).
Figure 3-14
Figure 3-15
(b)
An and
logic
circuit is used to perform the or function A + B. Negative must be used. The expression A + B equals 1 if A equals 1 or B equals 1. The output is if A is or B is (Fig. 3-15).
Note that both diagrams above denote the same logic blockan and circuit. Following are summaries of the or, nand, nor, and not circuits, and the functions they perform with positive and negative logic.
Chap. 3
NEGATIVE LOGIC
43
or Circuit
Voltage
truth table
Positive logic
Negative logic
truth table
truth table
AB
C
-
AB C=A+B 00
01 10
11
1 1 1
AB C=AB
1 1
1
-+ +-
+ +
10
01
++
00
AND Function
OR Function
-0~
OR
Circuit
C gÂHOfr+-C
Figure 3-16
nand
Circuit
Voltage
truth table
Positive logic
Negative logic
truth table
truth table
AB
AB C--AB--A+B
00
01 10
1
AB C=A+B=AB
1
+
-+ + +- + ++
10 01
00
NAND Function
A, B-
NOR Function
UandUw
NAND
Circuit
A
r
B4>'
N0RO-W7
Figure 3-17
nor
Circuit
Voltage
truth table
Positive logic
truth table
Negative logic truth table
AB C
AB
00
01 10
1 1
C--A+B--AB
1
AB C =AB =A+B
\
+ -+ +- ++
1 1
10 01
00
NOR Function
A-
NAND Function
NOR
NANDC I-+-C
NOR
Circuit
Figure 3-18
:.
44
LOGICAL CIRCUITS
Chap. 3
not Circuit Inverter
Voltage
truth table
Negative logic truth table
A
1
C=A
1
A C =A
\ 1
NOT Function
AI
I
NOT Function
NOT
U*C AONOTO-*^
NOT Circuit- inverter

Figure 3-19
An
inverter functions the
same regardless of the type of
logic used.
Application of Positive and Negative Logic
To
further illustrate the application of positive
and negative
logic, the
design of a simple circuit will be examined using both types of logic.

Circuit requirement:
Three inputs
A B C
(Storage loaded)
(Error)
(Computation
if
finished)
finished.
Output: If storage loaded, or
no error and computation
Boolean expression for output:
A + BC
Positive logic implementation (Fig. 3-20)
If storage loaded, input
If error, input
A is +. C is +
is
B is +.
finished, input
If
computation
is
If storage loaded, or
Output
-f if
is
no error and computation finished, output -f or if B is and C is +.

,
+.
NOT
"U
AND
T^
OR
N0T<>
ANDO
OR
Circuit using positive logic
Circuit using negative logic
Figure 3-20
Figure 3-21
Chap. 3
MIXED LOGIC
45
Negative logic implementation (Fig. 3-21):

If storage loaded, input
If error, input If
is
C is
finished,
B is
no error and computation or if B is + and C is

,
computation
is
finished, input
If storage loaded, or
output
is
Output
if
is is
Since negative logic
being used, an or circuit

circuit
is
is
used to perform the
and
function,
and an and
used to perform the or function.
Mixed
Logic
Sometimes "mixed logic" is used, that is, positive logic is used for the and negative logic for the output, or vice versa. For instance, if with a nand circuit, positive logic is used at the inputs and negative logic is
inputs,
used at the output, the and function performed (Fig. 3-22).
is
Voltage truth table
Logic truth table positive logic Inputs: Outputs: negative logic
With the option of employing
posi-
AB
AB C=AB
00
01
tive or negative logic at the inputs,
and
positive or negative logic at the output,
the and, or,
nand, and nor circuits each can perform the and, or, nand, or
-+ + +- + ++
10
\
1
nor
functions. Figure 3-23
is
a summary
AND Function
of the functions performed by these logic

blocks with
all
combinations of positive
sA AND( ^*-C
Figure 3-22
and negative
logic.
Function
AND
OR
nand
NOR
AND
AND
= >- **
OR -<
nand<
**
'nor
u
.0 o> _l
OR
^NDC >*
>
'nand
>
NOR
<
>*
NAND
z
i
AND(
~ S
0R
;
A
(
NAND
NO r<
;
NOR
'and
>
OR
>-*
'nandc
>
NOR
Figure 3-23
46
LOGICAL CIRCUITS
Chap. 3
Suppose
circuit the
it
is
desired to implement the

is
and
.
function. Using
an and
circuit
output
is
only
when
all inputs are
+. Using an or
when all inputs are Using a nand circuit the output is only when all inputs are +. Using a nor circuit the output is + only when all inputs are The other functions can be similarly
the output
only
analyzed.
For illustration of some of the variations possible in logic implementation,

the "exclusive or" function
will
AB + AB will now be examined. Positive logic be used throughout. Using and, or, and not functions, the "exclusive or" can be realized as
in Fig. 3-24.
A more economical realization can be obtained (Fig. 3-25) by recognizing

the following Boolean identities.
AB+ AB = (A + B){A + S)
= {A + B)AB
A B
AND NOT
rL OR
IT
A B
-AB+AB
OR
1
AND NOT
AND
>[A+B)AB
AND
NOT
Figure 3-24
Figure 3-25
Any Boolean
nor
function can be realized with
nand
functions only or with
functions only. 1
The not function
is
obtained by using only one input
of the logic block. Figure 3-26 shows the realization of the "exclusive or"
function using
realization.
nand
functions only. Figure 3-27
is
a more economical
A B
NAND
NAND
AB
NAND
B
NAND
NAND
+AB-AB--AB+AB
Ib
Figure 3-26
Any Boolean
or and not
function can also be realized with

functions only.
and and not
functions only, or
with
Chap. 3
MIXED LOGIC
47
A B
NAND
AB
NAND
AB'A
NAND
^
u p
1
NAND --yJ.4 /! =4+4
AB-B
Figure 3-27
It is interesting to
note that a two-stage
nand
circuit is equivalent to
an
and-or circuit (Fig. 3-28). Also, a two-stage nor an or-and circuit (Fig. 3-29).
NAND
circuit is equivalent to
AB
NAND
*>ABCD
--AB+CD
AB+CD
NAND
CD
Figure 3-28
A-
NOR
A+B
NOR -> 'A+B+C+D
=
c
(A+BUC+O)
C-
{A+B)(C+D)
|
D-
N0
Cl-D
Figure 3-29
D-
The Boolean expression corresponding to the most economical circuit implementation generally varies with the types of logic blocks used. Also, the various types of logic blocks themselves generally differ in cost. In
multi-output circuits, where the outputs can "share" logic blocks in the most economical over-all circuit implementation may not be
common, made up
of the most economical implementations for each individual output. Furthermore, a given logic block has physical limits on the number of
allowable inputs, and on the types and number of other logic blocks that can be "driven" from its output. Therefore, experience and ingenuity are often helpful in arriving at the most economical logical circuit.
Electronic Logic Blocks
In the previous chapter, some

the functional standpoint.
will
common
logic blocks
were studied from

these blocks
The
is
internal structure of
some of
now be examined
to see
why
they function as they do. Since logic
rather than "hardware,"
of primary interest, and also because of the

is
ever-changing technology, no attempt
made
here to examine any
more
than a representative sample of existing logic blocks. Most blocks will be illustrated with only two inputs. However, be understood that a greater number of inputs
is
it
should
generally possible.
Diode Logic Blocks

Figures 4-1 and 4-2
show two
logic blocks
employing diodes.
In the
if all
first circuit,
the output will be at the
same voltage
circuit.
level as the
is
lowest input voltage
level.
Therefore, the output voltage level
only
input voltage levels are
+, and
this is
an and
48
Chap. 4
VACUUM
TUBE LOGIC BLOCKS
49
AB
-+
C--AB
C--A+B
=o
In the second
+++
C
Circuit
AND
Figure 4-1
circuit, the
highest input voltage level. Therefore, the output
output will be at the same voltage level as the is if any input is +,
and
this is
an or
circuit.
Vacuum Tube
Logic Blocks
if
is is
employing vacuum tubes. which uses a single vacuum tube triode, the grid input is at the low voltage level, conduction through the triode prevented, no current flows through the load resistor, and the output
logic blocks
Figures 4-3 through 4-6
show
In the
first circuit (Fig.
4-3),
at the high voltage level. If the grid input is at the high voltage level, conduction takes place through the triode, current flows through the load resistor causing a voltage drop across it, and the output is at the low voltage
level.
Thus, this circuit
is
an
inverter.
In the second circuit (Fig. 4-4), multiple triodes have their plates connected to a common load resistor. If all grid inputs are at the low voltage
level
none of the
triodes conduct, there
is
no current through the load

+
*-c
C--A
=tH~
->'
Inverter
A B C*A+B--AB
- + + -
+ +
NOR
Circuit
Figure 4-3
Figure 4-4
50
Chap. 4
and the output is at the high level. If any grid input is high there be conduction through that triode, current will flow through the load resistor causing a voltage drop across it, and the output will be at the low
resistor,
will
voltage level. Thus, this
is
nor
4-5),
circuit.
In the third circuit (Fig.

a third grid which
level,
is
a pentode
is
used. (This
vacuum tube has
not shown.) If either grid input is at the low voltage conduction through the pentode is prevented and the output is at
the high voltage level. If both grid inputs are at the high voltage level, the pentode conducts and the output is at the low voltage level. Thus, this is
nand
circuit.
In the fourth circuit (Fig.
4-6), multiple triodes
have their cathodes
A B
C--AB--A^B
++
I
j ^
1
NAND
Circuit
Figure 4-5
connected to a
common
load resistor. If
at the
all grid inputs are at the
voltage level none
of the triodes conduct,

is
low no current flows through the

level. If
load resistor, and the output
low voltage
any grid input
is at the high level there will be conduction through that triode, current will flow through the load resistor causing a voltage drop across it, and the
output will be at the high voltage level. Thus, this is an or circuit. few more vacuum tube circuits are shown to illustrate some of the flexibility possible with vacuum tube logical circuits (Fig. 4-7). It may be
helpful in analyzing such circuits to
first
write the logical expression describ-
ing the conditions for which current flows through the load resistor, and or for this conduction. If it is +, then determine whether the output is
the output expression
is
equivalent to that for conduction;
if it is
the
output expression
in the first of the
is
the
complement of that for conduction. For example,

conduction through the load pentode conducts. The triode conducts if A is and C are +. Therefore, the expression for con-
two
circuits above, there is
resistor if the triode or the
the pentode conducts if
Chap. 4
TRANSISTOR LOGIC BLOCKS
51
*"
D --A+BC
A[B+C)
=AB+CD:{/l+B)(C+0)
Figure 4-7
duction in the load resistor
is
A+
A+
BC,
describes the conditions for a
BC. The complement of this + output. The second
expression,
circuit
can
be analyzed in a similar manner.
Transistor Logic Blocks
The
versatility
of transistors will be seen in the study of the logic blocks
that follow.
There are two basic types of transistors nPn and pNp. The nPn transistor analogous to a vacuum tube triode. The collector is analogous to the plate. The emitter is analogous to the cathode. The base is analogous
:
(Fig. 4-8) is
to the grid. to collector.
A+
The pNp
base allows conduction, electron flow being from emitter transistor (Fig. 4-9) is analogous to a hypothetical
+
Base
Collector
(
Base
,J Collector
IN. Emitter
l\ Emitter
nPn transistor
Figure 4-8
pNp
transistor
Figure 4-9
vacuum tube triode that operates with all voltages reversed. allows conduction, electron flow being from collector to emitter.
transistor;
side.
base
An inverter is made by placing a load resistor on the collector side of the

an emitter-follower
circuits are
is
made by
placing the resistor
These
shown
in Figs. 4-10
and
4-11.
emitter-followers
do not perform a
logical function.
on the emitter Note that single However, when they
52
Chap. 4
-*-A
-*>*
-**A
*>A
T
nPn emitter
follower
nPn
Figure 4-10
inverter
pNp
emitter follower
pNp
Figure 4-11
inverter
are used in multiples, or with other circuits, they
Some
logical circuits using emitter-followers
do perform logical functions. and inverters are shown in

circuits
is
Fig. 4-12.
These
circuits
can be analyzed similarly to the vacuum tube
previously discussed. For example, in the last circuit of Fig. 4-12, there
or B is +. The output is conduction through the load resistor if A is output when there is no conduction; therefore, the expression for a
+
is
+ B = AB. A summary of the types of logical circuits obtainable with these transistor
and
inverters
is
emitter-followers
shown
in the table below.
Input
Emitter-
B
Inverter
Follower
nPn
nPn
Emitter-Follower
pNp
nPn
pNp
A+B
AB AB
A+B
AB
pNp
Input
A
Inverter
nPn
AB
pNp
A +B
A+B
(Fig.
Another type of
transistor logic block has
complementary outputs
4-13). "P-blocks," made up of nPn transistors, have or and nor and "JV-blocks," made up of pNp transistors, have and and nand
outputs,
outputs.
Still another type of transistor logic block uses resistors or diodes in conjunction with a transistor, the resistors or diodes performing an and
Chap. 4
53
*>A+B AB
B
+~A+B
T
nPn
NOR
inverters
circuit
nPn emitter OR circuit
followers'
+-AB
=_
A+B
N
'AB
pNp
ANO
emitter followers
circuit
pNp
NAND
inverters
circuit
17
p
/?
N
P
N
P
T
AB
-A+B
nPn emitter follower
ond
pNp
ond
emitter follower
pNp
inverter
nPn
inverter
Figure 4-12
or
or
function, with a transistor inverter complementing the output. These
logic blocks are thus
nand
or
nor
circuits.
Figure 4-14 shows some logic
blocks of this type.
The logic capabilities of transistor logic blocks are often extended by commoning collectors; this is sometimes referred to as "dotting." "Dotting" any of the logic blocks shown in Fig. 4-14 results in a second stage of logic,
54
Chap. 4
A+B
A3
P_
A
+-A+B
N B N
\N
**AB
=:
/'-block
NOR
OR
ABFigure 4-13
=0=
/l/-block
NAND
*-AND
AB
AB
AVW "
NAND
circuits
**A+B
A
-*M+
V\A/ B W\/
NOR
circuits
"W
Figure 4-14
Chap. 4
55
as illustrated in Figt 4-15. Some other transistor logic blocks are shown in Fig. 4-16. "Dotting" these logic blocks serves only to expand the input limit, as illustrated in Fig. 4-17.
4 AA/V
BAAAr-
DAAA
Figure 4-15
*>AB
A+B
4-AAAr
B
V\A/
+
NAND
circuit
NOR
Figure 4-16
circuit
56
Chap. 4
AA/W
Figure 4-17
5
Contact Networks
In this chapter, the relationship of Boolean expressions and contact networks will be examined. Contacts may be operated by several means such as switches, keys, cams, or relays. The following discussion will be
exclusively in terms of relays,
which can operate a number of contacts

devices,
simultaneously.
The implementation of simpler
such as switch
contacts, will be obvious.
The general schematic diagram for a switching circuit (Fig. 5-1) can still hold for relay contact networks if the circuit is thought of as it appears in Fig. 5-2. For the time being, only contact networks with a single output will be considered.
In electronic circuits, the inputs and outputs are thought of as being at one of two possible voltage levels. In contact networks, the individual contacts and the entire contact networks are thought of as being either
closed or open', again, there are exactly two possible states. In relating a Boolean expression, which may equal 1 or 0, to a contact network, which may be closed or open, the following assignment is usually made.
Boolean Expression
1
Contact Network
= =
57
closed
open
58
CONTACT NETWORKS
Chap. 5
\JUULr
\JUULr'
Inputs
Coils
i
Contacts
Outputs
Inputs
Switching
circuit
Outputs
\HSJLr
Contact network
input
Figure 5-1
Figure 5-2
to the relays,
In a Boolean expression, the variables, which may equal 1 or which may be operated or unoperated, as follows.
0, relate
Boolean Variable
Relay
operated
unoperated
For example, the Boolean expression A + BC relates to a relay contact and C = 1. The network as follows: A + BC = 1 if A = 1 or if B = or if relay B is operated A relay is if closed is related contact network operated. is unoperated and relay C The discussion of the implementation of such
JV
Figure 5-3
JL
Figure 5-4
contact networks will be limited, for the time being, to two types of relay contacts normally:
open, N/O, and normally-closed, N/C. (N/O contacts
are
also
called
"make"
state.
contacts;
N/C
The
contacts are also called "break" contacts.)
unoperated state of a relay
is
considered the normal
Thus, normally-
is unoperated, and closed when the contacts are closed when the relay is Normally-closed relay is operated. By convention, conoperated. is relay when the open unoperated, and
open contacts are open when the relay
tact
networks are drawn with the contacts shown in their normal state. might be drawn pictorially as in Fig. 5-3 and a N/O contact on relay
contact on
relay
N/C
in Fig. 5-4. circuit requirement: a circuit is to be simple following the Suppose is operated. The Boolean expression for the circuit requireclosed if relay
X X as
ment
is
simply
x
and the
circuit
would be drawn as
is
in Fig. 5-5.
JL1_
y
Figure 5-5
JTL
Figure 5-6
When
closed.
relay
operated, the
N/O
contact
is
requirement: a circuit
Suppose now, another, equally simple circuit Boolean is to be closed if relay X is unoperated. The
is
expression for this circuit
Chap. 5
IMPLEMENTATION OF AND, OR,
AND NOT FUNCTIONS
59
and the
circuit
would be implemented
is
as in Fig. 5-6.
When
1
relay
is
un-
operated, the
N/C contact
closed.
In the preceding two examples, note the rela-
an uncomplemented literal and its corresponding N/O contact, and the relationship between a complemented literal and its cortionship between
x
N/O X contact
responding
tacts
N/C
in
contact. This relationship gives
the convenient symbolic notation for relay con-
Jl-
--*"-
shown
in
Fig. 5-7.
Each uncomplemented
N/C X contact
Figure 5-7
literal,
a Boolean expression relating to a
contact network, corresponds to a
N/O
contact;
each complemented
literal in
the expression corresponds to a
N/C
contact
The
relationships thus far established are
summarized in the table below.
Relay
N/O
Contact
N/C Contact
Literal
X
Operated
X
Closed
X
Open
Closed
X
1
X
1
Unoperated
Open
Implementation of and, or, and not Functions

AND
are operated.
Suppose a relay contact network is to be closed only The Boolean expression for this circuit is
if
relays
A and B
AB
-A
AB
Figure 5-8
and the network requires a N/O contact on relay A and a N/O contact on relay B. For the network to be
closed only
when both
relays
A and B
are operated,
(Fig.
5-8).
must be placed in Thus, the Boolean and function is

these contacts
series connection.
series
realized in contact
networks by a
and
series
connection
OR
Suppose that a contact network
is
to be closed if relay
is
A or B is operated.
The Boolean expression
for this circuit
A+B
Again, a
N/O
contact
is
required
on each
relay.
For the network to be
60
CONTACT NETWORKS
closed
is
Chap. 5
if
relay
A or B
is
operated, a parallel connection
required (Fig. 5-9). Thus, the Boolean
or function
is
A+B
Figure 5-9
realized in contact networks
by a
parallel connection.
+=
or
= parallel connection
NOT
The not
if,
function, as previously shown,

if
is
implemented by the use of

is
normally-closed contacts. Thus,

say, relay
a relay contact network
to be closed
is
not
operated, the Boolean expression
would be
A
and the circuit would be realized by the use of a normally-closed contact on A. The circuit to realize the function A + BC, discussed L/9 rJ earlier in this chapter, would be as in Fig. 5-10. It should A+BC be noted that a Boolean expression is related to a singleinput
single-output
(two-terminal)
series-parallel contact
Figure 5-10
network.
The examples
in Fig. 5-11
show
the application of a few Boolean algebra
t:-:t=t:t B
A
A-
B-
Theorem 120
A+AB
2.
A+B
-cAB-r-
-rA B-r\-A
C-\
M
=
C-l
Theorem \Zo
i-B C J AB+AC+BC
AB+AC
rz'j'XTj
C-i-B-'
A B AC
A-rA
Theorem 14c
AB+AC
(A+C)(A+B)
Figure 5-11
theorems to the simplification of contact networks. In the

the normally-closed
first
is
example,
contact
is
redundant. If the
contact
closed, the
is
network
will
unoperated, the
be closed regardless of the state of relay A: if relay A AB path closes the network; if relay A is operated, the
illustrates the application
A
of
path closes the network. The second example
Chap. 5
TRANSFER
CONTACTS
61
The BC path is redundant since there is also B contact in the AB path and a C contact in the AC path. If both of these contacts B and C are closed, then the network will be closed because relay A must be in one state or the other, and either the normally-open A contact or the normally-closed A contact must be closed. In the third example, the
the included-term theorem.
transposition theorem
is applied to the resultant circuit from the second example. Note that the transposition reintroduces the included path BC.
We shall now go beyond the simplification of Boolean functions and examine further simplifications peculiar to contact networks: transfer contacts, bridge circuits, nonplanar networks, graphical complementation,
and multi-output networks.
Transfer Contacts
Relay contact terminology includes the P eratin 9 terms springs, contacts, and positions. There Normal iy-open
are three types of springs as
5-12.
[N/O)
shown
in Fig.
Norrno y . c osed {N/C)

,
Normally-open contacts are made up of two springs (Fig. 5-13); normally-closed

contacts are
5-14).
Figure 5-12
made up of two springs (Fig. Transfer contacts are made up of a normally-open
normally-closed contact sharing a

are
common
contact and a operating spring. Thus, they
made up of three springs (Fig. 5-15). Transfer contacts in which the operating spring opens one contact before closing the other contact are
With
these transfer contacts,
called "break-before-make" transfer contacts.
o-r*
Figure 5-13
Figure 5-14
a~s
Figure 5-15
is a brief period of time during relay operation when both the normally-open and normally-closed contacts are open. Transfer contacts in
there
which the operating spring closes one contact before opening the other
contact are called "make-before-break" or "continuity-transfer" contacts.
With
these transfer contacts, there
is
a brief period of time during relay

normally-closed
contacts
operation
are closed.
when both
the normally-open and
In a contact network, it is desirable to bring together in an optimum manner normally-open and normally-closed contacts on the same relay to make transfer contacts. A normally-open and a normally-closed contact
62
CONTACT NETWORKS
combined require four springs
in all; if they are
Chap. 5
that are not
make a
transfer contact, only three springs are required.

this is
An
combined to example of
shown
in Fig. 5-16.
Sometimes
relays are built
up of
springs as needed,
to minimize the
and it is desirable
springs.
number of
relays
In
other
cases,
come
For
sizes:
standardly equipped with a fixed
number of
transfer contacts.
instance, a particular type of relay
might be available in three

Four springs on
relay
Three springs on
relay
4, 6,
or 12 transfer contacts; these

referred
B
Figure 5-16
are
to as 4-,
6-,
or 12-
position relays. In each position,
a transfer contact is available. If one position on the relay is required. If a circuit specifies a N/O contact, again one position is required, the normally-closed spring being left unused. If a circuit specifies a N/C contact, one position is required, the normally-open spring being left unused. Thus, a N/O contact and a N/C contact that are not combined require two relay positions in all; if they can be combined into a transfer contact, only one position is required. Each literal in a Boolean expression corresponds to a contact in the associated series-parallel network. Therefore, the minimization of the Boolean expression leads to a minimum series-parallel contact requirement. Optimizing the number of transfer contacts enables us to minimize the number of springs or positions, whichever is the criterion. The minimization of positions is especially important if it leads to a smaller standard relay being required, since the cost of a relay is a function of its size. For instance, if seven positions on a relay are needed, a 12-position relay could be
circuit specifies a transfer contact,
required.
However,
if
the circuit can be redesigned to require only six
positions, then a 6-position relay could suffice.

If,
in a relay contact network,
P=
S
the total
number of positions
and
= the total number of springs C = the total number of contacts

P=
the following relationship exists
S-C
relationships discussed.
The following
table summarizes
some of the
Chap. 5
NONPLANAR NETWORKS
63
N/O
Contact
N/C Contact
Transfer
Contacts
Figure 5-17
Figure 5-18
Springs
Contacts
Positions
Bridge Circuits
Since, in contact networks, the and function is implemented by series paths and the or function by parallel paths, any Boolean expression can
be directly implemented only by a series-parallel network. Frequently, economy can be achieved by the use of bridge circuits. A bridge circuit is one in which there is at least one cross-connecting contact between two
series
paths (Fig. 5-20).
TIT
Boolean expression -for series-parallel equivalent:
rrr
Boolean expression
for
series-parallel equivalent:
AB+CD+ADE+BCE
Figure 5-20
AB+CD+BC
Figure 5-21
A cross-connecting contact
5-21 shows.
in a bridge circuit often conducts current in
both directions: for example, the E contact in the A-E-D and C-E-B paths in the circuit above. This is not a necessary requirement, however, as Fig.
The circuit in Fig. 5-21 is a bridge even though the cross-connecting A contact conducts current in only one direction. Current is prevented from flowing in the other direction because of the A and A contacts in series.
Nonplanar Networks
Economy
(Fig. 5-22).
is
also sometimes achieved by the use of nonplanar networks nonplanar network is one that cannot be drawn on a plane
64
CONTACT NETWORKS
lines.
Chap. 5
without crossing
The
it
fact that a circuit
is
drawn with crossovers does

it
not necessarily
make
a nonplanar network since
may be
possible to
redraw the
to
circuit to eliminate the crossovers. circuit
draw the
without crossovers
is
Only when it is impossible the network nonplanar.
LJJwJ
Boolean expression for series-parallel equivalent:
ABC+DEF+AFG+CDH +ABEFH+ BCDEG+ACEGH+BDFGH

Figure 5-22
Complementation of Contact Networks

If a contact or two-terminal contact
network
parallel
(1) (2)
is open, and vice versa. network can be obtained by:
network is closed, its complementary The complement of a two-terminal series-
Changing Changing
all
N/O
contacts to
N/C
contacts,
and
vice versa.
all series connections to parallel connections,
and vice versa.

Fig.
For example, the complementary network of
TIT
-BC
A+BC
Figure 5-23
-'TIT
C-
B-
5-23
is
Fig. 5-24.
is
A{B+C)
Figure 5-24
a graphical method, however, for obtaining the complement of any planar two-terminal contact network, including bridges. First, a mesh in a contact network will be defined as a closed
There
does not contain any smaller loop. contacts A and C is a mesh; containing Thus, in Fig. 5-25, the loop and the loop containing conmesh; a the loop containing B, D, and E is the addition, In tacts C, D, E, and F is a mesh. ,
loop that
area above the network

is
is
considered a mesh, as
the area below the network. Thus, the circuit point, or node, is in Fig. 5-25 has five meshes.
,-y B
I
CL- D E F
I
placed in each
mesh
as shown.
The nodes
in
adjacent meshes are connected with lines passing through contacts common to both meshes. This is done in all possible ways. These connecting
lines
must always pass through contacts; they may never "cut a wire." The input and output
terminals are considered as extending to infinity,
Graphical complementation
Figure 5-25
terminal. so that a connection cannot "circle around" an input or output 5-25. Fig. in shown is point this at progress The obtain the complementary network, the new connections are retained
To
Chap. 5
MULTI-OUTPUT
CONTACT NETWORKS
and
all
65
and the
that
original connections are deleted,
contacts are complemented,
is, all
N/O
contacts are changed to
N/C
contacts and vice versa.
The
top and bottom nodes become the input and output terminals of the complementary network. The resultant complementary network is shown
in Fig. 5-26.
Figure 5-27
bridge circuit.
is
an example of graphical complementation applied to a
B-
-H-+
\-C Di E-\
F
hH
D
G-*
1
f'H G
F
L
f
Complementary
network
L-
Graphical complementation
Figure 5-26
Figure 5-27
the
The number of contacts required for a complementary network is always same as that required for the original network, although the spring and
position count
may
differ.
nonplanar network must be converted to a planar equivalent before graphical complementation can be applied.
Multi-Output Contact Networks

Combining a Network and
Its
Complement
it is
In designing economical contact networks having more than one output, often desirable to combine a network and its complement. Consider first the combination of a simple series circuit containing two contacts, and
the complementary circuit

in parallel.
made up of
the two complementary contacts
Example:
V
X
Y
XY-
-XY
=
T T'T X
Y
.,
*-XY
+-X+Y
Figure 5-28
*X+XY=X+Y
To
effect the
circuit is
combination, the series circuit is not altered, but the parallel modified by making use of the theorem
66
CONTACT NETWORKS
Chap. 5
X+XY=X+
in reverse, as the
is
above example illustrates. The use of transfer contacts NJO and N/C contact pair is combined. This procedure can be extended to any series parallel network. Some examples are given in Figs. 5-29 and 5-30.
optimized since every
ABCDl_
I I
r Ai B
s
D~
A
I
B
I
C
I
D
I
Figure 5-29
A-
~' C
r-i':r R-i-n-i
A
I
-
A
I
'1
B
C
C
I
C
I
L_L
Figure 5-30
The procedure is useful not only in multi-output circuits, but also in a single-output network, a portion of which contains a circuit connected to
its
complement
(Fig. 5-31).
ABC-
"R
i_J
in
T'T B
A
I
B-C-
Figure 5-31
Combining Like Contacts
Series Paths
The method of combining
like contacts in series
paths
is
intuitively
obvious, and bears a relationship to factoring in Boolean algebra.
Example:
XY *-XY
-*xz
'XY
i;:
~xz
Figure 5-32
Chap. 5
MULTI-OUTPUT
CONTACT NETWORKS
67
Combining Like Contacts
in
Parallel
Paths
In one
Figs. 5-33
common method
and
5-34.
of combining like contacts in parallel paths,

is
the theorem
X + XY'= X + F
used in reverse again as illustrated in
-X-T-+.X+Y
r-Y-y+XY+Y=X+Y
Y
-r-J
r
If
x+y
r-r-f-^xY+YzX+Y
Y
-Xi
-wx+z
z i-z-L-^xz+z^x+z
Figure 5-33
/
-X+W+Z *-Z-*-^XWZ+WZ+Z
=
-z
x+w+z
Figure 5-34
the
parallel
paths
also
include, in addition to like contacts,
contacts, that
tains
a pair of complementary is, one path con-
> X+Y
,
a contact, and the other path contains the complementary

contact, another
r
X
Figure 5-35
XY+Y=X+Y
method of com-
bining can be used, as illustrated

in Fig. 5-35.
tact
C-IL X+Y
Y,
Lp-U.XY+Y=X+Y
The common con-
bridges across the two
paths, one of which contains the contact
and the
other, the comple-
mentary contact Y. This combining by bridging can be used whenever there is at least one contact and its complement in the two paths respectively, the bridging consisting of the circuitry common to both paths. It does not matter what other contacts might be in the two paths.
Example:
-Â+BC+D+E
>(A+BC){D+F) + D+E
B-C-D-E-A\-BC-\
-D-F-
-E-
A+BC+D+E
-D-\
+A+BC+D+F
-F
5-36
-*(A+BC)(D+E)
+D + F--
A+BC+D+F
Figure
68
CONTACT NETWORKS
Because of the
Chap. 5
in one output path,
circuitry
common
to both paths,
A +
and the D in the other path, the BC, can be used to bridge across the
outputs.
More than one of
these simplification procedures can sometimes be
applied to a single problem, as
shown
in Fig. 5-37.
-**A
-**A
*-A
-7L A+BC
*-BC
-L+A {B+O+BC-A+BC
Figure 5-37
\-ffJL C -L+/\c AC+ABC+BC =
A+BC
PROBLEMS
1.
Redraw
the following circuit pictorially (Fig. 5-38).
x-i-r-
T-T-Tl
-Z-*
Figure 5-38
*2.
Redraw
the following 9-spring circuit pictorially (Fig. 5-39).
A-r-A
-B--B-C-LcFigure 5-39
3.
Design a relay contact

(9 springs).
circuit
to
realize
the following expression
Draw pictorially.
ABC + ABC
4.
Using the graphical method, obtain the complement of the

Fig. 5-40.
circuit in
PROBLEMS
Chap. 5
69
BC D
E
I
6
I
U-U-J
Figure
5-40
circuit in
5.

Fig. 5-41.
-H
L
K-
Figure 5-41
*6.

Fig. 5-42.
circuit in
w
-X-r-Y-\
til
Z-i-Vcircuit
Figure 5-42
*7.

in Fig. 5-43.
TTTTn
A
i
i i
c-
-I
Figure
5-43
8.
Two
relay circuits,
made up of
circuit is to
states.
contacts on nine relays,
are required.
One
is
A through J, be closed only for a prescribed 205

is
combinations of relay
other circuit
This circuit
shown
in Fig. 5-44.
The
to be closed only for the other
307 combinations of
relay states. Design this circuit.
70
CONTACT NETWORKS
Chap. 5
LJ4-UJ
Figure 5-44
9.
r~r.7r*i E D C
two-output relay circuit
is
required, the expressions for the outputs
being:
Output 1 A(B + C) + Output 2: (A + 5C)(D

:
BE + )
relay.
Design the
10.
circuit using
one transfer contact per
Design the following two-output relay one position on each relay.

(a)
circuits, in
each case using only
Output 1 Output 2:
:
(b)
Output Output
2:
:
AB + C AD + E A + BC A+D+E
(c)
Output 1 A(B Output 2: A(B
+ +
C) C)
+D+E +E+F
5-45),
11.
Redesign the following multi-output network (Fig.

springs.
using 10
AB
\-A~-rB-\
'Li C
*-D-y-A
'i:t
Figure 5-45
Tabular Method
of Simplification
Optional Combinations
Until now, for a desired circuit function, all of the possible input combinations could be considered as being divided into two groups: one group consisting of those combinations for which a circuit output is desired, and
the other group consisting of those combinations for which
is
no output
desired.
For example, suppose a
circuit
output
is
specified by:
AC + ABC
This expression expands into
ABC + ABC + ABC

No
output
is
desired for the remaining five possible combinations:
ABC + ABC + ABC + ABC + ABC

which can simplify to
71
72
Chap. 6
AC + AC + AB
or
AC + AC + BC
Note that the expressions for output and no output are complementary.
Now,
all
divided into three groups
of the possible input combinations will be considered as being one group consisting of those combinations for
:
which an output
no output
group of those combinations for which and the third group of optional combinations. These optional input combinations arise from two possible conditions:
is
desired; another
is
desired;
1.
The optional combinations
are invalid; that
is,
they are
known
never
to occur.
2. The we do not
optional combinations are "don't care" combinations; that

care whether or not
is,
we
get
an output
if
these input combinations
occur.
It is
binations; they both influence a circuit expression in the
not necessary to differentiate between invalid and don't care comsame way. If
optional combinations are added to a Boolean expression for a circuit

output, the expression
may become
simpler or
therefore be determined which optional combinations to add,
more complicated. It must and which
not to add, in order to achieve optimum simplification.
Examples:
(a)
Suppose that there are two keys

is
desired that these keys light a
key
is
is
A and B which operate contacts. It lamp only if key A is depressed and not depressed. The Boolean expression for lighting the lamp
that the keys are mechanically interIt
AB. Suppose, furthermore,
locked so that only one can be depressed at a time.

bination
would thus be
impossible to depress both keys together, which means that the com-
AB
can never occur. If this optional combination
to the output expression
AB, the expression
AB is added AB + AB = A results.
A
Therefore, instead of requiring a normally-open A contact and a normallyclosed
B
is
contact in series to light the lamp, only a normally-open

required. It can be seen intuitively that this
is
contact
true, since if
key
depressed;
it is not necessary to stipulate that key B be not cannot be depressed since keys A and B cannot be depressed together because of the interlock. In this example, utilization of the optional combination led to
is
depressed,
it
simplification. In the next example,

(b)
it
will lead to complication.
Using the same two interlocked keys, suppose now that the lamp is to light only when neither key is depressed. The Boolean expression for
Chap. 6
73
lighting the
the
lamp is AB. If the optional combination AB is added to output expression AB, the expression AB AB results. Since
of the optional combination complicates the expression, rather than simplifies it, it is better not to add the optional combination, but leave the expression in its original form, AB.
utilization
and
In these two examples only one optional combination was involved, it was not very much work to investigate whether or not its utilization
optional combinations will be examined.
led to simplification.
Now, an example with two

The expression
for the output
is
ACD + BCD
and the combinations ABCD and ABCD are optional. Using neither optional combination, the original expression can be
factored, giving
(1)
{A
+ B)CD
Using both optional combinations,

(2)
ACD + BCD + ABCD + ABCD = ACD + BCD + ABC = C(D + AB)
an expression of the same complexity is obtained. Using just the optional combination ABCD,
(3)
ACD + BCD + ABCD = C[(A + B)D + ABD]

ABCD,
a more complicated expression results. Finally, using only the optional combination
(4)
ACD + BCD + ABCD = CD

simplification
is
maximum
achieved.
With two optional combinations, four trials were necessary to determine the optimum solution. In general, with n optional combinations, 2 n such
trials
are necessary. Obviously, n does not have to be very large before the
work involved in this sort of algebraic simplification becomes prohibitive. The tabular and map methods of simplification, however, handle optional
combinations with
facility,
as will be seen in the following sections.
Tabular Method of Simplification
The
tabular
method of simplification
is
based principally on the theorem
XY+XY = X
X representing one or more variables,
and
Y representing
a single variable.
74
Chap. 6
The
is
first
step in the tabular
simplified) in the
method is to get the expression (to be expanded sum of products form. The preceding theorem
all
then applied exhaustively to obtain

all
irreducible terms, that
is,
terms
to which the theorem cannot be further applied.
The theorem is applied first to which the theorem can be applied by one literal. For example,
possible pairs of terms.
Two
terms to
smaller
will
reduce to one term which
is
ABC + ABC = AB
Next, all terms reduced by one literal are examined to see whether they can be combined further, by the application of the theorem, to reduce to a still smaller term containing two fewer literals than the original terms. This procedure is continued until no further terms can be combined. The resulting irreducible terms are called "prime implicants." The last step in the method is to select in an optimum manner prime implicants that account for all of the original expanded terms. These prime
implicants will form a
minimum sum
of products.
In the reduction process, the following relationships hold:
= number of variables
of variables occurring in
all
m = number
2 m terms
(n
possible combinations in
m) = number of variables constant in the 2m terms

to a single term defined
The 2 m terms reduce

variables.
by the constant
m)
Example:
ABCDE + ABCDE + ABCDE + ABCDE = ABC

5, n (the number of variables) (the number of variables occurring in and E); these combinations occur in 2m
m
(Z)
all
possible combinations)
2
=2
= 2 = 4 terms.
the four terms,
to be simplified
The remaining (n m 3) variables are constant in and the expression reduces to ABC. In the tabular method of simplification, the expression
must
first
be expanded,
if it is
not already in expanded form. However,

it
instead of the expanded expression being written in algebraic form,
can
be written in tabular form. For example,
ABCD + ABCD + ABCD + ABCD

can be written
ABCD ABCD ABCD ABCD
Chap. 6
75
This table can be written in a still more convenient form by simply using A, B, C, and D as columnar headings, and then, in the table, using a 1 to represent an uncomplemented literal and a to represent a complemented literal. The preceding table would then be written
ABCD
11
110 110
In the study of the tabular method, the following expression will be
10
used as an example.
AB + A BCD + ABCD + ABCD + ABCD

first step is to expand this expression into a table. The AB term will expand into four terms; the last four terms are already in expanded form, and none of these is the same as a term resulting from the expansion of AB.
The
Therefore, the table has eight rows, as
shown below.
ABCD
1110 1111
10 10 10
1
110 110
111
10
Instead of examining all possible pairs of rows for application of the theorem, the work can be simplified by the following reasoning. For two
rows to combine, they must differ in only one column; in one row, that column must contain a 0; in the other row, that column must contain a 1. Thus, a necessary condition for two rows to combine is that one of the rows must contain one more 1 than the other row. If, therefore, the rows are grouped according to the number of l's per row, and the groups are
arranged consecutively according to the number of l's per row, it is necessary only to compare rows in one group with rows in an adjacent group.
The
table
is
thus reordered. Lines are drawn between adjacent groups to
aid in identification.
76
Chap. 6
A B c D
One
1
per row
{0
(1
Two
l's
per row
1
1
ll
(1
1
1
1 1 1 1
Three
l's
per
row
(o
Four
l's
per
row
{1111
Now we
the three rows in the next group.
look for rows that combine. The 0100 row is compared with The 0100 and 1100 rows differ in only
one column, column

is
therefore, these
written, in a
new
table, as
100.
D
<v
0v/
two rows combine into a row which
B
1
B
1
1 1 1
1 1
1
1
(V
Is/
1
1 1
1 1
1
1 1
w
1
1
1
1
(V
In/
1 1
1
1
__
1
w
ABC 5
and
The
entry
100
records that the terms
ABC 5
reduce to
BCD.
Since the 0100 and 1100 rows are accounted for by the new row 100, they are "checked off," signifying that they are not prime implicants. Since all of the prime implicants must be found, we continue to look for
possible combinations of rows, even with rows that have already been
off.
all
checked
that they differ in
The 0100 row and the 1010 row are compared and it is found more than one column; therefore, they do not combine. The 0100 row and the 1001 row are compared, and it is found that they do not combine either. Lines are drawn between adjacent groups in all tables; 100 row. therefore, a line is drawn under the The three rows in the second group are now compared with the three
Chap. 6
77
rows in the third group. Rows 1100 and 1101 combine to give 110 rows 1100 and 1110 combine to give 11 0; 1010 and 1110 combine to give 1 01. All other pairs of 10; and rows 1001 and 1101 combine to give 1 rows, one from the second group and one from the third group, differ in more than one column, and thus do not combine. Next, the three rows in the third group are compared with the 1111 row in the last group. Note that all rows with a single will combine with an all-1 row. Thus, new rows 11 and 111 are obtained. It should 1, 111 also be noted that a row with all 0's would combine with all rows con;
taining a single
In this example,
been checked
implicant.
off. If
all rows in the original table have combined and have any row had not combined, it would have been a prime
The next
step
is
to
compare the rows
in the
new table
in search for further
combinations. Again, for two rows to combine, they must differ in only
one column; in one row, that column must contain a 0; in the other row, column must contain a 1 All other columns must be identical, that is, in all other columns, both rows must contain 0's, both rows must contain l's, or both rows must contain in one row 's. Note especially that a must match with a in another row. The 's speed up the comparison process. For instance, in the only row in the first group of the new table, in the A column. 100, there is a In the next group, none of the four rows have a in the A column. Therefore, it can be seen immediately that 100 does not combine and is a prime implicant. A prime implicant is identified by an asterisk, as shown
that
.
below.
D
0*
10
1
11*
s/

1
1 1
0V
0*
1*
1
1
v
1*
Next, the four rows in the second group are compared with the three rows in the third group 1 10 combines with 1 1 1 to give 1 1 in a new
:

78
Chap. 6
table; 11
combines with
11
to also give 11
This 11
row
table.
1
is
not repeated, but
and 1 01 have 's in the B 's in the B column in any row in the third group, it is immediately seen that these two rows are prime implicants. 111 is also a prime implicant. In the newest table there is only a single row, which obviously cannot combine with any other row, and so it is also a prime implicant.
it
serves to check off
two more rows in the column, and since there are no
10
that all prime implicants have been obtained, the last step is to an optimum manner prime implicants that account for all of the original expanded terms. To do this, a different kind of table is constructed there is a column for each of the original terms, and a row for each prime implicant. For each prime implicant, a check mark is placed in the columns of those terms accounted for by that prime implicant. The completed table
select in
is
Now
shown below.
1100
s/
v/
s/
1101
1110
1111
1010
1001
0111
0100
v/
100*
110*
V V
s/
s/ s/
s/
>/
101*
111*
11
s/
A prime implicant with no

implicant with one
two
's
will
's will account for only one term; a prime account for two terms; a prime implicant with account for four terms, etc. For instance, the first prime
will
implicant
100 (BCD)
is
accounts for two terms 1100
(ABCD) and 0100
(ABCD).
Although there
gained
single
if it is first
a formal method for determining the optimum selecintuitively. First,
tion of prime implicants, a better understanding of the
looked at
problem can be any columns with only a

is
check mark are noted.
single
check mark indicates that there
only one prime implicant that will account for the term in that column;
prime implicant in that row is required in the final expression prime implicant." In the example, the last four columns have only a single check mark. The term 1010 is accounted for only by the prime implicant 1 10; 1001, by the prime implicant 1 01; 0111, by the prime implicant 111; and 100. The first four prime implicants are 0100, by the prime implicant
therefore, the
it is
an
"essential
Chap. 6
OPTIONAL COMBINATIONS WITH TABULAR METHOD
79
therefore required. Required prime implicants are identified by
an
asterisk.
The terms
are checked off as they are accounted for. Prime implicant
100
point,
accounts for the terms 1100 and 0100; 110, for the terms 1110
for 1101 and 1001; and 111, for 1111 and 0111. At this can be seen that all terms have been accounted for, and the first four prime implicants are the only ones required. Forming a sum of products with these four prime implicants gives the minimum sum of products equivalent to the original expression
and 1010; 101,

it
BCD + ACD + ACD + BCD

This particular problem was easy because the accounting for the columns
with single check marks effected the solution. In some problems,

all
many
or
columns may have many check marks, making the solution of this last step by intuitive methods more difficult. In the next example a formal method of accomplishing this last step will be examined, as well as the
method
for treating optional combinations.
Optional Combinations with Tabular Method
Any
optional combinations are added at the bottom of the original table

is drawn separating them from the The optional combinations and valid combinations
and, for identification purposes, a line

valid combinations.
prime implicants have been all prime implicants the optional combinations and valid combinations are treated alike. After the prime implicants have been obtained, the final table is constructed with columns for the valid combinations only, since only the valid combinations must be accounted for. The optional combinations are thus used only for the possible generation of additional prime implicants, or prime implicants with fewer literals.
are not differentiated again until after
all
obtained; that
is,
in reordering the table
and finding
Example:
In the following example there are nine valid combinations and two
optional combinations, 0000 and 0100.
the reader carry out the steps
results.
It is
suggested that, for practice,
referring to the book, and Note that in the final table, there are columns only for the valid combinations. The optional combinations account for the two missing check marks in the third row and the one missing check mark
shown without
then check his
in the fourth row.
80
Chap. 6
Example with Optional Combinations
D
On/
z>
z> *
1 1
>/
1 1
Os/
w
1
0v/
01*
Is/
w V
0s/
n/
11*
Os/
ov
1
1*
Is/
10
Is/
w
1
-V
Os/
0s/
-v/
Ox/
Is/
1 1
111
0001
v/
w
Is/
s/
0011
s/
0101
1010
1011
1100
1101
1110
mi
001
t/
V
s/ v/ v/ v/
v/
Oil
s/ v/
s/ v/ v/ n/
v/
s/
00 w 10 X 11 Y Z 11
Algebraic Solution of Final Table
The formal solution of the final table, interestingly enough, utilizes Boolean algebra. The prime implicants are the variables, and are given letter names; in the example, they are designated U, V, W, X, Y, and Z,
respectively.
For each valid combination, a Boolean expression is written indicating which prime implicants can account for it; this expression, by its nature, will be a sum. Thus, in the example, the combination 0001 can be accounted
Chap. 6
ALGEBRAIC SOLUTION OF FINAL TABLE
81
for by the prime implicants
U or
etc.
is
W, which
is
written in Boolean algebra as
(C/+ W);
implicants
the combination 0011
can be accounted for by the prime
or
V (U
all all
-\-
V);
product of
these
sums
formed, the resulting Boolean expression

for.
indicating
how
of the combinations in the table can be accounted

is
In the example, the product of sums obtained
(U
W){U + V)(W + X){ Y)(V + Y){X + Z)(X + Z)(Y +

simplification gives
(17
Z)( Y
+ Z)
Some obvious
W){U + V){W + X)(Y)(X + Z)

all
This expression "says" that
the combinations in the table can be
accounted for by the prime implicants (17 or
W) and (U or
V) and
(W or X)
and(F)and(ZorZ).
The product of sums
is
now
multiplied out, with obvious simplifications,
to given an equivalent expression in the
sum of products form
(U
W)(U + V){W +
X){ Y)(X
+ Z) = (/+ VW)(X+ WZ)Y = UXY+ UWYZ+ VWXY+ VWYZ

it
This
sum of products
expression logically states the same thing as the

states that
previous product of sums expression, except in another way:

all
the combinations in the table can be accounted for by the prime impli-
cants
{U and X and Y) or (U and and Y and Z) or (V and and Y) or (V and and Y and Z). In general, the smallest term
W and X
is
selected
to account for the table, since

implicants.
it
represents the fewest required prime

selected because
In the example, the
UXY
term
is
it
is
the smallest,
and the prime implicants
U = 001 = ABD X = 10 = BC
Y= ll=AC
are used to account for the table. If any other term rather than three prime implicants
had been selected, four would have been required.
The
selected
prime implicants are

is
summed
to obtain the
minimum sum
of products, and the solution
ABD + BC + AC
This method of solution of the table not only gives one
products,
it
minimum sum
of
gives all possible
minimums
if
there are
more, it gives all irredundant solutions, that is, all prime implicant may be removed and still have
more than one. Furthersolutions from which no

all
output combinations

82 TABULAR METHOD OF SIMPLIFICATION
Chap. 6
accounted
for.
In the preceding example, there are four irredundant solutions.

that prime implicant
In the example, examination of the table before applying the algebraic
method would show

implicant
algebraic
Y is
required because the comis
bination 1010 has only a single check mark, which
in the
Y row.
and
Prime
also accounts for the combinations 1011, 1110,
1111.
method could be used
to account for the remaining five
The com-
binations in the table, prime implicant

obtained.
being added to the expression
The inspection of a table for columns with single check marks can thus simplify the work involved in solving the table.
In multiplying out the product of sums, use should be
simplification theorems
made of
the
whenever possible. Note that since there are no complemented variables involved, only a few of the simplification theorems need be considered. Also, one can be selective in which factors he chooses to multiply out first; if those with the most literals in common are multiplied together
first,
the process
is
simplified.
Weighting of Prime Implied nts

If there
is
more than one
solution with a
minimum number of prime

literals is
implicants, the solution with the least
number of
usually desired.
As an
aid in obtaining the desired solution, each prime implicant can be
assigned a "weight" according to the
number of
literals it contains,
and
the solution with the smallest weight selected.
In the previous example, the weights would be assigned as follows
Weight
u
V
001 011
3 3
w
X
Y
00 10 11
11
2
2
2 2
z
The terms
in the algebraic solution then
have weights as follows:
UXY + UWYZ+ VWXY+ VWYZ

Weight:
7
larger
9
it is
9
possible that a solution with the
With a
number of variables,
more prime
minimum number of prime

solution containing
implicants
may
contain more
If a
literals
than a
implicants.
solution containing a
minimum number
of
literals is desired, this
method of weighting would
point out which solution to choose.
Chap. 6
SIMPLIFICATION OF FINAL TABLE
83
Simplification of Final Table

If
sufficient to find
it is
mums), the final table can often be columns and rows, as follows.
1.
any minimum solution (rather than all minisimplified by the elimination of certain
that
A column, a, can be eliminated if it has check marks in every row some other column, b, has. (Column b represents a "tighter" requirement than column a; that is, if column b is accounted for, column a will
also.)
be
Example:
(a)
V V
s/
v/ >/
Column a can be
that
eliminated because
it
has check marks in every row
column b
has.
(b)
n/
v/
v/
v/
in every
2.
Either column, a or b, can be eliminated because each has check marks row that the other has.
can be eliminated if some other row, y, has check marks has, and if the number of literals in the z prime implicant is equal to or greater than the number of literals in the y prime implicant. (The y prime implicant is "stronger" than the z prime implicant
z,
row,
in every
column that z
in that it accounts, at least, for all columns that z does, and at the same time does not require more literals than z.)
84
Chap. 6
Example:
(a)
s/ s/
s/
v/
Oil y
101
z
v/
Row z can be eliminated because row y has

that
row z
has,
and the number
of literals in the z
literals in
check marks in every column prime implicant is equal
to or greater than the
number of
the
y prime
implicant.
(b)
v/ n/
Oil y
101
z
v/
in every
y or z, can be eliminated because each has check marks column that the other has, and both prime implicants have the same number of literals.
Either row,
(c)
v/ v/
s/ v/
01
y
z
101
Only row z can be eliminated because even though each row has check marks in every column that the other has, the z prime implicant has a
greater
number of
literals
than the y prime implicant.
(d)
v/ s/ y/ n/ v/
on
01
y
z
Neither row can be eliminated. Even though row y has check marks in
Chap. 6
COMPLEMENTARY APPROACH WITH TABULAR METHOD
85
every column that

is less
row z
has, the
number of literals
the
than the number of
literals in
in the z prime implicant prime implicant. y
Complementary Approach with Tabular Method

In the complementary approach, a table
tions for
is
made up of
those combina-
which no output
is
desired.
Any
is
optional combinations are added
to the table as before.

resultant
The
table
is
solved in the usual manner, and the
minimum sum of
products
theorem. Thus the final solution appears in a form.

solution with fewer prime implicants or fewer
to try both solutions, selecting the
is
complemented using DeMorgan's minimum product of sums
Since either the direct or the complementary approach

literals, it is
may
lead to a
often desirable
optimum one. If the number of "output" compared to the number of "no-output" combinations, the complementary approach may be used simply to reduce the labor involved in reaching a "good" solution. If there are no optional combinations, the minimum product of sums obtained using the complementary approach is a true equivalent of the
combinations
large
minimum sum of
if
products obtained with the direct approach. However,
there are optional combinations involved, the
two expressions may not
be truly equivalent.
The two expressions will always be equivalent in the sense that if any "output" combination equals -1, both expressions will equal 1, and if any "no-output" combination equals 1, both expressions will equal 0. However,
an optional combination equals 1, the two expressions may or may not be equivalent. If, with optional combinations, it so happens that the prime implicants used in the direct approach solution and the prime implicants used in the complementary approach solution together account for all of the optional
if
combinations, and there is no optional combination accounted for in both approaches, the minimum sum of products obtained in the direct approach
will
and the minimum product of sums obtained in the complementary approach be equivalent. If any optional combination is not accounted for in
accounted for in both approaches, the two resulting The expressions obtained with the two therefore not be logically equivalent; however, lack of occur only for optional combinations.
is
it is
either approach, or
expressions will not be equivalent.
approaches
equivalence
may may
The complementary approach

previously solved. Again,
this
will now be applied to the problem suggested that, for practice, the reader solve
problem on
his
own
first.
86
Chap. 6
D
oy
D
<V <v
0*
D
0*
1 1 1
0^ ov
Oy/
oy
10
oy
oy 10 0*
v W
Oil*
1000
>/
0010
0110
0111
1001
000
v/
>/ >/ s/
v/
100
* * *
on
may be solved intuitively, and it is found that the are required. The resultant sum of products implicants prime three
This simple table
last
ABC + ABC + AD
complemented using DeMorgan's theorem, gives the minimum product of sums solution
(i
+B+
C)(A
+B+
C){A
D)
less
In this example it is seen that the complementary approach involved work because of the fewer combinations involved. However, the minimum product of sums solution contains more literals than the minimum
sum of products
The two
solution.
expressions in this example are not logically equivalent since the optional combination 0100 was accounted for in both approaches by in the in the direct approach, and by the prime implicant equals complementary approach. When this optional combination
10
0 0
ABCD
1,
the
minimum sum
0.
of sums equals
are equivalent.
of products equals 1, and the minimum product For all other possible combinations, the two solutions
The
tabular
is
expression
in
method of simplification can also be used when the original an expanded product of sums form. The procedure is the
selected
same throughout, the

product of sums.
prime implicants representing a minimum
Chap. 6
ITERATIVE
METHOD FOR OBTAINING
PRIME IMPLICANTS
87
Iterative
Method
for Obtaining Prime Implicants
In the method described in this chapter, the expanded sum of products form was obtained in order to obtain the prime implicants. If the original
to be minimized is not expanded, it may be desirable to obtain the prime implicants directly, without having to expand first. An iterative method for obtaining the prime implicants from any sum of products
will
sum of products
now be
described.
13 in reverse,
The method makes use of Theorem

13.
3.
and Theorems
and
1 1
XY + XZ = XY + XZ + YZ X+X = X
11.
X+XY=X
stated very simply.
The method can be

systematically to
all
Theorem
13 in reverse
is
applied
pairs of terms to obtain all possible included terms,
which are added to the expression. The pairing continues as the included terms are added. At the same time, terms are eliminated as Theorems 3 and 1 1 are applied whenever possible. An included term that can be immediately eliminated by the use of Theorems 3 or 1 1 is not added. The process
is
exhaustively continued until no more included terms can be formed, or until the only included terms that can be formed would be immediately eliminated by the use of Theorems 3 or 11. The existing terms at this point
all
comprise
of the prime implicants.
Example:
Find
all
of the prime implicants from the expression
ACD + ABD + ABCD + ABCD + ABCD

terms
first term, ACD, paired with the other terms, adds the included BCD, BCD, and ABD; BCD eliminates ABCD, and ABD eliminates ABCD. We now have
The_
The
BD
ACD + ABD + ABCD + BCD + BCD + ABD second term, ABD, with the other terms, adds ACD
ABD, BCD, and ABD. The
and BD;
is
eliminates
expression at this point
ACD + ABCD + BCD + ACD + BD

minates
term, ABCD, with the other terms, adds ABC, which eliABCD. Next, BCD, with the other terms, adds CD, which eliminates ACD, BCD, and ACD. The expression is now
The next
BD + ABC + CD
which comprises all of the prime implicants, since there are no more included terms that cannot be immediately eliminated. This process can, of course, also be carried out in tabular form.
88
Chap. 6
Multi-Output Networks
Multiple-output networks
or contacts in
AB
may sometimes be able to share logic blocks common. For example, if the expression for output- 1 is + CD, and the expression for output-2 is CD + CD, the CD term can be shared by both circuits, as shown in Fig. 6-1. A AND The determination of terms that can be shared is
OR
not always so obvious.

sions
1
:
For example, the expresliterals)
c D AND
OR --2
ABD + ACD and 2: ABC + ACD + BCD

and 15
have no term in
expression for
equivalent
(a total of 5 terms
common; however, an
output-2
is
which has the term ACD in common with the output- 1 expression (a total now of 4 terms and 12 literals). Furthermore, a possible common term may not be a prime implicant! Thus, even an examination of all possible equivalent minimum, or, for that matter, irredundant sums of products may not show up possible terms that can be shared to give an optimum multi-output network. As an example,
Figure 6-1
ACD + BCD + ABC,
the expressions
12 literals) have
term
AB + BC + ABC in common
AB + BC + AC and 2: AC + BD + BC (6 terms, no terms in common, but the equivalent expressions 1: ABC and 2: AC + BD + ABC have the non-prime implicant
1
:
(5 terms, 11 literals).
In this section, the tabular method will be extended to multi-output networks. Multiple-output prime implicants are obtained from which is selected
a set of sums of products or products of sums that is minimum in an overall sense. The method will be illustrated by an example.
both input and output columns. All input one output on are listed; the outputs that are on for each of these input combinations are recorded by a check mark in the appropriate output column. The rows are ordered in the
The multi-output
tables have
is
combinations for which there
at least
usual manner.
A B C D
1
1
3
v/
A B C D
1
1
3
s/ v/
V
v/
V
s/
1 1
1
v/
1
1 1
1
J
>/
s/ >/
1
1 1 1 1 1
1
n/
v/
V
s/ s/
1
1
1
V
1 1 1 1 1 1
s/
1
1 1 1
1
V V
s/ >/ v/ v/
V
v/
1 1 1
v/
v/ n/
V
v/
s/
1 1 1
v/
Chap. 6
MULTI-OUTPUT NETWORKS
89
The combining of
(a)
the rows
at least
is
necessarily modified as follows:
Only rows with

checked.
one on output in
common
(b) In the resulting row, only the on outputs that
can be combined. were common are

it is
(c)
combining row
is
"checked off" (signifying that
not a prime
implicant) only if the resulting
row accounts
for all of its on outputs.
For some
specific examples, note in the table that
rows 0001 and 0101
A B C D
1
2
s/
3
s/
10
s/
cannot be combined because there are no on outputs in common.
A B C D
1
3
s/ s/
A B C D
V
v/
001
10
Rows 0001 and

the
1001, with oh output-3 in
common, can combine
to give
which only output-3 is checked. Neither of the combining rows can be checked off, since the resulting row doesn't account for all
in
row 001,
of the on outputs in either case. Rows 1000 and 1001, with on output- 1 and on output-3
A B C D
3
s/
v/ s/
A B C D
10 10
in
v/
1
10
row 100
s/
s/
common, combine
to give the
in
which both output- 1 and

off,
output-3 are checked. Both combining rows are checked

resulting
since the
row accounts for all of the on outputs in both cases. Rows 0101 and 0111, with on output- 1 in common, combine
1
to give
A B C D
3
s/
A B C D
1
10
the
for
n/ v/ v/
111
row 01
v/
1, in which output-1 is checked. The resulting row accounts of the on outputs in row 0101, but not for all of those in row 0111 therefore, only row 0101 can be checked off. The complete tabulation follows.
all
90
Chap. 6
A B C D
1 1
A B C D
*
>/ y/
3
n/
y
s/
s/
V
s/
*
y/ s/
1 1 1
10 10
s/
y/
V
s/
s/
1
y/
1
1
>/
* *
y/
1 1 1
v/
s/
s/
V
y/
1 1 1 1
1 1
1 1
v/
s/
s/
V V
v/
Oil
1 1
V
y/
y/ y/
*
y/
* *
s/
V
n/
10 01 10
1
*
y/ y/
y/
V
* *
v/
y/
Ill 11
A B C D
10
y/
y/
struct
The multi-output prime implicants having been obtained, we now conthe final table. A column is required for each input-output
combination.
Chap. 6
91
*
J
> > > > > > > > >

1C 1-H 11 1-H
>
">
^
">
1
I
o
I
I 1
1-H
J,
<
1
o o
<
>
>
">
8
r>
>
^
^
8
I o
">
>
>
">
1
T
>
^ >
9
"H
>
>
">
> > > ^ >
o o
- 8
1
>
">
>
^
^>
1
O
y
">
">
>
^>
92
Chap. 6
For each prime implicant, check marks are placed only in columns corresponding to that prime implicant's on outputs. Thus, for example, for prime implicant 001, only output-3 is pertinent; therefore, check marks
are placed only in the output-3 0001
and 1001 columns. Check marks are

a whole
(i.e.,
not placed in the output-1 1001 or output-2 0001 columns.
The completed
output)
is
table, treated as
not broken
down by
are
solved in the normal manner.

asterisk.
The required prime implicants
marked with an
One
last step
all
must now be made.

its
A selected prime implicant may not be
required by
on outputs. Therefore, a check must be made for each output, to determine if any of its corresponding prime implicants is redundant as far as that particular output is concerned. One case of such redundancy exists in the present example, and relates to output-3. The relevant portion of the table is extracted for instructional purposes. Note that only
of
3 0001
0110
0111
1000
1001
1010
1011
2
v/
3
*
s/
0001
V V
v/
0111
*
v/
v/
n/
Ohv/
io
*
s/
the selected prime implicants pertinent to output-3 are considered. Examination of the table shows that, with regard to output-3, prime
implicant 0111
involved;
is
redundant.
last step
Note that this

it
does not affect the total number of terms or
literals
may, however, reduce the number of or logic block inputs or, in the event that an expression is reduced to a single term, eliminate an
or
logic block.
The optimum
(1) (2) (3)
set
of expressions for the multi-output network
is
ABCD + BCD + AB ABCD + ABCD + ACD ABCD + ABC + AB

resulting
If there are
The
network is shown in Fig. 6-2. any optional input combinations, they are added to the original table in the usual manner; for these combinations, it should be assumed that all outputs are on. Also, for a valid input combination, some
outputs
may be
optional;
it
should be assumed that these outputs are on
Chap. 6
93
AB-
AND
B-
CD-
AND
OR
ABCDA-
AND
C0AB?DA-
AND
OR
AND
BC-
AND
OR
Figure 6-2
also. These optional input-output combinations are used only for obtaining the prime implicants. In the final table, there are columns for only the valid input-output combinations.
Example:
The input combination 0010 can never occur; for the combination we don't care what any of the outputs are; for the combination 1100, output- 1 must be on, output-2 must be off, and output-3 can never occur; for the combination 1110, output-1 and output-3 must be off, and we don't care what output-2 is.
0100,
These combinations are added to the original
table, as follows.
A B C D
v/ y/ v/
v/ v/
1
1 1 1 1 1
V V
s/
94
Chap. 6
In the
final table, the
which there
is
will
only one of these input-output combinations for be a column (the only one that must be accounted for)
output- 1 1100.
PROBLEMS
1.
The following
the
table represents the
expanded sum of products. Obtain
minimum sum of
products, using the tabular method.
A B C D
1
10
11
1110
111
10 10
2.
110 110
10
In the preceding problem, use the complementary approach and com-
pare
3.
results.
The following
table represents the

is
combination prime implicants, and express algebraically.

optional.
ABCD
expanded sum of products. The Using the tabular method, find all
ABCD
10
11
10 10
111
1
10 10 11
110
1110
10 10
Chap. 6
PROBLEMS
95
4.
Given the output combinations and prime implicants below, and using
the algebraic
(a) the
method of solution, determine:
(b) the
(c)
number of irredundant solutions minimum-term sum of products
the minimum-literal
sum of products
A B C D E
10
10
10
11
00
U
V
001
000
W
1
_1
x
Z
1 Y
10
*5.
The
circuit
shown
in Fig. 6-3
the three input combinations

these optional combinations.
was designed without the knowledge that ABCD, ABCD, and ABCD were invalid.
circuit,
Using the tabular method, redesign the
taking advantage of
A-
0c_-
AND
DA-
BD-
AND
B-
CDj-
AND
OR
B0ABC-
AND
AND
Figure 6-3
6.
Design an optimum multi-output network for the requirements in the

following table.
96
Chap. 6
A B c D
1 1
1 1 1 1 1
V
y/
V
s/ s/
y/
y/
V
v/
1
1
y/
1
1 1 1 1
V V
v/
v/
v/ s/ s/
y/
1 1
Map Method
of Simplification
basically the
The underlying principles of the map method of simplification are same as those for the tabular method. Maps are easy to use
is automatically expanded as it is entered on the map, and the prime implicants can be identified by the visual recognition of certain basic patterns. However, some practice is
because the expression to be simplified
required before the user can feel confident in the use of maps, particularly when the number of variables becomes large.
A
map
map
for n variables contains 2 n squares, there being a square
on the
placed
for every possible input combination.
is is
placed in each square

desired; a
is
representing a combination for which an output

in each square representing a combination for
which no output is desired; and a is placed in each square representing an optional combination. Often, to reduce the writing, the O's are omitted, and a blank square is
understood to represent a no-output combination. Figure 7-1 shows two forms of a two-variable map. Although twovariable maps are seldom if ever actually used for simplification, an analysis
97
98
MAP METHOD OF SIMPLIFICATION

A
1
Chap. 7
AB
00
01
II
10
the twoboth forms will aid in an understanding of the fundamental principles involved.
variable
of
some examples using
map
in
In entering a
Figure 7-1
map with an expanded
term, a
1 is
placed in the square of the
map
term.
corresponding to that expanded

not expanded, a
1 is
The
entry for
AB
is
shown
in Fig. 7-2.
is
In entering the
Fig. 7-3.
map
with a term that
placed in
all
squares defined by that term.
The
entries for the
term
are
shown
in
AB
00
01
1 1
A
10
1
AB
00
01
1
1
10
Figure 7-2
Figure 7-3
Note that if B had first been expanded into AB + AB, the same two would have been made. Thus, B was automatically expanded as it was entered on the map. In "reading" a map, two 1 -squares that are adjacent either horizontally or vertically can be grouped. Larger numbers of 1 -squares can also be grouped, the number of squares in a group always being some power of 2; however, for the time being, only groups of two will be considered. The
entries
variables that are constant for the
group of
1 -squares
define the group.
map in Fig. 7-3 is read as B. The map in Fig. 7-3 might have been entered with AB + AB. With the map entered, it is observed that two 1 -squares are adjacent. This group of two 1 -squares is defined by B. Therefore, the term B is rcad from the map,
Thus, the
accomplishing the simplification. The four possible groups of two
1 -squares
in a two-variable
map
are
shown in Fig. 7-4. Note the "reflected" binary ordering of the variables in the right-hand map in each case. With this ordering, any two adjacent squares will differ in only one variable. Thus, all possible groups can be formed by two adjacent 1 -squares. The fourth case, that for B, warrants special attention. Note that the left-hand square 00 differs from the right-hand square 10 in only one variable. These two squares are considered adjacent in the same sense that the others are adjacent. The adjacency of the two end squares
1
êe Chapters
11
and
12.
Chap. 7
MAP METHOD OF
SIMPLIFICATION
99
AB
00
01
11
AB
10
00
01
11
10
<Z3> <CID
A
<CJ>
AB
AB
00
01
10
00
01
11
10
<3>
Figure 7-4
<Zj>
\j>
<C
may be better appreciated if the map is pictured as rolled into a cylinder, with the right-hand edge touching the left-hand edge. While in a two-variable map it is not necessary to get involved in this edge-to-edge wrap-around the square array could have been used instead this concept has been purposely
introduced with the simple twovariable
map
because
it is
used in
AB
00
01
AB
10
11
00
01
1
10
maps of more
If,
H
1
variables.
instead of the reflected binary
ordering, a straight binary ordering 2
had been used, the four previous maps would have looked like Fig. 7-5. Note that the nice relationship
of groups always
jacent squares
this
AB
00
1
AB
01
1
10
11
00
1
01
10
1
occupying adreflected
no longer holds. For

the
reason,
is
binary
1 -square
Figure 7-5
ordering
usually used.
In reading a map, every
must be accounted for
at least once,
although a
-square
may be used
in as
many groups
as desired. Also, a
group should be as large as possible, that is, a 1 -square should not be itself if it can be accounted for in a group of two 1 -squares; a group of two 1 -squares should not be made if the 1 -squares can be included in a group of four; etc. These "largest" groups correspond to prime implicants. All 1 -squares should be accounted for in the minimum number of groups, and the resulting expression read from the map will be a minimum sum of products.
accounted for by
2
See Chapters 11 and 12.
Example:
ab
oo
ot
11
10
<jZSO>
AB+AB+AB-A+B
Figure 7-6
In this example, there are two groups of two 1 -squares each, one group denned by A and the other group by B (Fig. 7-6). Note that the combination AB was used in both groups.
Examples
AB
00
01
11
io
AB
00
c
01
AB+AB
Figure 7-7
10
Figure 7-8
In the example of Fig. 7-7 there

1 -squares
is
no
simplification possible; the
two
is
are not adjacent horizontally or vertically, and

expression.
AB + AB
minimum
two
1
Fig. 7-8. Figure 7-9
The construction of a three-variable map is shown in shows, for study, some familiar examples of groups of AB
-squares
on
11
three- variable maps.
AB
00
01
AB
01
II
10
00
10
00
01
11
10
<Z3>
AB
AB
00
01
11
AB
AB
10
AC
AB
01
ii
00
10
r 00
01
11
10
<z J>
00
01
11
j> W
BC+AB
AB
00
01
<L 32 3>
1
BC+AC
AB
H
10
10
00
01
11
10
'J>
<r:
<C3I
AC+BC
Figure 7-9
AB+BC
100
Chap. 7
MAP METHOD OF SIMPLIFICATION
101
Groups of four
1 -squares
may
occur either in a straight line array or
in a square array, as
shown
in Fig. 7-10.
Note again the concept of the

7-10.
10
edge-to-edge wrap-around in the
example of Fig.
AB
00
01
11
AB
10
00
01
11
_!
f j) K^
B
01
11
AB
00
01
11
AB
10
00
10
(C
B
Figure 7-10
~J)
Some
additional examples are given in Fig. 7-11 to 7-14.
Examples:
ABC+ABC+ABC+A&C AB
00
01
II
ABC+AC+BC4-A&C AB
00
/T\
'i^
01
11
10
10
M H5
<c.
VJ.
^!''
y
or
C\
-AB+AC+BC
Figure 7-11
-AB+AB+AC
AB+AB+BC
Figure 7-12
ABC+AC+BC+AB AB H 10 00 01
/
BC+AB+BC+AC AB
00
01
II
10
1\
0/1
1\
C+AB+AB
Figure 7-13
B+C
Figure 7-14
In Fig. 7-12, there are two equally good solutions; the
ABC
square
can be accounted for by either AC or BC. Note, in all of these examples, that all
for at least once,
and that
all
have been accounted groups are as large as possible.

1 -squares
102
MAP METHOD OF
SIMPLIFICATION
Chap. 7
Complementary Approach with Map Method

As in the tabular method, it is possible with maps to use the complementary approach. In the preceding four examples, 0's have purposely been entered on the maps in preparation for the discussion of the complementary
approach.
In the complementary approach, the 0-squares, rather than the
are grouped. Since the resultant
1 -squares,
sum of products is the complement of the desired expression, this sum of products is complemented using DeMorgan's theorem. The final expression is thus in a minimum product
of sums form.
The complementary approach

in Fig. 7-15.
to the preceding four examples
is
shown
AB
00
01
i
AB
11
10
1
00
1
01
11
10
/0\
(*)
1
o~~"W~d
AB+BC+AC (A+B){B+C)(A+C)
--
y
10
ABC+AB= (A+B+C)(A+B)
AB
00
01
11
AB
10
00
01
i
11
1
ABC +ABC
--
<
Figure 7-15
:>
i
<'.
i
(A+B+C)(A+B+C)
BC--B+C
Comparison of the equivalent results of both approaches shows that in Example 1, the two solutions are equally optimum; in Example 2, there are fewer literals with the complementary approach; in Example 3, there are fewer literals with the direct approach; and in Example 4, the solutions
are identical.
In the complementary approach, the minimum product of sums can be read directly from the map by the mental application of DeMorgan's theorem during the process of reading. For example, in Example 2, instead of the 010 entry being read as the product ABC, and later complemented, B C) by the mental compleit can be read directly as the sum (A
mentation of the variables as the map is read. Maps are convenient for converting an expression from the sum of products form to the product of sums, or vice versa. For instance, a product
Chap. 7
"METHOD OF ATTACK"
103
of sums can be entered on a map, with
l's,
and a sum of products read
from the map by grouping the
0's.
"Method of Attack"
A good general approach in reading the optimum solution from a map is

to account
first
for
all 1 -squares
that can be grouped in only one best way,
is involved. Look first for any do not combine with any others; these entries must be accounted for by themselves. Next, look for any 1 -squares that combine with only one other 1 -square; such groups of two should be accounted for next. If a 1 -square combines with exactly two other squares, look to see if
leaving until last those in which a choice

1 -squares
that
is a fourth 1 -square that completes a group of four. If there is, the four entries should be accounted for as a group; if not, then there is a choice involved as to which of the two groups of two to choose, and such decisions
there
should be left until last. And so forth. Remaining 1 -squares should be combined into the fewest possible groups. The following simple example illustrates the approach suggested. This example is of interest also because it illustrates the included term theorem.
Example:
In this example (Fig. 7-16), there
entry
is
only one best
way to account for the
the
ABC: with the group AB; and there is only one best way to account for entry ABC: with the group BC. These two groups account for all entries,
and therefore the solution is AB + BC. Note that the entries ABC and ABC each can combine in two ways, and therefore consideration of these entries
is
deferred.
AB
AB+BC+AC AB
00
01
II
00
01
11
10
CD 00
fO
C3>
--AB+BC
Figure 7-16
01
1
10
Figure 7-17
four- variable
in both the horizontal
only are the
left
are also adjacent.
is shown in Fig. 7-17. Note the reflected ordering and vertical directions. In four-variable maps, not and right edges adjacent, but the top and bottom edges A mental picture of this left-right top-bottom wrap-around
map
104
MAP METHOD OF
SIMPLIFICATION
Chap. 7
one considers the map as rolled into a cylinder with the left and then the cylinder rolled into a torus with the top and bottom edges touching. Figure 7-18 shows a few examples of groups involving these wrapcan be formed
if
and
right edges touching,
around adjacencies. Figure 7-19 shows two examples of groups of eight
1 -squares.
AB
00
01
11
AB
10
AB
01
II
00
10
00
01
II
10
CD 00
01
1
CD 00
CD
00
01
1
I
J>
<c.
01
1
10
Group of two
10
Group of four
10
Group of four
BCD
AD
Figure 7-18
BD
AB
CD 00
01
1
1
AB
01
11
00
10
LU 00
01
1
00
01
1
11
10
j)
10
10
^
AB
00
^
01
11
Figure 7-19
Groups should always be

that
is,
as large as possible,
10
every group should correspond to a prime CD
00 implicant. However, a group should not be made just because it is large. The following example o
i
XD <Zj>
illustrates this
important point.
i
Example:
In Fig. 7-20, the
tive
10
group
AC looks
very attrac-
a
Figure
because
it is
the only group of four
on the
ABD+BCD+BCD+ABD
7-20
map. However,
all
of the entries in this group can
Chap. 7
"
METHOD OF ATTACK
"
105
combine
in
that cannot
more than one way and it is best to consider first those entries combine in more than one way. Study of the map reveals that
1 -squares
combines with only one other 1 -square. it is found that every 1 -square on the map has been accounted for; thus, the term AC is redundant. Figure 7-21 is given for study in both entering and reading a map. The groups are numbered to correspond to the terms from which the map was entered. The map is repeated in Fig. 7-22 showing the groups that are read. These groups are numbered to correspond to the terms in the final
each of the other four
When
these four groups of
two have been made,
expression.
Another comparison of the
straight binary ordering

is
binary ordering, this time in four-variable maps,
and the reflected shown in Fig. 7-23.
ABCD +BCD +ACD +ABC+BCD

1
AB
00
01
II
10
CD 00
z
01
1
I
10
ABC+ABD+BC
1
Figure 7-21
Figure 7-22
AB
CD
00
01
10
1 1
1
AB
01
00
10
II
CD
00
01
1
00
01
11
10
10
BD
Veitch chart Straight binary ordering
BD
Karnaugh map
Reflected binary ordering
Figure 7-23
The
is
first
application of this type of graphical approach to simplification
The Veitch chart used the straight binary ordering shown on the left. M. Karnaugh modified the Veitch chart, using the reflected binary ordering shown on the right. The resulting improvement is that, in the Karnaugh map, all groups are adjacent rather than some
accredited to E.
Veitch.
W.
106
MAP METHOD OF
SIMPLIFICATION
Chap. 7
of them being scattered as in the Veitch

chart.
An
alternative
is
Karnaugh map
method of labeling the shown in Fig. 7-24.
Optional Combinations with
Map Method
map by
in
Optional combinations are entered on a placing 's in the corresponding
B
Figure 7-24
squares. These optional entries
may be used
for.
obtaining
fewer and/or larger groups.
Only the
entries
1 -squares
must be accounted
In Fig. 7-25, optional combinations are used to advantage. The optional
ABCD
and
ABCD
and
are used with the
to give the group
AC;
the optional entries
-squares ABCD and ABCD ABCD and ABCD are used with
1
the 1-squares
ABCD
ABCD
to give the
group AC. The optional entry
ABCD
is not used. Optional combinations can be used in both the direct and complementary
approach, as shown in Fig. 7-26. Note that the direct approach results in
eight literals while the
complementary approach
results in seven literals.
Note
also that the two resultant expressions are not true equivalents because
the optional combination was used in a group in both approaches.
AB
CD
00
01
1
1
AB
01
11
AB
01
I
00
10
CD
00
00
/l
11
10
!
00
01
10
f J t^
l\
01 X?\
-)
10
f ^ ^ J
AC+AC
Figure 7-25
W
ft
AC+ABD+ABD
Figure
10
(B+D){A+B)(A+C+D)
7-26
Maps
of
More than Four Variables
When
There are several ways of drawing maps of more than four variables. three or more variables are involved in one dimension, adjacencies are no longer preserved and new patterns must be recognized, as shown
in the five-variable
map
of Fig. 7-27. In addition to the adjacencies already
Chap. 7
MAPS OF MORE THAN FOUR VARIABLES
107
ABC
DE
00
01
1 1
000 001 OH 010
110
111
101
100
AB
CD
00
01
00
01
11
1
10
1
10
BCDE+BCDE
Figure
10
7-27
vertical center line are considered
discussed, squares equidistant

adjacent.
from the
more general approach, that can be extended to any number of is shown in the five- variable map of Fig. 7-28. This five- variable map is made up of two four-variable maps drawn side by side. Groups are
variables,
formed as before except that,

picture this adjacency
in addition to the adjacencies already discussed,
corresponding squares on the two maps are considered adjacent.
One may
by considering the right-hand map as being situated directly behind the left-hand map, making a three-dimensional map four squares across by four squares down by two squares deep.
AB
00
CD.
01
11
AB
10
CD
00
01
1
00
01
II
10
oo]j>
01
1
<c
^.
10
^
also be
10
^
in a
entries
ABCD+ACD+BCDE
Figure 7-28
In the preceding example, the

adjacent to the
ABCD. The
The
ABCDE entry on the left-hand map is ABCDE entry on the right-hand map, giving the group AC 5 group is also made up of -squares from both maps.
1
BCDE group is
six-variable
A
maps
made up of 1 -squares from the E map only. map is made up of four four-variable maps drawn made from corresponding
square array. In addition to the groups that can be formed on any one
four-variable
map, groups can
on
horizontally or vertically adjacent.
108
MAP METHOD OF
In the
SIMPLIFICATION
Chap. 7
map of Fig. 7-29, the group ABCDE comes from corresponding on the two left-hand maps; the group ABCDF comes from corresponding entries on the two upper maps; the term ABCD comes from corresponding entries on all four maps. A seven-variable map is made by placing two six-variable maps side by side. In addition to the groups that can be made on each six-variable map, groups can also be formed from corresponding entries on the two maps. An eight-variable map is made by placing four six-variable maps in a square array; a nine-variable map is made by placing two eight- variable maps side by side; a ten- variable map is made by placing four eight- variable maps in a square array and so on.
entries
;
AB
01
00
01
II
10
%
i
10
AB
CD
00
01
1 1
CD 00
01
00
01
11
10
H
10
10
ABCDf+ABCDF+ABCD
Figure 7-29
EF
00
AB
C p 00
01
11
AB
10
01 01
11
AB
10
11
AB
11
10
01
11
cp 00
cp 00
01
10
cp 00
10
ABCDE+ABCDF+ABCD
Figure
7-30
Chap. 7
FACTORING
ON
THE MAP
109
Sometimes a six-variable map is drawn as in Fig. 7-30. The four fourmaps can be pictured as being placed one behind the other, the left-hand map on top and the right-hand map on the bottom, forming a cube four squares across by four squares down by four squares deep. In this cube, the left-hand and right-hand faces are considered adjacent, the front and back faces are considered adjacent, and the top and bottom
variable
faces are considered adjacent.
Summary
Following is a summary of some pertinent points regarding the map method of simplification. There is a square on the map for every possible combination of variables. A 1 is placed in each square representing a combination for which an
output
for
is
desired; a
is
is
placed in each square representing a combination
which no output
desired; a
is
placed in each square representing
an optional combination. Each 1 -square must be considered

considered as often as desired.
Generally,
all 1 -squares
at least once.
Each
-square
may be
should be accounted for in the

as large as possible, that
minimum number
of groups.
Each group should be
is,
each group should
correspond to a prime implicant.
The number of squares

In a group of 2 m squares,
in a
group must always be some power of two.
m variables will occur in all possible combinations. If the total number of variables is n, then (n m) variables will be constant in these 2 m squares, and these (n m) variables will define the group.
the
made in an optimum manner, the expression read from be a minimum sum of products. The complementary approach may be used, in which case the 0-squares rather than the 1 -squares are grouped. The groups are complemented and a minimum product of sums is obtained. Optional combinations may be used to obtain fewer and/or larger groups. The map method, like the tabular method, can also be directly adapted to the simplification of expressions in the product of sums form, each 1 -square representing an expanded sum, and the selected groups representing
If the groups are
map
will
minimum product of sums.
Factoring on the
Map
map
factoring. Factoring can also be
The only
directly
algebraic simplification possible to perform

is
expressions read from the
on the minimum done

is
on the map,
as illustrated in Fig. 7-31.
Note
that there
"almost"
110
MAP METHOD OF
SIMPLIFICATION
Chap. 7
AB
CD
00
01
1 1
00
01
11
10
f\
>\
is one 1 -square missing from this group of four, the ABCD square. This group can thus be described as "AC but not ABCD"
a group y4C; there

potential
S
1
v_
1
J
1\
which can be written algebraically as
AC -ABCD
in terms of
= AC(B
square."
-+-
D).
the
as
The missing square can be considered

the remaining variables only,
that
is
10 \a
The group can thus be described
"BD "AC
Figure 7-31
but not
BD" which is written algebraically as
AC'BD=AC(B +
In this map, there
thus the group
is
D)
also "almost" a
missing from this group, these squares being described as
group C; there are two squares AD. There is
"C but
not
AD" which written algebraically is C'AB = C(A + D)
The
final factored expression is
AC(B
+ D) +
C{A
D)
PROBLEMS
Minimize the following expressions using the
1.
map
method.
*2.
ABC + AD + D(B + C) + AC + AD ACD + BD + BC + BD + CD

Optional combinations:
ABCD, ABCD, ABCD
3.
4.
BC + AB + 5CZ) + ABD + ^5CD BCD + A6Z) + ^CD + ABC + iCD Optional combinations: ABCD, ABCD, ABCD
C(BD
Read
*5.
6.
+ BD) +
the
iC(5
D)
CZ>(^
+ 5) + ^Z)(5 +
1
C)
+ ^
map
in Fig. 7-32.
AB
00
01
AB
H
10
00
01
1
4
4
CD
1
00
01
10
1
00
01
1 1
10
Figure 7-32
10
Chap. 7
PROBLEMS
111
7.
8.
Read
the
map
in Fig. 7-32, using the
complementary approach.
products:
Using the
map method,
obtain the
minimum sum of
ABCDEF + ABCDEF + ABD + BCDEF + BCDEF + ABCDE + ABCDF + ACDEF + ACDEF Optional combinations: ABCDEF, ABCDEF
*9.
Using the
map method,
obtain the
minimum sum of
products
ABCDEF + ABDEF + ABCDF + ACDEF + ABDEF + ABCDEF + ABCDE + ACDEF + BCD Optional combinations: ABCDEF, ABCDEF
Trees
Relay
and
Electronic
tree is a multi-output circuit in

it.
a unique output associated with

relay trees
Two
which each input combination has types of trees will be discussed:
and
electronic trees.
Relay Trees
A relay tree,
or transfer
tree, is
a particular type of multi-terminal relay
contact network having a single input which
may be
connected to any one
connected to the input at any given time, the selection being controlled by the combination of relays operated. Each input-to-output path passes through one contact on each
of a number of outputs. 1 Only one output
is
relay,
and
all
outputs are disjunctive, that
is,
no output can ever be con-
nected to another output through the

^rees are
circuit.
also sometimes used in reverse, that
is,
one of a number of inputs
is
con-
nected to a single output.
112
Chap. 8
RELAY TREES
113
The number of
in
possible relay combinations with n relays
is
2 n ; therefore,
an
w-relay tree there are 2n possible outputs.
full tree
has an output
terminal for each of the 2n possible relay combinations, and the total
number of
transfers 2 in the tree is 2n partial tree has less than 2" 1. output terminals, and the total number of transfers in the tree may vary.
A full transfer tree is shown in Fig. 8-1.

the tree in Fig. 8-1
is
The
transfer contact distribution
on
A B C D
1
8
-C
15
00i
i 1 C i I C 10 D
I
d00'
4
5
6 7
C-
T
I I
i
8 9
*An D
1
B-
C r-0 10 H n C
10
C
10
12 13
14
15
i0Figure 8-1
16
may be somewhat must always have a single transfer contact; however, the contact loads on the other relays may be made more uniform. In the above tree, there is a total of fourteen transfer contacts on relays B, C, and D. The most even contact division
the rearrangement of a
full tree,
By
the contact load
equalized.
The
relay connected to the input of the tree
among
these three relays
is
a 4
5
14
5 distribution.
A circuit with the transfer contact distribution A B C D

5
is
shown
in Fig. 8-2.
The outputs
are
numbered to correspond with those
in the previous tree.
Regardless of the contact distribution, the total

2
number of
transfers in
In this chapter "transfers" denote "positions.

114
TREES RELAY
AND
ELECTRONIC
Chap. 8
full tree is
always 2"
1.
Rearrangement of a
partial tree,
however,
can lead to a reduction in the total number of transfers required.
*A-
i D C u Tt> L-o C i D I D BC -~~ B C I C 15 u: 14

I
2 3
'
13
D-
10 12
c-
16
Figure 8-2
Minimization of Partial Trees
method of minimizing partial trees, that is, obtaining a required tree minimum number of transfers, will now be examined. All possible arrangements of a tree could, of course, be tried, and the minimal one selected, but this process would be too long and laborious. The following table gives some indication of the progressive complexity of a trial and
with the
error approach as n increases.
Number
2
3
of
relays in tree
Number
of possible arrangements of full tree
21
31
.
22
2*
4
5 51
6i
.
41
32
42 44
34
38
28
2 16
52
= = = = =
2
12
576
1,658,880
16, 511, 297, 126,
400
The number of
possible arrangements of
2
an
n-relay tree
2S
is
represented by
I(
2,
1)
][(" - 2) I(" 2
3)
[2H
an n-relay
tree,
If
represents the
number of
possible arrangements of
Chap. 8
MINIMIZATION OF PARTIAL TREES
115
then the number of possible arrangements of an (n

(
+
1
1)
relay tree
is
\)P\
full transfer tree,
In a
minor
tree, representing
such as the one shown in Fig. 2 X combinations contains 2 X
8-3,
a branch, or
transfers.
_ -A
D y-B D
1 1
\-o
C-
L D
-v-DI
n-
y-D
1
C-4
I D
Branch
Branch
Branch
Branch
W
X
Z
represents 8 combinations and contains 7 transfers

transfers
transfer
represents 4 combinations and contains 3 Y represents 2 combinations and contains

I
represents
combination and contains

Figure 8-3
transfers
A particular partial tree can be obtained by starting with a full tree and removing the branches representing the groups of unused otpuut combinations. The removal of a branch representing a group of 2 X unused combinations results in the elimination of 2 X
tree in Fig. 8-3, if the four
transfers.
For
instance, in the
combinations
ABCD, ABCD, ABC 5, and ABCD
were unused, the branch labeled (X), representing the group of these four combinations, could be removed, eliminating three transfers.
It
equals the
into
number of transfers eliminated from a full tree number of unused combinations minus the number of groups which these combinations are combined. The method of minimizing
follows that the total
tree, therefore, consists
a partial
and eliminating the maximum number of

into the
of starting with a hypothetical full tree transfers by arranging the order
of the relays in the tree so that the unused combinations can be combined minimum number of groups. The key to the method, then, lies not in the analysis of the used relay combinations, but rather in the analysis of the unused combinations.
116
TREES RELAY
AND
ELECTRONIC
Chap. 8
Maps are used as the means for combining the unused combinations and obtaining the optimum order of the relays in the tree. The following differences between the normal use of maps and their use here should be noted: in this method (1) the unused rather than the used combinations
are of prime consideration, (2) each combination
as desired but
is is
not considered as often
considered only once, and (3) the groups formed must be compatible with fundamental transfer tree configuration. The meaning of
this third point will
The use of
necessarily a
the
be apparent presently. map to obtain any desired partial n-relay

will
tree (not
minimal one)
1
be described
first.
An
^-variable
map
is
drawn, and a
tion, as
is
entered in each square representing an output combina-
shown
in Fig. 8-4.
Output Combinations
AB
ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD

The map
variable
CD
00
01
1
1
00
01
11
10
10
Figure 8-4
is then divided into two ( 1)- variable submaps, the divided becoming an adjunct to one submap, and the complement of the divided variable becoming an adjunct to the other submap. In each submap,
the adjunct to that
submap
is
written in the lower left-hand corner of each
square representing an output combination (Fig. 8-5). (The particular order of subdivision used in this example leads to a minimal tree; the basis for
arriving at this
optimum order
will
be apparent
later,
and the example
should be reviewed from this standpoint.)
AB
00
01
11
10
00
01
1
10
CD
oo
01
CD 00
01
A
1
A
1
AC
1
AC
1
AB
A_
1 1
AC
AC
1
A
1
AB
1 1
10
A
Figure 8-5
10
AB
Figure 8-6
AB

Chap. 8
117
MINIMIZATION OF PARTIAL TREES
Each
(n
1)- variable
submap containing an output combination
is
subdivided into two (

(Fig. 8-6).
2)-variable submaps, the newly-formed adjunct
in each case being written to the right of the previously-written adjunct
divided.
submap containing only unused combinations is not further subAn unused-combination submap containing 2 X squares represents
the elimination of 2 X
transfers.
The subdivision process is continued until each 1 -square becomes a submap; all other submaps will contain only unused combinations (Fig. 8-7).
AB
00
CD 00
01
1
AB
01
1
AB
01
1
10
00
11
1
10
00
01
1
11
\
10
CD
1
CD
1
AC
1
AC
AC
ABD
00
01
1
ACD ACD ABDC

1
00
ACDB ACDB ABDC

1 1
AC
--
-ACD ACD
1
01 -- _ -_
ACDB ACDB
1
1
ABC
1
ABCD
ABCD
1
10
ABD ABC
10
o ABDC ABCD
Figure 8-7
10
ABDC ABCD
The designation of each output combination will be completely written at the bottom of its representative square.
r-B
B .
The
relay tree
can then be drawn with

I
n:
aI
-B
B_
reference to these written designations,
y-S
'
each input-to-output path from left to right corresponding to the equivalent order of the related written combination
(Fig. 8-8).
B-
T~ r
I
D d
Note
that in a partial tree,
Figure 8-8
sometimes only the normally-open
or
only the normally-closed part of a transfer contact is used. The order of subdivision determines the order of the relay contacts in the tree. The writing of the adjuncts in the 1 -squares is the means of recording the order of subdivision so that the transfer tree can be drawn
by reference to the map. The subdivision process insures that the submaps formed will be compatible with transfer tree configuration.
Any order of subdivision will lead to a legitimate tree. However, to obtain a desired tree having the minimum number of transfers, the map must be subdivided so that the number of unused-combination submaps
is
a minimum. The procedure
is
to
the
minimum number of groups
that can be obtained
combine the unused combinations into by the subdivision
118
TREES RELAY AND ELECTRONIC
Chap. 8
process 3 (there
divide the
may be more than one way
of doing
this),
and then sub-
map
to form the desired groups (there
may be more than one
way of doing
this, also).
This was the procedure followed in the example, as a review will illustrate. Analysis of the map shows that the minimum possible number of
groups of unused combinations is three (AC, ABD, and ABC), and that these groups can be obtained by the subdivision process. To form these three groups, the map was subdivided as shown. The tree obtained is,
therefore, a
minimal one.
The method may be modified by continuing the subdivision process only until all unused-combination submaps have been formed, which completes
the branch removal (Fig. 8-9).
From
the
map
at this stage, the tree
can be partially constructed, and
the rest completed arbitrarily.
map
is
shown
in Fig. 8-10.
the tree obtained from this Branch removal has been completed and any
The portion of
variations in the rest of the tree will not affect the
number of
transfers.
AB
AD 00
01
00
1
01
1
11
1
10
AC
1
AC
1
ABD
AC
1
I
AC
1
ABC
1
10
ABD ABC
Figure 8-9 Figure 8-10
Following
is
summary of the
relationships involved:
n
2"
= number of relays in tree. = number of output combinations in full tree.
(2
1) = number of transfers in full tree. m = number of unused output com-
binations.
3 In the facing map, it is possible to combine the unused combinations into three groups (AC, BCD, ASD). However, these three groups cannot be collectively obtained by the subdivision process (they are not compatible with transfer The minimum number of groups of tree configuration).
AB
CD 00
01
1 1
1
00
01
11
10
1
unused combinations that can be obtained by the subdivision

process
is
four.
10
Figure 8-11
Chap. 8
ELECTRONIC TREES
119
(2"
m) = number
p
of used output comof unused combina-
binations.
= number
from
tion submaps.
(m
(2
n
p) = number of transfers eliminated

full tree.
1
1)
(m p) = (2n m) + p = number
tree.
of transfers in partial
Electronic Trees
Fig. 8-12 represents an electronic tree. As in relay each combination of inputs turns on one of the possible outputs. straightforward way of accomplishing this switching is shown in Fig. 8-13. Using the total number of logic block inputs as a measure of circuit cost,
The block diagram of
trees,
the circuit "costs" sixty-four inputs (sixteen four-input and's).
AABBCCDD
AND
*
".
AND
>^ 2
AND
Four-variable electronic tree
Figure 8-12
Figure 8-13
The
circuit,
circuit in Fig. 8-14
accomplishes the same function as the previous but with only forty-eight inputs (twenty-four two-input and's).
This
the
is
the most economical circuit accomplishing the desired switching.
optimum network of this type, regardless of number of variables involved, will now be discussed. The total number of variables is written, and divided as evenly as possible into two numbers (integers). This is diagrammed by writing the number of variables, and from it drawing two lines to the left, each line terminating at one of the numbers into which it has been divided. The resultant numbers are divided the same way, this process being continued until the numbers 2 or 3 are reached. Two lines are drawn from each 2, and three lines from
each
3,
A method for obtaining an
these lines terminating in the variables involved. This process
is
illustrated in Fig. 8-15, with
an example in nine
variables.
120
Chap. 8
A A B B
AND AND
AND
AND
C C D D
AND
AND AND AND AND
AND AND
--1
-*-2
-3 -*-4
-*5
AND AND
AND AND
--6
-*-7
-**8
AND
AND AND AND
AND AND
--9
--10
--13
AND
AND AND
->-l4
-H5
-**I6
Most economical four-voriable electronic tree

Figure 8-14
Chap. 8
ELECTRONIC TREES
121
Such a diagram
is
interpreted
to right as follows: each 2 represents

ables that are switched in
all
by reading from left two of the varipossible (four) combina-
B-^"
c ~^^2^
tions; each 3 represents three of the variables that are
f^- 2 \
H p z
switched in
all
possible (eight) combinations. In this
example, the nine variables are broken
down
into four
^ ' ^5
3
groups of 2,
2, 2,
and 3
variables each.
Two
of the variables {A and
in this example)
(four)
Figure 8 -is
combinations, and two others (C and D) having been switched in all (four) combinations, the resultant outputs of these two circuits are switched together in all (sixteen) combinations. This operation leads to the 4 on the diagram, which represents the fact that at this point four variables {A, B, C, and D)
all
having been switched together in
are switched in
all (sixteen)
combinations.
Two other variables (E and F) are
switched in
all (four)
combinations, and the remaining three variables (G, H,
and /) are switched in all (eight) combinations, and the resultant outputs of two circuits are switched together in all (thirty-two) combinations. The 5 on the diagram represents the fact that five variables (E, F, G, H, and
these
/) are switched in all (thirty-two)
(sixteen) outputs
combinations at this point. Finally, the
of the four variables {A, B, C, and D) and the (thirty-two)
outputs of the five variables (E, F, G, H, and /) are switched together in all (512) combinations, giving the 512 possible outputs with nine variables.
The
directly
total
number of
logic block inputs can be conveniently counted
from the diagram. Each number, X, on the diagram represents the

.
number of variables being switched in all combinations at that point. The number of combinations at that point is therefore 2 X In other words, 2 X is the number of and circuits associated with the number X on the diagram. .The number of lines leading to X represents the number of inputs to each and circuit at that point. Therefore, the total number of logic block inputs associated with each number X equals the number of lines
total
leading to
X times 2X
Only
in the case of 3's
is
2 X multiplied by three; in
all
other cases 2 X
inputs
is is
multiplied by two. In this example, the total
number of logic block
2 2
3
2 2 2
X X X X X X X
22 22 22 23 24 25 29
= 8 = 8 = 8 = 24 = 32 = 64 = 1024
1168
122
TREES RELAY
AND
ELECTRONIC
Chap. 8
The number of
approach
is
,
logic block inputs

is
required in the straightforward

variables.
nl n where n
the
number of
9
With nine
variables,
W 2"=9.2
=4608
n,
The reader may find it interesting to compare, for other values of number of logic block inputs required with each approach. One more example, with n = 7, is given for study in Fig. 8-16.
the
Figure 8-16
The number of logic block inputs

3
is
2 2 2 2
X 23 X 2 X 2 X 24 X 27
2
2
= 24 = 8 = 8 = 32 = 256
328
logic block inputs
is
With the straightforward approach, the number of

7-2
7
=896
of the most economical
If all possible outputs are used, the "cost"
network is, of course, the same regardless of how the variables are grouped. However, if all of the outputs are not used, the choice of variables in each group can affect the circuit cost, as illustrated in Fig. 8-17. In this example, a saving of three two-input and's results if the variables are grouped AD and BC, rather than AB and CD. The reader may wish to investigate the result of grouping AC and BD.
PROBLEMS
1.
Equalize, as
much
as possible, the contact load
on a
full tree
of
five
relays A, B, C,
D, and E.
Chap. 8
PROBLEMS
123
A A B B
AND
AND
AND
AND
CC D D
AND
AND
AND
AND
AND
AND
AND
--3
(ABCD)
^5
(ABCD) (ABCD)
(ABCD)
7
*-12
AND
AND
AND
-H4
-H6
(ABCD)
(ABCD)
AADD
AND
14 two- input AND'S
AND
BBC
C
AND
AND
AND
-i
AND
-*-3
(ABCD)
(ABCD)
(ABCD) (ABCD)
(4/9CZ?)
AND
AND
-*-5
-+>7
AND
AND
AND
Equivalent circuit with
11
-*H2
-14
16
(ABCD)
two- input AND'S
Figure 8-17
124
Chap. 8
2.
Minimize the number of transfers in the following

(a)
partial relay trees,
Output Combinations
ABCD
0000 0010
0011
0101
0111
1000 1110
1111
(b)
Output Combinations
ABCD
0100 0110
1001
1011
1100
1101
1110
1111
3.
The map
tree.
in Fig. 8-18
shows the output combinations of a
partial relay
How many
transfers are required if
(a) relay
(b) relay
(c)
relay
A is connected to the input ? B is connected to the input? C is connected to the input?
(d) relay
D is connected to the input ?

AB
CD 00
01
1 1
00
01
11
10
1
10
Figure 8-18
*4.
The map
tree.
in Fig. 8-19
shows the output combinations of a

are required if
partial relay
How many transfers
Chap. 8
PROBLEMS
125
(a) relay
(b) relay
(c)
relay
A is connected to the input? B is connected to the input? C is connected to the input?
(d) relay
D is connected to the input?

AB
CD 00
01
1 1 1
00
01
1
11
10
10
Figure 8-19
5.
Design the most economical electronic trees for five, six, eight, and ten How many logic block inputs are saved over the straightforward approach in each case?
variables.
*6.
Design the most economical electronic trees for eleven and thirteen How many logic block inputs are saved over the straightforward approach in each case?
variables.
Symmetric Functions
Design a
circuit that will
be closed
if
and only
if
exactly three out of a total of
eight relays are operated.
understanding of symmetric functions is useful in the design of switching circuits, particularly relay contact networks (see example above), where symmetric switching functions lead directly to bridge and non-planar
An
networks that are
much more economical than
the best series-parallel
circuit otherwise obtainable.
Variables of
Symmetry
The function
said to be
is
XYZ + XYZ + XYZ symmetric in X, Y, and Z since the successive interchanges

126
of
Chap. 9
m-OUT-OF-n FUNCTIONS
127
interchanging of
any two of the variables X, Y, and Z leaves the function unaltered. The X and Z, for example, that is, the replacement of all X's with Z's, all X's with Z's, all Z's with and all Z's with JP*s, results in
X% ZYX + ZYX + ZYX
which
in
is
identical with the original function. X, Y,
and
in this function
are called the variables of symmetry.
A symmetric function is defined as one

symmetry were uncomple-
which the interchange of any of the variables of symmetry leaves the

In the preceding function,
all
function identically the same.

variables of
mented. Sometimes, in a symmetric function, some of the variables of
symmetry may be complemented. For example, the function
XYZ + XYZ + XYZ

is
symmetric in X, Y, and Z, that is, X, Y, and Z are the variables of symmetry. Again, the interchanging of any two of the variables of symmetry will result in the identical function. For instance, interchanging
and
Z (replacing
all
X's with Z's,
all
Z's with Z's,
all
Z's with
X%
and
all
Z's with X's) results in
ZYX + ZYX + ZY
which
is
identical to the original expression.
some of the variables of symmetry are complemented is usually not obvious, and this subject will be taken up later in this chapter.
recognition of symmetric functions in which
The
m-ouf-of-n Functions
Symmetric functions in which all of the variables of symmetry are uncomplemented are usually known as such in advance by the circuit specifications and are called m-out-of-n functions. Algebraically, these
functions equal
1
if
exactly
out of the n variables equal
1.
For example, the function
ABC + ABC + ABC

can be described as a "symmetric 2-out-of-3 function of the variables, A, B, and C," and can be written in "symmetric notation" as
S\ABC
A, B, and
are the variables of symmetry,
when
exactly
two of the three
variables equal
and the expression will equal 1 1 and under no 6ther

/w's.
conditions.
Symmetric functions may be defined by multiple

the function
For example,
128
SYMMETRIC FUNCTIONS
Chap. 9
XY + XZ + YZ
equals
1
only
if
two or three of the
variables equal
1.
This function can be
written in symmetric notation as

"2, 3-<* YZj
and can be described as a symmetric variables X, Y, and Z.
2-
or 3-out-of-3 function of the
Boolean Operations with Symmetric Notations

Boolean operations can be performed with symmetric notations that is, expressions with the same variables of symmetry can be ANDed and ORed, and these expressions or the variables of symmetry or both can be complemented. First, the ANDing of symmetric functions will be examined.
;
Example
(S\t%i ABCDE)(Sl, A ABCDE)
= S\ ABCDE
ti
S\
%i
ABCDE
1.
equals
if
one, two, or four of the variables of symmetry

1
equal
S\ t%<i ABCDE equals
if
two, three, or four of the variables of
symmetry equal 1. For the product to equal 1, both terms must equal 1, and this can occur only if either two or four of the variables of symmetry
equal
1.
Thus, ANDing two symmetric functions containing the same variables

of symmetry
is
accomplished by retaining those subscripts
common
to
both terms.
equals 0.
If there are
no subscripts
in
common,
the product, of course,
Next, the ORing of symmetric functions will be examined.
Example:
S5 l2A ABCDE
The sum of the two terms
two symmetric functions,
+ SlÂBCDE = S\<2iA ABCDE

1
will equal
if either
term equals
1.
1,
that
is, if
one,
two, three, or four of the variables of symmetry equal

all
Thus, in ORing
n, occurs,
of the subscripts in both terms appear in the
final expression. If every possible subscript,
from
through
the
sum equals 1 Now, the complementation of a symmetric

Example:
function will be discussed.
S 5wi ABCDE
The function S\
2 3
= S% ABCDE
5
ABCDE is
not equal to
1 (is
equal to 0)
if
one, two,
Chap. 9
SYMMETRIC RELAY CONTACT NETWORKS
129
three, or four
of the variables of symmetry equal

1
1. It is
logically equivalent
to say that this function equals
for any condition other than one, two,
symmetry equalling 1. The only other none or five of the variables of symmetry equalling 1. Thus, complementing a symmetric function is accomplished by supplying all subscripts, from through n, that are missing from the original expression. Jnrthe^xample, the missing subscripts are and 5. ;ration of complementing the variables of symmetry will be
three, or four of the variables of
possible conditions are
'
exai
Sl 3 ABCDE
= SitABCDE
The expression S\MBCDE equals 1 if one or three of the variables of symmetry equals 1. Saymg that one of the variables of symmetry equals 1 is the same as saying that n minus one (or, in this example, four) of the variables of symmetry equal 0. Saying that three of the variables of symmetry equal 1 is the same as saying that two of the variables of symmetry
equal
0.
Therefore, another
way of
saying that a symmetric function equals
if
one or three of the

function equals
Still
five variables
of symmetry equal
is
to say that the
1 if two or four of the five variables of symmetry equal 0. another way of saying the same thing is that the function equals 1 if two or four of the complemented variables of symmetry (A, B,C,D, and E)
equal
1.
Thus, another way of writing a symmetric function is to complement all of the variables of symmetry and obtain a new set of subscripts by subtracting each of the original subscripts
from the
total
For
practice, the equivalence of the following four

verified.
number of variables. symmetric expressions
should be
S*
Mi ABCDE
S^ ABC DE
SI*,
S% AAA ABCDE
ABCDE
Symmetric Relay Contact Networks

Suppose a relay network is desired that is closed only when exactly three out of a total eight relays are operated. The Boolean expression for this circuit might start out like
ABCDEFGH + ABCDEFGH + ABCDEFGH +

for 56
(8
etc.
C)
3
terms. Examination of this expression will
show
that
no sim-
130
SYMMETRIC FUNCTIONS
Chap. 9
plification is possible other
than factoring. However, a 3-out-of-8 circuit is a symmetric circuit, and circuits of this type can be designed in a matter of seconds, even though they may be complex bridge networks or even
nonplanar networks.
First, the general structure
of symmetric networks will be examined.
Symmetric Trees
A +
symmetric tree
is
a multi-output relay circuit with one input and

is
outputs, where n
the total
outputs are numbered from

ated, the
through
number of relays in the n, and with m out of n

is
circuit.
The
relays oper-
output
is
connected to the input.

three-relay symmetric tree
As an example, a
shown
in Fig. 9-1,
in conventional symbolic form,
and
also in a diagrammatic
both form that is
convenient to use for symmetric
circuits.
S
A'
-3
->1
</
--0
Figure 9-1
Referring
first
to the circuit diagram

is
on the
1
left, it
can be seen that with

should be obvious
zero relays operated, the input

operated, the input
is
connected to the
output;
output; with one relay

etc. It
connected to the
that a circuit structure of this type can be extended to include any
number
of relays. The diagram on the right represents the identical circuit. To 1 horizontal 1 vertical guide lines and n construct such a diagram, n
guide lines are drawn, as shown. Then n relay designations are written at the bottom, in the spaces between the vertical guide lines. At the right, the
horizontal guide lines are labeled, from bottom to top, with the output
designations
shown;
lines
all
to n. Horizontal and diagonal lines are then drawn as horizontal lines between two vertical guide lines represent
all
normally-closed contacts on the relay indicated below, and
diagonal
between the two
vertical guide lines represent
normally-open contacts
a portion of a sym-
on that relay. For the usual symmetric

metric tree
closed only
is
circuit requirement, only
required. Suppose, for instance, a
circuit is desired that is
when
exactly three out of eight relays,
through H, are
Chap. 9
131
operated. This circuit requirement can
be written in symmetric notation as
S\ABCDEFGH
The circuit can immediately be drawn, as shown in Fig. 9-2. Nine vertical guide lines are drawn one more than the total number of relays involved
Figure 9-2
leaving a vertical space for each of the

eight relays.
Four horizontal guide lines are drawn one more than the number of relays that must be operated for an outputthe topmost guide
Only that portion of the
line representing the 3 (relays operated) output.
symmetric tree leading to the 3 output is then drawn. The order of the relays is arbitrary; no matter what the order, the circuit diagram remains the same. Also, the contact distribution cannot be equalized; a relay closer to either end of the diagram usually requires fewer
contacts than one nearer the middle of the diagram.
Identification of Transfer Contacts
Figure 9-3 shows a method for identifying transfer contacts on symmetric small arc is drawn between a normally-open and circuit diagrams.
normally-closed contact, signifying a transfer contact. Six transfer contacts

are required for the symmetric tree in Fig. 9-3.
The
3-out-of-8 circuit
is
redrawn in Fig.
9-4,
is
with the transfer contacts
one transfer contact each; identified. Note that on relays C and F, three transfers relays each; on transfers on relays B and G, two one normally-closed plus transfers three E, each; and on relays D and
and
H there
contact each.
A <^ // / B
A
Figure 9-3
Figure 9-4
Symmetric Circuits with Multiple m's
Symmetric circuits in which an output is desired for two or more difcircuits defined by symmetric notations ferent numbers of relays operated be discussed. will now with multiple subscripts
132
SYMMETRIC FUNCTIONS
Chap. 9
Suppose, for instance, that a circuit require-
ment
is
S\ i3 ABCDE. That part of a symmetric

"one-out-of-five"
tree giving outputs for
"three-out-of-five" can be drawn,
puts connected together, as
and and the outshown in the diabe

followed
gram of
Figure 9-5
Fig. 9-5.
This procedure can

regardless of
always
numbers of operated relays lead to an output. However, in general, this is not the most economical way of realizing such circuit requirements, and some methods for obtaining more economical circuits will now be examined.
different
how many
Elimination of redundant transfer contacts.

gression with a difference
eliminated, as illustrated
When
symmetric
circuits are
defined by notations with multiple subscripts forming an arithmetic pro-
of one, redundant transfer contacts can be by the following example.
Example
S
A S\ ABCDE circuit is required (Fig.
9-6).
Figure 9-6
In the left-hand figure, pay particular attention to the point marked X.
The
and the output is a parallel path consisting of a circuit between normally-open and a normally-closed contact on E, which is equivalent to
a closed
circuit.
Therefore, point
can be
common
to the output,
and
these contacts
on the right. Note that since the remaining normally-closed and normally-open contacts on E are both common to the output, they actually form a transfer contact although not shown adjacent on the diagram. The simplification principle illustrated in the above example can be extended to cases with more than two subscripts, as the following example
shows.
can be eliminated, the circuit reducing to that shown All points shown in heavy dots are common output points.
on
Example:
A S\ iABCDEE circuit is required (Fig.

3
,
9-7).
Chap. 9
133
Figure 9-7
Note, in the
left
diagram, that there
is
a closed circuit between the point
Y and the output, and between Z and the output; therefore, points Y and Z can be common to the output and two transfers on F can be eliminated. There is also a closed circuit between point X and the common points Y and Z. Thus, point X can also be common to the output, and a transfer on E can be eliminated. The final circuit is shown at the right.
Shifting down. If the multiple subscripts
form an arithmetic progression
with a difference greater than one, and the next step in the progression would be greater than the number of variables, a process called "shifting
down" can be used to achieve economy. Shifting down could not be used in the two previous examples because
the arithmetic progression
was not greater than one. A S\A ABCDEF circuit cannot be shifted down because even though the difference in the subscript progression is two, the next step in the progression would be 6, and 6 is not greater than the number of variables. Presently it will be seen why such
a circuit cannot be shifted down.
S5 2i ABCDE
circuit
can be shifted down,

is
as illustrated in Fig. 9-8. First, a circuit with
drawn, in this case a 2-out-of-5 circuit. Then, instead of the remaining circuitry (4-out-of-5) being drawn in the usual manner, the 2-out-of-5 output is
an output for the lowest subscript
zglz
Figure 9-8
1
also
made
4-out-of-5
output
shift
still
by
using
the 2 level to the
level, as
normally-open contacts to
down from
used to represent normally-open contacts; in shifting down, they slant in the opposite direction, however. The 1 level, in a sense, now also becomes the 3 level, that is, the 1 level is connected to the input if 1 or 3 relays are operated. The 2 level then also
shown. Diagonal
lines are
becomes the 4
level,
and the output
is
connected to the input
if
two or four
relays are operated.
The following example
illustrates
is
the next step in the progression
why a shift down cannot be made if not greater than the number of variables.
'
134
SYMMETRIC FUNCTIONS
Chap. 9
Example:
S\ 4 ABCDEF circuit
is
required.
In the circuit of Fig. 9-9, a shift down has been made in an attempt to realize the required
zgg?z
Figure 9-9
function.
An
is
output for two or four relays operated

output,
obtained, as desired. However, if six relays
are operated, there will also be an
which
a 5| 4
,
is
s
not desired. The circuit shown in thus

as illustrated
ABCDEF circuit.
shift
down may be made through any number of levels,
in the next example.
Example:
A SlsABCDEFGHl circuit is
required.
The number of
levels
shifted
down
is
one
less
than the difference

is
in the subscript progression. In this
example, the difference

4); therefore levels is
four (8
a shift
down
of three
made
(Fig.
9-10).
Four
relays operated connect the input to
the 4 level.
Figure 9-10
The normally-open conshift
tacts
is
used for the
down
the
represented by the long diagonals

"fifth" relay operated.
columns
and
Fconstitute
Three more relays operated, totaling eight in all, again connect the input to the 4 level. Sometimes additional levels must be added before a shift down can be made.
Example:
A SlsABCDEFGHI circuit
five levels is indicated.
is
required.
is six,
Since the difference in the subscript progression
shift
down of
must therefore be brought up to the 5 level before a five-level shift down can be made, as shown in Fig. 9-11. Equivalent points. Another simplification procedure is based on the recognition of equivalent points in the circuit diagram. This procedure will be illustrated by an example.
circuit
The
Example:
A S\ ABCDE circuit
t3
is
required. Since a shift
down cannot be made,
the circuit in Fig. 9-12
is
drawn. Note that points
W and
each have a
Chap. 9
SYMMETRIC RELAY
CONTACT NETWORKS
135
Figure 9-11
normally-closed contact on
fore, points
E between them and the common
output. There-
W and
on
Y can
closed contact
is
required. Similarly, points
be connected together, and only one normallyand Z each have a
normally-open contact on
E between them and the

together,
output. Therefore, points
X and Z can be similarly connected

on
and a normally-open contact
E eliminated
(Fig. 9-13).
connect points
Carrying this same procedure further, normally-closed contacts on D T and V to a common point, while normally-open contacts
therefore can be connected
V to another common point. Points T and V and a transfer contact on D eliminated. Normally-closed contacts on D connect points S and U to a common point; however, a normally-open contact on D connects point U to a point that is not similarly connected to point S. Therefore, points S and U are not equivalent and cannot be connected together. No other simplification is possible, and the final circuit is shown in Fig. 9-14.
on
connect points
and
Figure 9-12
Figure 9-13
Figure 9-14
Another design approach complement of the desired symmetric network can be drawn, and this network graphically complemented. The network to be complemented must, of course,
Complementation
of symmetric networks.
involves graphical complementation (see Chapter 5): the
be planar.
Example:
A Si 13ii ABCD circuit is required.
136
SYMMETRIC FUNCTIONS
Chap. 9
>
0ili3ii
sxu^jLs
S\ABCD.
Therefore, a
(Fig. 9-15).
S\ABCD
circuit
can be drawn
and graphically complemented
zg?
A\B
S\
Complement
J4
i_L
5o,,, 3 ,4
ABCD
ABCD
Figure 9-15
considered
Complemented variables of symmetry. The last design approach to be makes use of complementing the variables of symmetry.
for example, that
Remember,
Sl s ABCDE
be closed
S\ A ABCDE
In a relay network realization, the left-hand expression states that the

circuit is to
if
exactly one or three out of the five relays are operstates the
ated.
The right-hand expression

is
namely, that the circuit
to be closed if exactly
same thing in a different way, two or four out of the

shift
five relays are unoperated.
An
advantage of complementing the variables of symmetry is that a

that
down may become possible

a S\ 3 ABCDE circuit
circuit
would otherwise be impossible. For instance, cannot be shifted down, but the equivalent S\ A ABCDE
can be
(Fig. 9-16).
In the diagram, the complemented variables of symmetry signify that the

represent
meaning of the horizontal and diagonal lines are reversed the diagonal lines normally-closed contacts, and the horizontal lines represent
:
normally-open contacts.
zillE
Figure 9-16
zIW
Figure 9-17
Shift
downs with three or more
tion, three or
more
subscripts
subscripts. When, in the symmetric notado not form an arithmetic progression, care
Chap. 9
DETECTION
AND
IDENTIFICATION
137
must be exercised
possible since
it
in shifting
down. For instance, with a Sl 25 ABCDE

to
circuit requirement, a shift
down
make
the 2 level also the 5 level
is
not
introduces a false output for the 3-out-of-5 combination
ABCDE (Fig.
or not a
circuit
shift
9-17).
down
The number of variables involved may affect whether is possible. For example, a shift down is possible in a
it is
S\i%i ABCD circuit (Fig. 9-18) whereas

because a
false
not possible in a S\t%i ABCDE

,
output for 5-out-of-5
is
introduced (Fig. 9-19).
z^2=
A
zmn ABCDE
Figure 9-19
Figure 9-18
Detection and Identification of Symmetric
Switching Functions
So
(or
far,
the discussion of symmetric functions has been centered

all
on the
m-out-of-n type, in which

all
the variables of symmetry are uncomplemented

the variables of symmetry
complemented). The detection and identification of symmetric
functions in which any
number of
discussed.
may be com-
plemented
will
now be
In testing for symmetry, all combinations of complemented and uncomplemented variables could, of course, be investigated, but with a large number of variables such a method would be impractical. A method which
uses
tables
of combinations
for
detecting
switching functions will be shown. This
and identifying symmetric method is given without proof,

gives
but a study of the behavior of symmetric functions manipulated in tabular
form can verify the validity of the method. Figure 9-20 this method in diagrammatic form.
an outline of
Step
The switching function to be tested for symmetry is written as a table of combinations, each variable appearing (uncomplemented) at the head of its respective column. The table should be checked to assure that no row combination occurs more than once. The arithmetic sum of each row
in the table
is
obtained and written to the right of the row. All row sums
are then checked for "sufficient occurrence" ; if n represents the

variables (columns)
and
r represents
a row sum, then that row
number of sum should
occur
138
SYMMETRIC FUNCTIONS
Chap. 9
Write table of combinations Obtain row sums Check for sufficient occurrence
Zo
Compare total of two sums with number of rows in table

Not equal
Compare with one-half number of rows in table

Not equal
Equal
N
Select any row sum of insufficient occurrence except r Obtain partial column sums
-
n/2.
More than two different sums
Two different sums
All
sums
No selection possible
only insufficient
No. var.
identical
No. var.
r-n/Z
odd
even
Aa
Doubly- complement selected columns Obtain new row sums Check for sufficient occurrence
Sufficient
Insufficient
4>
Doubly-complement selected columns Obtain new row sums Check for sufficient
occurrence
Sufficient
Insufficient
4<r
Doubly-complement any one column Obtain new row sums Check for sufficient
occurrence
Sufficient
Insufficient
I
N
N
is
if
Repeat
3.5,
and
5
)
\
indicated, 4. If 4c is indicated again, function is
Function
Function
symmetric
not symmetric
not symmetric
is
Outline of method for detection and identification of symmetric switching functions
Figure 9-20
Chap. 9
DETECTION
AND
IDENTIFICATION
39
r\(n-r)\
times. This
r at
is
the formula for the
number of combinations of n
things taken
a time (Cr ). The following table gives the required row sum occurrences for up to eight variables. This table is an adaptation of Pascal's triangle,
and may be extended to include
as
many
variables as desired.
Table of Required
Row Sum
Occurrence
Row Sum
Number
1
of Variables
5
1
2
1
3
1
4
1
6
1
7
1
8
1
2
1
3 3
1
4
6
6
15
7
21
2
3
10
10
5
1
28
4
1
20
15
35 35
21
56
4
5
70
56
28
8
1
6
1
6 7
8
7
1
row sums occur the required number of times, the function is symThe row sums represent the subscript numbers, and the variables of symmetry are denoted at the head of the columns. If all row sums do not occur the required number of times, go to Step 2.
If all
metric.
Example:
A B C
1 1 1 1 1 1 1 1 1
2
3
2
2
The required occurrence of row sum

3!
2,
with 3 variables,
is
2!1!
=3
140
SYMMETRIC FUNCTIONS
Chap. 9
The required occurrence of row sum

3!0!
3,
with 3 variables,
is
-li-=l
Both row sums 2 and
function
is
3 occur the required number of times therefore, the symmetric and can be expressed as
;
SUABC
Step 2
The
arithmetic
at the foot of the
sum of each column in the table is obtained and written column. If more than two different column sums occur,
column sums are
identical,
the function
is
not symmetric. If exactly two different column sums occur,
go to Step
3a. If all
go to Step
3b.
Example:
A B C D
1110
12
This function sums.
is
111
3
11
not symmetric because there are three different column
Step 3a
The
total of the
two
different
column sums
is
obtained and compared

is
with the number of rows in the table. If the total of the two sums
equal to the
If the total
not
number of rows in the table, the function is not symmetric. equals the number of rows in the table, go to Step 4a.
Step 4a
column sums is selected (preferably the one columns totaling the selected sum are doublycomplemented: all l's in the column are changed to 0's all 0's are changed to 1 's, and the variable at the head of the column is complemented. Note that the meaning of a column is not changed by double-complementation:
Either of the two different
all
of lesser occurrence) and
if if
X = 0,
X=l,
then then
X= X=
Chap. 9
DETECTION
AND
IDENTIFICATION
141
the doubly-complemented columns,
column sums are corrected to represent the new total for all column sums will now be identical. New row sums are obtained and checked for sufficient occurrence. If all row sums occur the required number of times, the function is symmetric;
If the selected
otherwise, the function
is
not symmetric.
Example:
ABC
10
1 1
1
ABC
10
= ~
1
113
the total of these two sums
(1
111
In this example, there are two different column sums, 1 and 3, and is equal to the number of rows in the table
+ 3 = 4).
Column sum
1,
is
selected because
it
occurs less frequently
than column sum
and column
C is
doubly-complemented.
Step 3b
The
(identical)
rows in the
table. If the
is
the function
column sums are compared with one-half the number of sums are not equal to one-half the number of rows, not symmetric. If the sums are equal to one-half the number
3.5.
of rows, go to Step
Step 3.5
Any row sum

metic
of insufficient occurrence except
= nil
is
selected,
and
only the rows totaling this
sum
are considered in obtaining a partial arith-
sum of each column.

is
the function
If more than two different partial sums occur, not symmetric. If exactly two different partial column sums
occur, go to Step 4b. If all partial
column sums are
identical,
and the number
of variables
is
is
odd, the function
even,
and
all
not symmetric. If the number of variables partial column sums are identical, or the only row sum of
is
insufficient occurrence is
equal to n/2 so that no row
sum
selection
may
be made, go to Step
4c.
Step 4b
Either of the
two
different partial
column sums
is
selected (preferably
142
SYMMETRIC FUNCTIONS
Chap. 9
the one of lesser occurrence) and

this partial
all
columns
in the entire table that
contain
sum
are doubly-complemented.
New row
sums are obtained
and checked for sufficient occurrence. If all row sums occur the required number of times, the function is symmetric; otherwise, the function is not
symmetric.
Example:
ABC
1 1
1 1
ABC
2 2
1 1 1 1
ABC
2
2
1 1 1 1 1 1
1 1
3
1
1 1 1 1
2
2 2
and they are equal to 6). Either row sum 2 or row sum 1 may be selected since neither occurs the required number of times. Row sum 2 is arbitrarily chosen in this example. Only the first two rows which total this row sum 2 are considered in obtaining a partial sum of each column, as shown in the middle table. In the example, exactly two different partial column sums, 1 and 2, occur. Partial column sum 2 is selected because it occurs less frequently than partial column sum 1, and column C, in the original table, is doublycomplemented. New row sums are obtained and checked for sufficient occurrence. The function is found to be symmetric and can be expressed as
identical
(3
In this example,
one-half the
all column sums are number of rows in the table
S\ A ABC
Step 4c
Any one column in the original table is selected and doubly-complemented, and new row sums are obtained and checked for sufficient occurrence. If all row sums occur the required number of times, the function is symmetric. If any row sum does not occur the required number of times,
repeat Step 3.5 and,
if indicated,
is
Step 4b. If Step 4c
is
indicated again,
it is
not repeated and the function
not symmetric.
Once a symmetric function has been detected and identified, the corresponding relay contact network can be designed using the symmetric tree
approach previously discussed. If a variable of symmetry is uncomplemented, the corresponding diagonal lines represent normal! '-open contacts
Chap. 9
PROBLEMS
143
and the horizontal lines represent normally-closed contacts; if the variable of symmetry is complemented, the meaning of the lines is reversed, the horizontal lines representing normally-open contacts and the diagonal
lines normally-closed contacts.
is
As an example, the shown in Fig. 9-21.
relay contact
network for the function
S\ABCDE
Figure 9-21
PROBLEMS
1.
Design relay networks for the following symmetric functions:

(a)
(b)
(c)
ÂBCDEFGH S\A ABCDEF

S\ A
SliABCDEFG
S{ 6 ABCDEFG
(d)
*(e)
*(f)
2. (a)
Sf w ABCDEFGHIJKL
S\xih ABCDEF S\xi ABCD
lt3
3.
+ S\ ZA ABCD = (b) si' EFGH + S\xi EFGH = (c) SiJJKL-StJJKL = (d) S^MNOP = (e) QRST = S QRSf (Fill in missing subscripts.) (f) S{ UVWX = S'UVWX (Fill in missing subscripts.) Redraw the X contacts pictorially, identifying the numbered terminals.
4
<S1,s
2>4
144
SYMMETRIC FUNCTIONS
Chap. 9
*4.
Redraw
pictorially.
zSz ABCD
Figure 9-23
5.
Detect and identify symmetry,
if
any
(c)
ABCDE
00010
00100
00111
(b)
ABCD
0001
ABCD
0000 0110
0101 1010
1001
*(d)
ABCDEF
000110
001001
0010
0111
010010
010100
100001
oino
10000
10011 10101
1000
1101
1110
mi
101000 010111
11010 11100
11111
011110
101011 101101
110110
111001
10
Reiterative
Networks
Forty relays are numbered consecutively from
to 40. Design a circuit that will

is
be closed
if
and only
if
one
set
of three consecutive relays
operated and
all
other
relays are unoperated.
circuit of the type required above is called a positional circuit because each relay occupies a definite physical position relative to the other relays.
Such a
circuit is also called
a reiterative (or
iterative) circuit
because of
its
inherent repetitive pattern. Because of this repetitive pattern, these circuits
can be designed by a procedure quite

discussed so far.
different
from those that have been
Symmetric networks fall under the class of reiterative networks also, and can be designed using the same procedure as that for positional networks. However, symmetric networks are more commonly designed using the symmetric tree approach that has been previously discussed. For this
reason, the examples in this chapter will deal exclusively with the design
of positional networks.
145
146
REITERATIVE
NETWORKS
Chap. 10
Positional requirements may specify the number of sets of consecutive operated or unoperated relays, without specifying the number in each set.
Example:
A
circuit
circuit
of twenty relays
is
to be closed if
all
and only
if
three sets of
consecutive relays are operated and
other relays are unoperated. This
should be closed, for instance, if relays 2, 3, and 4; 6, 7, 8, and 9; and 15 and 16 were operated, and all others were unoperated. A positional requirement may also specify the number of consecutive relays that must be operated or unoperated in each set, without specifying
the
number of sets.
Example:
circuit
of twenty relays
is
to be closed if
and only
if all sets
of conall
secutive relays operated contain three relays. This circuit should be closed,
for instance, if relays 4, 5,
and
6;
and
13, 14,
and 15 were operated, and

sets
others were unoperated.
positional requirement
may
specify
both the number of
and the
number of consecutive
Example:
relays operated or unoperated in each set.
A circuit of twenty relays is to be closed if and only if there are two sets
of consecutive relays operated, one
relays 8
set
containing three relays and the

others were
other set containing two relays. This circuit should be closed, for instance,
if
and
9;
and
18, 19,
and 20 were operated, and
all
unoperated.
Design of Reiterative Networks

In the design of reiterative networks the
number of
relays involved
is
immaterial, and the contact configuration for only one relay
1 be thought of as a prototype relay is designed. In this contact configuration, the number of input lines and the number of output lines are the same. This configuration is then repeated for all relays, and the configurations of the various relays are "strung together," the output lines of one
which
can
relay circuit
The prototype
becoming the input lines to the following relay circuit. relay circuit can be thought of as being one somewhere
information concerning
lines,
all
in the middle of a chain of identical relay circuits.

lines carry pertinent
The prototype input of the preceding relays.
The prototype output
which are the input
lines to the following relay,
carry similar information except that
now
the information pertains to the
prototype as well as to
all
of the preceding relays.

relays.
Sometimes economy can be achieved by using a prototype of two or more
Chap. 10
DESIGN OF REITERATIVE NETWORKS
147
The design problem is then: (1) how many lines must carry information from relay circuit to relay circuit, and what should this information be; and (2) how should the prototype relay circuit modify this information by
properly connecting the input lines to the output lines?
Sample Problem
The design procedure

problem
:
will
circuit
of forty relays
is
be explained by working through a sample is to be closed if and only if one set of

all
three consecutive relays
operated and
other relays are unoperated.
Thinking of the prototype relay as being somewhere in the middle of the "string" of relays, we ask, "How many different types of conditions of the relays preceding the prototype can lead to a final circuit output?"
1
If
none of the preceding relays have been operated,
it is still
possible
to get a circuit output.

2. If just one of the preceding relays is operated, and it is the one immediately preceding the prototype, a circuit output can be realized. This preceding relay would represent the first of a possible set of three con-
secutive relays operated.

If there
the prototype,
relays,
one relay operated and it is not the one immediately preceding it must have been followed by one or more unoperated creating a "set of one relay operated." Such a condition violates
is
is, if
the circuit requirement, that
such a condition exists there should be

it is
no
circuit output.
3.
If just
two preceding
if
relays are operated
possible to obtain a
circuit
output only
they are the two consecutive relays immediately pre-
ceding the prototype.
preceding relays representing the

secutive relays operated.
4.
The reasoning here is similar to condition 2, these first two of a possible set of three con-
consecutive relays operated
Only one more possible condition may lead to a circuit output: three and all others unoperated. In this case, the relays
may
or
may
not immediately precede the prototype.
circuit output.
Thus, there are four different possible conditions that can lead to a There will be an input line to the prototype relay circuit,
line, for
and a corresponding output
each of these conditions. Figure 10-1
represents the progress so far.
No
relays operated
No
Prototype
relay
circuit
relays operated
Only last relay operated Only last 2 relays operated Only 3 consecutive relays operated
Only last relay operated Only last 2 relays operated
2-
Only 3 consecutive
relays operated
Figure 10-1
148
REITERATIVE
NETWORKS
Chap. 10
The input and output lines have been numbered for reference. Note that the input and output lines are identical, the input lines carrying
information concerning
all
preceding relays, whereas the output lines carry
information on the prototype relay as well as on all preceding relays. The next step is to properly connect the input and output lines with
These connections can be indicated in a table constructed as follows: there is a row for each input condition, each row being labeled with the corresponding reference number; and there are
contacts
on the prototype
relay.
two columns, labeled

prototype relay
and
1,
representing the
two possible
states
of the
unoperated
No relays
Only Only Only
last
and operated
respectively.
operated
operated
last relay
2
3
2 relays operated
3 consecutive relays operated
The
relay
is
line that
row and column will be the number of the output should connect to the input line for that row when the prototype in the state indicated by that column.
entry in a given
in the table,
is
To
fill
first
consider input line
1no
line
relays operated. If the

1
prototype relay
to output line
unoperated
0.
column input
1
must be connected
is
1no
1,
relays operated; a
(for output line 1)
therefore
entered in
row
column
Output
line 1, in representing
all
no relays operated,
line
includes the prototype relay as well as

If the prototype relay is operated
preceding relays.
column
1input
must be
a 2 (for
connected to output line
2only
last relay operated; therefore,
output line 2) is entered in row 1, column 1. Output line 2 represents only last relay operated since only the prototype relay is operated under the
above conditions. Input line 2 represents only
last relay operated, that is,
the relay immediIf the prototype
ately preceding the prototype is the only
one operated.
relay is unoperated, a "set of
output
a
" "
is is
one relay operated" is created. A circuit not wanted for this condition, and therefore in row 2, column 0, entered, signifying that none of the four output lines should be
line 2.
is
connected to input
output line 3
If the prototype relay
operated, input line 2 must be connected to

is
only last two relays operated. Thus, a 3

"
entered in
row
2,
column
1.
By
similar analysis, a
"
is
entered in
row
3,
column
0,
and a 4
is
entered in
row
3,
column
1.
Now
consider the case where input line
4only
three consecutive relays
Chap. 10
DESIGN OF REITERATIVE NETWORKS
149
operated
is
connected to the circuit input. If the prototype relay
is
un-
operated, input line 4 must be connected to output line 4. If the prototype

relay
(if
is
operated, either a "set of four relays operated"
would be created
the three consecutive relays operated were those immediately preceding

(if
the prototype), or a second set would be started
the three consecutive
relays operated were not immediately preceding the prototype). In either
no circuit output column 1.

case,
is
wanted and,
therefore, a "
"
is
entered in
row
4,
Finally, information concerning the final circuit output is recorded in
the table.
Remembering
that the input
and output
lines are identically
designated, think
now about
the lines leaving the last relay in the string.
The
4
lines that will serve as the circuit
output are noted by circling the cor-
responding reference numbers at the

will
left
of the table. In
table follows.
this
example, line
be the only
line
used as the
final circuit
output; therefore the 4 at the
left
of the table
is circled.
The completed
2
3
2
3
(D
realized
by the use of normallycolumn 0, and by normally-open contacts establishing the connections indicated in column 1. The prototype relay network is shown in Fig. 10-2.
is
The prototype contact network
now
closed contacts to establish the connections indicated in
\x
X^
Figure 10-2
drawn by stringing together forty circuits one above. Considering any relay in the string as a prototype, if the states of all preceding relays are such that a circuit output is possible (the circuit requirements have not been violated), there will be a closed path between the circuit input and one of the inputs to the prototype. If the states of the preceding relays have violated the circuit requirements,
final circuit (Fig. 10-3) is
The
similar to the
150
REITERATIVE
NETWORKS
Chap. 10
\ \ A\\\T \\\\\nN \ \.\

l
N5
U
(
.
t^36-^37^-38-v 39-^40
36
37
38
*39 39
40
4v
5 5
]i.
36
37
38
\ 39 x40 \
\
4 36 37 38 39 40 \ 1-^-2-^-3^-4^-5^-1 1-^-36^-37^-38^39^^0^2X 3 1
Figure 10-3
none of the prototype inputs will be connected to the circuit input. The portions drawn lightly at both ends of Fig. 10-3 represent circuitry that is omitted. There is only one possible input to the first relay: line 1 no relays operated; there are only two possible inputs to the second relay: line 1 no relays operated, and line 2 only last relay operated; etc. Since line 4 is the only circuit output line, similar simplification takes place at the output end of the circuit.
Sequence Representation
To
helpful to write a "string" of 0's
determine the number and types of input and output lines, it can be and l's representing a typical sequence
leading to a circuit output, the 0's representing unoperated relays

l's
representing operated relays. This sequence can then be broken
and the up into
the different kinds of prototype input conditions.
Example:
A circuit of thirty relays is to

each
set.
be closed
if
and only
if
exactly
two
sets
of
consecutive relays are operated. There
may be any number of
relays in
A typical sequence leading to

The
3-
a circuit output might look like
000111100000110000
actual number of relays in the final circuit need not be considered in writing such a typical
sequence.
]2o)oi 111000
3-
4-5--
0011
000
The
different kinds of prototype input con-
ditions can be identified
by "looking back"
In
effect,
at
various points in the sequence.
the
prototype relay
Figure 10-4
is
pictured at these different
points in the sequence, each
breakdown includthe
typical
ing
in Fig
all
relays preceding the prototype.
One way of breaking up

sequence
is
shown
10-4.
There are
five different
prototype input
conditions which are identified.
Chap. 10
ELIMINATION OF REDUNDANT INPUT LINES
151
The
below.
five
conditions and a
word statement describing each
are
shown
00
0001
No relays
Only one Only one Only two Only two
operated
set
of consecutive relays operated, including
the relay immediately preceding the prototype
0001111000
00011110000011
set
of consecutive relays operated, not in-
cluding the relay immediately preceding the prototype
4
5
sets
of consecutive relays operated, including
the relay immediately preceding the prototype
00011110000011000
sets
of consecutive relays operated, not in-
cluding the relay immediately preceding the prototype
table
is
now
constructed, as in the previous problem.
2
3
3 3 5
5
(D
lines,
Note, in this example, that there are two

line
final circuit output. If the last relay is operated, as part
4 and 5, leading to the of the second set,
4 leads to the circuit output; if the last relay is unoperated, that is, if the second set does not include the last relay operated, line 5 leads to the circuit output. The prototype relay configuration is shown in Fig. 10-5.
1
x^-
~^f h
Figure 10-5
2
3
4
5
4 5
Elimination of
Redundant Input Lines
Sometimes, in the design of reiterative networks, more lines than necesA method of eliminating such redundancy will now be described.
sary are inadvertently introduced.
Two
lines are equivalent if (1) they lead to the
same
final circuit
output
152
REITERATIVE
NETWORKS
Chap. 10
condition, that
circuit output,
is,
they both lead to a circuit output or neither leads to a

(2) for
and
each state of the prototype, the two

lines. If
lines lead
to the
is same or equivalent eliminated. redundant and may be Following are shown some basic examples of equivalence. In all examples, only a portion of a table is shown, and lines 1 and 2 lead to the same final
two
lines are equivalent,
one of them
circuit
output condition. In
all
examples,
1=2.
1
4
4
3 3
1 1
3
3
2 2
3 3
3 3
2.
5.
1
2
1
3 3
6.
1
3 3
==
It is
lines.
Therefore, in
1.
by a
customary to retain the smaller reference number of two equivalent all six examples, every occurrence of a 2 is replaced The two rows then become identical and are replaced by a single row.
and 5, in which "the equivalence of lines 1 dependent upon the equivalence of lines 1 and 2." In such cases of interdependence, two lines can be made equivalent. The subject of equivalence also enters into the design of sequential circuits, and is covered more thoroughly in Chapters 14 and 18. An example
Particularly note examples 4
is
and 2
with equivalence follows.
Chap. 10
ELIMINATION OF REDUNDANT INPUT LINES
153
Example:
A A
circuit
of ten relays
is
is
to be closed if
and only
if
exactly one set of
consecutive relays
operated, this set consisting of either one or two relays.

is
solution to this problem
shown
in the following table.
No
relays operated
last relay
Only
operated
@

1
Only one relay operated, not the one immediately preceding

the prototype
3
Only two consecutive
relays operated

lines
It is
immediately seen that line
is
not equivalent to any of the other
lines since it
does not lead to a circuit output while the other three
do. Since lines 2, 3,
and 4
all
lead to a circuit output, these lines are
examined further for equivalence. Next, it can be seen that line 2

the prototype
lines
is
is
not equivalent to lines 3 or 4

line 4.
since, if
operated, input lines 3

line
and 4 do not lead to any output

and 4
is is
whereas input
2 leads to output
Finally, the possible equivalence of lines 3
examined. Both
lines
lead to final circuit outputs; if the prototype

is
operated, neither input line

is
connected to an output
is
line;
and
if
the prototype
unsperated, each
and 4 are and every occurrence of a 4 is replaced by a 3. The third and fourth rows are now identical and are replaced by a single row. The reduced
its
input line
connected to
respective output line. Thus, lines 3
equivalent,
table follows.
No
relays operated
last relay
Only
operated
Only one relay operated, not the one immediately preceding the prototype; or only two consecutive relays operated
it should be intuitively seen that there is no need to between the conditions only one relay operated, not the one immediately preceding the prototype and only two consecutive relays operated, since both conditions represent "set completed," and, in both cases, all relays beyond this point must be unoperated if a final circuit output is to be realized. The prototype relay network is shown in Fig. 10-6. Note the simplification in connecting input line 2 to output line 3, the paralleled normally-open and normally-closed contacts reducing to a closed circuit.
In this example,
differentiate
154
REITERATIVE
NETWORKS
Chap. 10
t-X
v
2 3
J^
Figure 10-6
PROBLEMS
Design the prototype relay circuit for each of the following reiterative requirements: A circuit of n relays is to be closed if and only if
1.
. .
.
there
is
exactly one set of consecutive relays operated, this set
consisting of
2.
.
two or more
relays.
there
is
consisting of one or three relays.

*3. ... there is exactly
one
set
of consecutive relays operated, this
set
consisting of
4.
.
. .
two or three
relays.
any
set
of consecutive relays operated consists of one or three
relays, or if there are *5. ...
no
relays operated.
relays
6.
. . .
any set of consecutive relays operated consists of one or three and there is at least one set.
is
there
consisting of
7.
. .
an odd number of
relays.
there
is
exactly one set of consecutive relays unoperated, this set
consisting of one or
8.
.
. .
two two
relays.
sets
there are exactly
of consecutive relays operated, both
sets
consisting of
two
relays.
*9. ... there are exactly
consisting of one relay

sets
two sets of consecutive relays operated, one set and the other set consisting of two relays. The
of three consecutive relays operated but of any other size.
of consecutive relays operated, this
the
set
may
occur in either order.
10. ... there is exactly
one
set
there
may be any number of sets

one
set
11. ... there is exactly
consisting of three relays; or there are exactly two sets, consisting of one relay and the second set consisting of three relays.
12. ... there are exactly
first set
two sets of consecutive relays operated, the first set consisting of two relays and the second set consisting of three; or the first set consisting of three and the second consisting of one.
Chap. 10
PROBLEMS
155
*13.
there are exactly
consisting of one or
relays.
two two
sets
of consecutive relays operated, one
set
relays,
and the other
set consisting
of three
The
sets
may
occur in either order.
Special Problem
A circuit of ten relays is to be open if and only if there is exactly one set
of consecutive relays operated,
Hint Design a
:
circuit that is closed
the ten relay circuits

entire network.
of one or two relays. under the above conditions, and after are "strung together" graphically complement the
this set consisting
11
Number
Systems; Adders
Number Systems
A number such as
2,547.16
is
not normally thought of as being composed of two 1,000's, five 100's, four 10's, seven l's, one -^, and six yf^'s. However, in a discussion of number
it
systems in general,
in this way.
will
be helpful to think of numbers broken
down
the
In general, the right-most digit to the left of the radical point represents number of l's or Bs, where B is the base or radix of the number system.
digit to the left represents the
The next
the
the
left
number of B^;
the next digit to

left
represents the
3
number of
s;
the next digit to the
iepresents
number of B The left-most
s; etc.
digit to the right
of
B'h;
the next digit to the right represents the
of the radical point represents the number number of B~ 2 s; the next

etc.
digit to the right represents the
number of B~ 3 s;
156
Chap.
11
NUMBER SYSTEMS
157
In the decimal number system, the base

decimal number 2,547.16
is
is
10.
The
analysis for the
shown below.
4
7 7
6
10- 1
= =
x 10 3 2 x 1000
2
5 5
x x
10 2
4 x 10 1 4 x 10
10
1
l
100
7x1
x x
x 10
Xrl
=2000 X 1000 = 500 X 100 = 40 10 4 x = 1 7 7 x 1 X 10 10 6 6 x 10 100

2
5
i i
2547-^
2547.16
In a number system to the base B, there are
different symbols, ranging

10, there are
from
to
1.
Thus, in the decimal system, base

9.
ten different
symbols,
through
The preceding
system.
general concepts will
now be
is
applied to
with other bases. The following number

256.71
written in the base 8
number systems number
This number
it is
is
not two hundred
fifty-six
and seventy-one hundredths. Since

it is
written in the base 8
number
6
system,
analyzed as follows
5
2
7 7
(base 8)
8" 2
1
=2 x 8 = 2x64
81
6x8
8" 1
5x8
2 x 64
6x1
=128
7x{
lx, ,
5x8 6x1
7
1
=6
=40
7
x x
174
(base 10)
256.71 in the base 8
seven
then,
-^'s
and one
-^.
number system represents two 64's, five 8's, six l's, The total 174| in the base 10 or decimal system,
8.
is
the equivalent of 256.71 in base
The above type of analysis can be used

base to
its
to convert
from a number
in
any
decimal equivalent.
a decimal number
convenient method for converting from to a number in some other base follows. The decimal
158
Chap.
11
number is separated into two parts that to the left of the decimal point, and that to the right of the decimal point. Each part is handled in a
:
different way.
The
is
left
part of the
to be converted,
is
procedure
number is repeatedly divided by the base to which it and the remainders are recorded for each division. This continued until the quotient is reached. The remainders,
first,
reading from the last remainder to the
represent the
left
part of the
number in the new base. The right part of the number is repeatedly multiplied by the base to which it is to be converted, and the carries are recorded for each multiplication. This
procedure
last,
is
continued until the product

places
is
is
reached, or
until the desired
number of
obtained.
The
carries,
reading from
in the
the
first
carry to the
represent the right part of the
number
new base. As an example,
the decimal
8.
number 174.890625
will
be converted to
its
equivalent in the base
Left part:
Right part:
Carry
.890625
Remainder
8 8 8
[174
6J
5
\JL
Li
.125000
x
irl
.000000
174 (base 10)
= 256 (base 8)
174.890625 (base 10)
.890625 (base 10)
.71 (base 8)
256.71 (base 8)
For an example of an approximate conversion, the decimal number

.14159 will be converted to
its
"equivalent" in base
3,
correct to four places.
Carry
.14159
x x x x
.42477
3
.27431
3
.82293
3
t2
.14159 (base 10)
.46879
.0102 (base 3)
Chap.
11
NUMBER SYSTEMS
159
few more examples of other number systems and their conversion to and from decimal are given below for study.
(1)
142 (base 5)
1
1
1
=
4
? (base 10)
2
51
X 52 X 25
4 x
1
4 X
2x5
2
4x5
5
2x1=2
x 25
= =
20
25
47
142 (base 5)
= 47 =
(base 10)
(2)
47 (base 10)
5 5 5
|47
? (base 5)
j_9
4
1
JJ
47 (base 10)
= =
x
142 (base 5)
(3)
201 (base 3)
? (base 10)
1
2
=2 x3 = 2x9
31
1x3
0x3
lxl
1x1=1 0x3=0
2 x 9
18
19
201 (base 3)
19 (base 10)
(4)
19 (base 10)
3 3 3
[19
j_6
? (base 3)
1
j_2
19 (base 10)
201 (base 3)
Question:
What
is
the decimal equivalent of 182 (base 8)?
160
Chap.
11
Answer: There can be no such number as 182 in the base 8; in this base through 7. There is no symbol for 8 in the base 8 number system, any more than there is a symbol for 10
there are only eight allowable symbols,
in the decimal system. In the base 8
number
system, a
1
in the 8's position in the 10's position
represents the value
8, just as in the decimal system, a
represents the value 10.
The binary or base 2 number system is of particular importance in computers. Each position in the binary number system has only two possible
symbols,
or
1.
Therefore, binary arithmetic or the storage of binary

circuits
numbers is a "natural" for Below is an example

conversion.
which have only two possible states. of binary-to-decimal and decimal-to-binary
101011 (base 2)
1 1 1
1
? (base 10)
1
1
x 25 X 32
0x2*
x 16
1
1
x 23 x 8
x 22
0x4
1
x 2 x 2
x x
2
1
x x x
= = = =
1x8=8
1
x 16 x 32
32 43
101011 (base 2)
= 43
(base 10)
43 (base 10) 2
(43
|21
? (base 2)
1
1
2 2 2 2
2
|10 \_5
|
2
1
|J
43 (base 10)
101011 (base 2)
directly converting
it is
Although there are methods for

another, neither base being decimal,
from one base to
convenient to perform the conversion in two steps: from the original base to decimal, and from decimal
to the
new
base.
Chap.
11
BINARY ADDERS
161
Following
discussed.
is
a table of the values
to 20 in the various
number systems
Number systems
Base 10
Base 8 Base 5 Base
3
Base 2
2
3
2
3
2
3
2
10
11
10
11
4
5
4
5
4
10
11
100
101
12
6
7
8
6
7
10
11
20
21
110
111
12
13
22
100
101
1000
1001
9
10
11
14
12
13
20
21
1010
1011
102
110
111
12
13
14
15
22
23
1100
1101
14
15
16
17
24 30
31
112 120
121
1110
1111
16
17 18 19
20
21
10000
10001
32
33
22
23
122 200
201
10010
10011
34
20
24
40
202
10100
Binary Adders
The purpose of
this section is to illustrate
how
switching circuits can be
used to perform arithmetic functions, and secondarily, to show

switching circuits.
how
the
concept of symmetric functions can be useful in the design of electronic

In the arithmetic addition of two binary digits or "bits," there are four
possible combinations, as
is
shown
in Fig. 11-1.
device for adding two bits
called a half-adder (Fig. 11-2).
A
fo]
half-adder has two inputs, for the two

[71
A
Carryout
10
IT
1
Sum
01
[Tj
[T
î
o"
'Carry-out into next higher-order position

Figure 11-1
162
Chap.
11
Et
Figure
bits to
be added; and two outputs, one for the

for the
sum S and one
"carry-out"
into the
n-2
next higher-order position.
Observation of the four possible combinations

of two bits shows that the
sum
equals
only
when A
is
and
B = 0,
or
when A
and
B=
\.
Furthermore, there
a carry-out into the next
when A and B both equal 1. Boolean expressions for the sum and carry-out outputs of the half-adder can be written as follows
higher-order position only
= AB + AB C =AB
S
The
logical circuit to
implement these expressions
is
shown
in Fig. 11-3.
This circuit can be simplified by the manipulation of the Boolean expression

for the sum.
= AB + AB = (A + B)(AJ- B) = {A + B){A~B)
is
The
A B
simplified half-adder
shown
in Fig. 11-4.
AND
A B
AND
NOT
1
AND
1
"^
OR
AND
NOT
1
NOT
Half-adder
Figure 11-3
OR
AND
*5
Simplified half-adder
Figure 11-4
When two bits, A and B, are added in a position, and there is a "carry-in" C/ from the next lower-order position, three bits in all must be added. In
the addition of three bits, there are eight possible combinations (Fig. 11-5).
Ct
ra
1
fl
1
1
B
S
Figure 11-5
'
Chap.
11
BINARY ADDERS
163
Figure 11-6 shows an example of binary addition.

bits is called
A device for adding three
a full-adder
(Fig. 11-7).
full-adder has three inputs: A, B,
and
CT
and two outputs: S and
C.
_
=
B
790 c i
F
Figure 11-7
>co
*b
In the addition of three

or three of the bits equal
1.
bits,
the sum equals 1 only when The sum can be expressed as
exactly one
= ABCr +
S
ABC!
ABCj
+ ABCX
or in the symmetric notation as
= SXjABCj
1
The carry-out
exactly
into the next higher-order position equals

bits
only
when
two or three of the
equal
1.
The
carry-out can be expressed as
C = ABC T + ABd + ABCZ + ABC Z = AB + ACj + BCj

or in the symmetric notation as
C
By
= &<l$AdCi
the intuitive manipulation of the above expressions, particularly the symmetric notations, some economical full-adders can be obtained. If the
expression for
is
factored, the resulting expression will be
found useful
for implementation:
C = AB +
The
direct
CM + B)
S is
not very economical.
implementation of the expression for
However, realizing that a S 3 0il ABC z circuit can be obtained simply by the complementation of the C circuit, and that SI ABC , and S\ ti>a ABC r circuits are easily implemented by and and or circuits respectively, the following useful relationships can be utilized:
(1)
(2)
= (S ABC r S\ X3 ABCr) + SlABCr = S\ABCZ + SlABCr = SI,, ABCz S = (SlÂBCj + S\ABCx)S\ ABCx = (SlÂBCMSlÂBCr) = S\ ABCj
S
3 0il
it>l
i3
'
164
Chap.
11
Using the first of the two relationships above, the full-adder circuit in can be obtained. A full-adder can also be constructed with two half-adders and an or circuit (Fig. 11-9). Some key points in the circuit have been defined to aid in analysis. The general structure of a 4-position binary adder would appear as in
Fig. 11-8 Fig. 11-10.
BCT
AND
OR
C
NOT
AND
OR
AND
OR
AND
OR
Full
adder
Figure 11-8
C --AB A
B
Ci
--AB
+ AB
H
Co^CjiAB+AB)
S
--
OR
"^
Co
=
=
{AB + AB)CT +{AB +AB) Cx ABCj
+ ABCX + ABCj + ABCj

ABCj
5?>3
ABCj
AB+Cj (AB+AB) = AB + ACj + BCj = Sj f3

Figure 11-9
A*
Az
BA
1
Bz
r~i r~i
1
m
5
Cc7
'
F
Overflow
*
F
5
c7
t
F
s
'
H
c
'A
'O
5
i
'
'
'
'
5g
5*4
^2
5|
Figure 11-10
Chap.
11
BINARY-CODED-DECIMAL ADDER
165
Binary-Coded-Decimal Adder
To
further illustrate
how
logical circuits
can be used to implement
arith-
metic functions, a binary-coded-decimal (BCD) adder will be discussed. The BCD code differs from the straight binary number representation
in that in the
BCD
code each decimal

13, in straight
digit is binary-coded.
For example,
is
the decimal
number
binary
number
representation,
1101
whereas in the
BCD
1
code, 13
is
represented by
0001
the decimal digits
0011
and 3 each being binary-coded.

1001
(9).
In the
BCD code, the highest allowable binary representation is

may be added
Therefore, the highest two numbers that

(9
are 1001
1001
+ 9).
Also, there
Thus, the
may be a carry-in from the next lower-order position. maximum sum that can occur is 10011 (19). However, when the
(9),
sum
exceeds 1001
a correction must be made, as indicated in the
following table.
Uncorrected
Sum
Corrected
Sum
C
1
8421
C
i i
8421
0000
0001
2
3
0000
0001
0010
0011
"Mr~
0010
0011
4
5
0100
Correction
0100
0101
0101
Necessary
6 7
8
0110
0111 1000
1001
^
'
0110
0111
1000
1001
1 1 1 1
9
10
11
1010
1011
0000
0001
12
13
1100
1101
0010
0011
14
15
1110
1
1 1 1 1
0100
0101
mi
1 1 1
16
17
18
0000
0001
0110
0111
0010
0011
1000
1001
19
166

Analysis of the table shows that the correction should be
Chap.
11
the uncorrected
is
sum
contains an 8 and 2, or an 8 and 4, or

8's position.
made when when there

numerically
a carry-out from the
Analysis of the table also shows that

(6).
the corrected
sum can be obtained by adding 0110

1
This
is
equivalent to subtracting 1010 (10) and adding
0000 (16) (generating a
carry-out to the next higher-order position).
The
circuit in Fig. 11-11 illustrates
one decimal position of a
BCD adder.
Carry -in from next

lower- order position
Carry-out to next
higher-order position
ft
-Uncorrected
<
OR
AND OR
sum
I
Corrected
if
sum
54
52
Binary-coded-decimol adder
Figure 11-11
PROBLEMS
1.
Convert 111011 (base 2) to base
3.
2.
Convert 2601 (base
7) to base 6.
7.
*3.
4.
Convert 3333 (base 6) to base
Convert 13.8125 (base 10) to base
2.
4.
*5.
Convert 49.296875 (base 10) to base
12
Codes, Error Detection,

Error Correction
In this chapter, some of the more popular codes used for data representation will be discussed. These codes are used for such things as arithmetic
and storage and transmission of information. For example, on one of ten lines (Fig. 12-1) or by one of ten timed signals (Fig. 12-2) the 6 may be binarycoded as 0110, and represented with only four lines (Fig. 12-3) or with
processes
instead of a decimal 6 being represented by a signal
only four timed signals (Fig. 12-4).
Nonchecking Numeric Codes

First, various
schemes for coding the ten decimal
digits,
through
9,
will
be examined.
167
168
Chap. 12
"Clock"
0123456789
jTjTjTjT_r\j~u~Ln_n_n_
Figure 12-1
Figure 12-2
8
Clock
4 2
_n_n_ri_n_
Figure 12-3
Figure 12-4
BCD Code
One of
the
most
logical codes for representing the decimal digits
is
the binary-coded-decimal or
BCD
code.
Four
"bits"
(binary digits)
are
required to code the ten decimal digits.
/o
1 1 1 1 1 1 1 1 1 1
1
1
2
3
BCD
4
code
<
1 1
1
6
7
8
19
Excess-3 Code
The
BCD
code
may be thought
of as utilizing the
first
ten of the sixteen
possible combinations of four bits.
Another code, which

is
utilizes the
middle
ten of these sixteen combinations,
called the Excess-3 code.
Each coded
Chap. 12
NONCHECKING NUMERIC CODES

is
169
character
the binary equivalent of the represented decimal
number
is
plus three.
property of the Excess-3 code that makes
it
useful in arithmetic
that the 9's
complement of a decimal digit may be obtained by complementing all bits. For example, the coding for the decimal digit 1 is 0100. The 9's complement of 1 is 8, which, in the Excess-3 code, is 1011. Complementing all bits of 0100 results in 1011.
1
1
/o
1
1
1 1
2
3
1 1 1 1
Excess-3 code
4 5
6 7
8
1 1 1 1
1 1 1 1
,9
1 1 1
1 1 1 1 1
Cyclic
Codes
it
Sometimes
is
desirable to have a code in which successive coded
characters differ in only one bit position. Such codes are called cyclic codes,
and they are
particularly useful in analog-digital systems.

is
One
type of cyclic code
the reflected code.

is
A reflected binary code for
known as the Gray code. Note that except for the high-order position, all columns are "reflected" about the mid point; in the high-order position, the top half is all 0's and the bottom half all l's. This pattern can be used for a reflected binary code of any number of bits. A reflected code for three bit positions is enclosed by dotted lines for illustration.
sixteen decimal digits follows. This code
also
170
Chap. 12
1 1 1
1
1 1
1
1
1
1
Reflected
1
binary or
Gray code
If a reflected
BCD
code
is
desired, the first ten of the sixteen
combi-
nations could be utilized.
By choosing
that the 9's
the middle ten combinations, instead

is
of the
first ten,
a reflected excess-3 code
obtained.
An
advantage of the
complement can be obtained merely by complementing only the high-order bit, which is an ultimate in ease of complementation. Both reflected codes are shown below.
reflected excess-3
code
is
(0
1 1 1 1 1 1 1 1
1 1 1 1
2
3
0\
1
1 1
Reflected
4
5
1 1
BCD code
2
3
6
7
8
,9
4
5
1
1
> Reflected excess-3 code
1
1
6
7
8
9;
1 1
1 1
1
1 1 1
1
1
Chap. 12
ERROR DETECTION
AND CORRECTION
171
Error Detection
and Correction
None of the codes discussed so far can be error-checked. If bits become erroneously changed, say because of circuit failure, there would be no general way to detect the error because in these codes there are cases of
two coded characters
differing in only
one
bit position.
If even only a
became erroneously changed, another valid character could result, and there would be no way of knowing that the resultant character was not the intended one. The characteristics of error-detecting and error-correcting codes will now be discussed. The distance between two coded characters is the number of bits that must change in one character so that the other character results. For example, the distance between the coded characters 0011 and 1000 is three, since three bits must change to transform one of the characters to the other. The minimum distance of a code is the minimum number of bits that must change in a coded character so that another valid character of the
single bit in a character
code
will result.
:
there all of the codes discussed so far, the minimum distance was 1 was at least one case in each code in which a coded character could be changed to another by changing only one bit. The relationship between the minimum distance of a code and the
In
amount of
error detection or correction possible
is
as follows:
M-
=C+
D,
where
C< D
M = minimum distance of a code

C = number
of bits in error that can be corrected
D = number of bits in error that can be detected

Since no error can be corrected without being detected, C cannot be greater than D. All possible values for C and D for values of up to six are
tabulated
on the next page.

is
An
and
error-detection code
defined according to one less than the mini-
mum error it will not always detect.

triple errors,
Thus,
if
a code detects
all single,
double
and some or no quadruple errors, it is called a triple-error detecting code. This would still be so even if the code detected all quintuple errors. An error correction code is defined in the same manner, that is, according to one less than the minimum error it will not always correct. The relationship between the minimum distance of a code and the amount of error correction or detection possible may be more graphically
pictured
if
a "table-lookup" error detection system

is
is
considered. All the
valid characters in the code are stored in the table.
Each coded character
to be checked
compared with the characters
in the table. If a character in
172
Chap. 12
M
1
C D
2
3
1
2
1
4
1
5
1
4
3
2
6
1
2
5
4
3
the table
if
is found to match exactly, it is assumed that no error has occurred no character matches exactly, an error has been detected. Whether or not the error can be corrected depends upon the minimum distance of the
code, as will be seen.
In codes with a
minimum
distance of one, where
two valid characters
may
differ in
only one bit position, a single error in a character could
make
that character appear like another valid character in the code. This other
valid character
that
would be found in the table, and it would be falsely assumed no error had occurred. Thus, in codes having a minimum distance
of one, single errors can fail to be detected. Of course, if single errors can be undetected, multiple errors can be undetected also. In codes with a minimum distance of two, all coded characters must
differ in at least
two
bit positions. If there is
a single bit error in a character,
match any of those in the table; therefore, all single errors will be detected. Codes with a minimum distance of two are called single-error detecting codes. Errors in two or more bits might make the character match exactly some other valid character in the table, and therefore these errors would not be detected. In codes with a minimum distance of three, all coded characters must
the character cannot possibly
character with a single or double cannot match any character in the table; therefore, all single and double errors will be detected. Errors in three or more bits can result in another valid character and therefore these errors cannot be detected.
differ in at least three bit positions.
bit failure
Minimum
The key to
distance three codes can be used for single-error correction.

is
error correction
that
it
must be possible to
locate the bit or
bits in error. If a single error occurs in a
minimum
distance three code,

table,
the resulting character will not
match
exactly
any character in the
Chap. 12
ERROR DETECTION
AND CORRECTION
173
matching the correct character. It will not come within one bit of matching any other character. To accomplish the correction, the one bit that does not match is changed. In any code that can be used for correction, correction is "bought" at the expense of detection. If a minimum distance three code is used for
but
it
will
come
within one bit of
correction,
and a double error
occurs, the resulting character
may come
within a single bit of matching

there
is
some other character
in the table. Since
no way of knowing that a double error has occurred, it would be single bit was in error, and this bit would be erroneously "corrected." Thus, the error would be compounded, and an incorrect character would result. Minimum distance three codes thus will not detect
assumed that the
double errors if they are used to correct single errors. Summarizing, if minimum distance three codes are used for correction, the location of one bit in error can be determined and the error corrected. Errors in two or more bits can appear to the error correction system as a
single error,
and an erroneous correction (undetected

three
error)
can
result.
Minimum
The
distance
codes
are
often
referred
to
as
single-error
correcting codes.
characters in
minimum
and
distance four codes differ in at least four bit
positions. Single, double,
triple errors
can be detected with these codes,
cannot match any of those in the table. Errors in four or more bit positions can result in a character that matches some other valid character in the table, and thus these errors cannot
since the resulting character
be detected.
Instead of
minimum
distance four codes being used for triple-error
detection, they can be used for single-error correction with double-error detection. If a single error occurs, the resulting character will not
match
exactly any character in the table, but
it
will
come within one
bit
of matching
the correct character. It will differ from
all
other characters in the table

the one bit that
by
at least three bits.
The
correction
is
made by changing
does not match.
come within two bits of matching may also come within two bits of matching an incorrect character. There is, therefore, no way of knowing which bits are actually in error and so no attempt is made to correct double
character with a double error will
the correct character of the table, but
it
errors; they are simply detected.

If a triple error occurs in a character, the resultant character will differ
from the correct one in the table in three bit positions, but it may differ from some other character in the table in only one bit position. This one bit would thus be erroneously "corrected," and an incorrect character would result.
Summarizing,
if
minimum
distance four codes are used for correction,
the location of one bit in error can be determined and the error corrected.
174
Chap. 12
Double
errors can be detected but their location cannot be determined for
correction. Errors in three or
correction system as a single error,

error)
more bit positions can appear to the error and an erroneous correction (undetected
can
result.
Minimum
The
table
distance four codes are often referred to as single-error cor-
recting, double-error detecting codes.
lookup system was used as an aid in learning the concept of it relates to error detection and correction. In practice there are many schemes for accomplishing error detection and correction. As other codes are now examined, it will be seen how some of these schemes work.
minimum
distance as
Single-Error Detection
Minimum
Distance
Two Codes
single-error detecting code can be obtained by adding a redundant a nonchecking code. The redundant bit can be added to each character in such a way as to make the number of 1 bits in the character even. If this
bit to
is
done, the code
is
referred to as
an "even parity" or "even redundancy"
The redundant bit may make the number of 1 bits in

code.
codes.
8
instead be added to each character so as to
the character odd, giving an "odd parity" or "odd redundancy" code. Following are examples of both types of parity
JJ
i?
1
.0
1
1
1 1 1
1 1
2
3
1
1 1 1
1
4
5
1 1
1 1
1
1
6
1
1
1 1
1
1
7
8
1 1
m
The odd
Parity
BCD
Code
Odd Parity
BCD
Code
parity BCD code is sometimes preferred over the even parity code because an all-0 character is frequently undesirable if a gross circuit failure can change a character to all 0's, it is desirable that an all-0 character not be one of the valid characters in the code. However, a modification is frequently made in which the binary 1010 is assigned to the
BCD
Chap. 12
SINGLE-ERROR DETECTION
175
decimal 0; thus, the even parity character 10100 rather than 00000 represents
the decimal 0.
Characters in these codes are checked for the proper parity. If a single
it will be detected because the character will have the wrong Double errors will not be detected since the parity will check correctly. Another class of codes are the fixed-bit or m-out-of-n codes. In these codes there are n bits per character, of which m bits are l's. Such a code suitable
error occurs,
parity.
for representing the ten decimal digits
is
the 2-out-of-5 code, there being
two at a time ( 5 C 2 ). While any assignment of the ten 2-out-of-5 combinations to the ten decimal digits could be made, there are some that are more convenient to remember. It is not possible to correctly "weight" all ten combinations, but it is possible to properly weight nine of them. Two such weightings are shown: the 01247 code and the 01236 code.
exactly ten combinations of five things taken
2-out- of-5
1
Codes
1
4
1
7
1
2
1
1 1
1 1 1
1 1
2
3
1
1 1
1 1
1
1 1 1
1 1
1 1 1
1 1 1
4
5
1 1 1
7
8
1
1
1
1
1 1
Only the decimal is improperly weighted in both codes. There are two other 2-out-of-5 codes that weight nine of the ten combinations correctly, but both of these involve negative weights
-1,
2,
1,
3, 3,
4,
5
5
-2,
4,
popular 2-out-of-5 code that weights eight of the ten combinations is the 84210 code. All combinations are weighted correctly except the decimal and 7; the 8 2 combination is used for the decimal 0, and
properly
the 8
4 combination
is
used for the decimal
7.
This code
is
not very different
from the even parity BCD code and very little convert from one of these codes to the other.
logical circuitry is
needed to
1-bits.
Characters in fixed bit codes are checked for the correct number of
176
Chap. 12
Single errors will be detected since the

will
O's
1
number of
1 -bits
in the character
be one too many or one too few. Double errors involving two l's or two becomes a 1, and a will also be detected, but double errors in which a
becomes a 0, will not be detected. Another popular fixed bit code is the biquinary code. This is a seven-bit code made up of a l-out-of-2 group and a l-out-of-5 group. Again, there are ten possible combinations. Two possible weightings for this code are shown; the second one is sometimes called the "quibinary code" to differentiate it from the first one.
Biquinary Codes
5
1
1 1
4
1
2
1
1
1
1
1
1
1
1 1 1
1 1
1
1 1 1
1
1 1
1 1 1
1
1 1 1
1
1 1 1
1
1
1
1 1 1
An
operations
advantage of these codes is that the circuitry to perform arithmetic is quite economical. The quibinary code has the advantage of
more economical conversion to and from the
BCD
code.
Single-Error Correction
Minimum
Distance
Three Codes The construction and operation of a Hamming code

will
be used as an
example in the study of single-error correcting codes. First of all, in determining how many bits per character are required,
the bit positions are
etc.
etc.,
The
positions that are a
numbered sequentially from power of two, that is
left
to right as
1, 2, 3,
positions
1, 2, 4, 8, 16,
are reserved for check bits. All other bit positions

bits.
may
then contain
information
If
a single-error correcting numeric code is required, and the four-bit code is used for the information, seven bits in all would be required positions 1, 2, and 4 for check bits, and positions 3, 5, 6, and 7 for the four information bits. These seven bits can be labeled as follows:
BCD
Chap. 12
SINGLE-ERROR CORRECTION
177
12
C, C,
C4
2
,
The
values of the check bits
C C
1}
and
for each
coded character, are
determined as follows:
C C C
is is
is
chosen so as to establish even parity for positions chosen so as to establish even parity for positions chosen so as to establish even parity for positions
1, 3, 5,
2, 3, 6,
4, 5, 6,
and and and
7. 7.
7.
This pattern
in binary.
may be more
obvious
if
the position locations are written
(CO (C2 )
1 1
1 1 1
1
1
1 1
(Q)
1
3
2
6 2
7
1
c,
For an example, the check

be generated.
1
bits for the character for the
decimal 9 will
6 2
7
1
c,
C
7
;
therefore,
must be chosen so as to C must be a 0.

x
establish even parity for positions
1, 3, 5,
and
6 2
7
1
Cx
7;
C C
2
must be chosen so as to must also be a 0.

1
establish even parity for positions 2, 3, 6,
and
7
1
C c
x
4 o
178
Chap. 12
7;
C C
4
must be chosen so as to must therefore be a 1.
establish even parity for positions 4, 5, 6,
and
12
Ci C, 8
Q
1
is
1
therefore
The coded character
for the decimal 9
0011001
To
illustrate
how
a single error in
will
this
coded character can be detected

6.
and corrected, an error
be "made" in position
12
110
The
three parity checks, involving
11
C u C 2 and C4 are applied to the Based on the outcome of these checks, a binary number is developed, the C lt C2 and C4 checks corresponding respectively to the 1, 2, and 4 positions of the binary number. If the check shows even (correct) is entered in the corresponding position of the binary number; parity, a
,
,
character.
if
the check shows
odd
(incorrect) parity, a
is
entered.
The
resulting
binary
number
indicates the position in error; to correct the error, the bit

is
in the position indicated
changed.
In this example, the three parity checks are as follows
c i: C C4
2
:
1 1
1
i 1 1 1 1 1
even-
odd-
odd
~l
The C show odd
x
110=6
C
2
parity check
parity.
is
shows even
parity, while the
and
parity checks
The
resulting binary number,
110=6,
indicates that
is
position 6
in error.
To
correct the error, the bit in position 6
changed
from a 1 to a 0. Study of the construction of this code will show that the position of any bit in error is uniquely identified by the outcome of the
parity checks. If the resultant binary
indicated.
number
is
zero (000), no error
is
Only
single errors are detected
and corrected with
this code. Errors in
Chap. 12
ALPHANUMERIC CODES
179
two
bit positions will
error,
and a
error.
false correction will
appear to the error correction system as a single be made. Triple errors may also appear as
single errors
and be
falsely corrected, or they
may
"cancel out" and appear
as
no
If this code is used for detection only, all single and double errors will be detected; the error detection system checks only for the occurrence of an error, but does not try to identify a position in error and correct it.
correction.
The Hamming code is by no means the only type allowing single-error As long as the coded characters are chosen so that all pairs of
characters differ in at least three bit positions, single-error correction can
be accomplished.
Single-Error Correction with Double-Error
Detection
Minimum
Distance Four Codes

can be extended into
Hamming
single-error correcting codes
Hamming
by the addition of one more bit establishing even parity over the entire coded character. For example, taking the seven-bit character for the decimal 9, if an eighth bit is added to establish even parity over the entire character, this bit must be a 1, and the resulting character for the 9 is
single-error correcting double-error detecting codes simply
00110011
Four parity checks are made on the character: the C U C 2 and C4 checks, and the over-all parity check which can be called the P check. Any single error will be indicated by the P check showing odd parity. If the single error occurs in any of the first seven-bit positions, it will show up in some combination of the C u C2 and C4 checks, which will indicate the position in error. If the single error is in the eighth bit, the absence of any error indication by the C u C2 and C4 checks indicates that the bit in error is the eighth bit. The P check showing odd parity thus indicates that a single error has occurred, and that a correction should be made. If a double error occurs, the P check will show even parity. Even though the C U C2 and C4 checks indicate some position in error, the P check showing even parity indicates that a double error has occurred, and that no
,
,
correction should be made.
Alphanumeric Codes
"Alphanumeric" codes are those containing enough coded characters to code the ten decimal digits, the twenty-six letters of the alphabet, and
180
Chap. 12
A few examples of such codes will be described. code can be expanded into a six-bit code giving 64 possible coded characters, satisfying the requirement for an alphanumeric code. To make such a code into a single-error detecting code, a parity bit can be
often special symbols also.
The
BCD
added.
There are various m-out-of-n codes used for alphanumeric information.
For
instance, 3-out-of-8 codes (56 characters)
and 4-out-of-8 codes (70
characters) are used.
in
Alphanumeric Hamming single-error correcting codes require ten bits six information bits and four check bits, the check bits occupying positions 1, 2, 4, and 8. By adding an eleventh bit to this code, an alphanumeric Hamming single-error correcting double-error detecting code is
all,
obtained.
Cross-Parity
Sometimes a check is associated with an entire block of characters. For instance, at the end of a block of even parity BCD characters, an entire redundant character is added, the bits in this character being chosen so as
to establish even parity in each "channel," that
4-bit channel, the 2-bit channel, etc.
is,
the 8-bit channel, the
Parity checks
on
this
block of information are
made
it
in
two
directions
"vertically" for each character and "horizontally" for each channel. This
code
will detect all single,
double and
triple errors, or
may be used
as a
single-error correcting double-error detecting code.
Example:
Characters
95714382/?
8
1
1
4
2
1 1
Suppose that an error occurs in the "1"
bit
of the "3" character.
Chap. 12
PROBLEM
181
Characters
95714382/?
8
1
1
4
2
<
A
The odd vertical parity on the "3" character and the odd horizontal on the "1" channel locate the single error for correction.
parity
PROBLEM
1.
Each
is
digit
of a 4-digit decimal number
is
correcting double-error detecting
Hamming
code.
encoded in a single-error The coded information
received high-order digit
first
as follows:
2
x
7
1
c C
O ? ? ?
>
Q
l
4
1
P
1
1
>
Correct and decode
13
Sequential Circuits
have been discussed so far are called combinational circuits. In combinational circuits, the outputs are functions solely of the inputs: for a particular input combination there will either always be an output or else there will never be an output. The rest of this book discusses sequential circuits (Fig. 13-1). In sequential
The
circuits that
circuits,
time
is
an element, that
is,
sequential circuits have a
memory,
the outputs being functions not only of the present inputs but also of past
circuit states.
Sequential circuit inputs are also called primaries, and their states are represented by jc's. The states of sequential circuit outputs are represented
by
is
Z's.
The memory
characteristic of sequential circuits
is
realized
by
secondary circuit components that there is a time delay between their excitation and their resulting change of state. The states of the secondaries are represented by /s. Their
or secondaries.
excitations are represented
property of the secondaries
by
7's.
same as
its
present excitation; that
The next state of a secondary will be the is, a y will, after the time delay, become
182
Chap. 13
SEQUENTIAL CIRCUITS
183
Inputs <*g
(r r
>'
'
I'
>i
*Delay
Combinational
circuit
Secondaries-*
Delay
Y
v.
/
Delay
r
1
<
1
circuit
Schematic diagram of sequential switching

Figure 13-1
the
same as the corresponding present

In electronic sequential
circuits, the
Y.
Thus, the Y' s also represent the
next states of the secondaries. paths leaving the combinational circuit and feeding back into
secondaries are feedback paths

it.
The delay
feedback
may be
inserted or
may be
inherent in the feedback paths. Also,
all
paths must have gain, so that the circuits involved are self-sustaining;
therefore,
amplifiers
may have
is
to be inserted in the feedback paths if
inherent amplification
not already present.
In relay sequential circuits (Fig. 13-2), the secondaries are relays.

delay
is
The
inherent in the operate and release time of the secondary relays.
Coils
"\StSlSLr-
Inputs <
~\SlSSLr-
Outputs
Contacts
v
-
Q_Q_Q_/
iQPQy
\SlSlSLr~
yr xr -y
Secondaries
r r<s&suContact network
input
Schematic diagram of relay sequential switching

Figure 13-2
circuit

184
SEQUENTIAL CIRCUITS
Chap. 13
The
state
of a secondary relay
is
described by the operation or inoperation

is
of the contacts. The excitation of a secondary relay

energization or deenergization of the
coil.
described by the
Primary relays are under the direct control of the inputs, and are used
to
make a
multiplicity of contacts available for switching. Therefore, the
states
of the primary relays are considered as equivalent to the states of
the corresponding inputs.
Concept of Stability
When
that
is,
the excitation of a secondary
is
7 = y,
the next state will be the
the same as the present state, same as the present state, and
to be stable.
since the secondary will not
change
state, it is said
When the excitation of a secondary is not the same as the present state, that is, Y ^ y, the next state will not be the same as the present state, and
since the secondary will
If
change
is
state,
it is
said to be unstable.
= = =
1
and
and and
1
= 0, the next state will be 0, the secondary state will not

stable.
1, 1,
change, and the secondary

If y
Y= Y= Y=
the next state will be

is
the secondary state will not

the secondary state will

If
stable.
1,
y y
1,
the next state will be

is

If
unstable.
and
0, the
is
next state will be 0, the secondary state will

unstable.
easily visualized in
The concept of
(Fig. 13-3).
stability
can be
terms of relay operrelay
ation. Consider the coil
and a normally-open contact of a secondary The following assignment is made:
= y = Y=
contact unoperated
contact operated
coil deenergized
coil energized
7=1:
Assume, to
the
cr
\JU)SLn
r-yopen, the coil deenergized, and
Figure 13-3
start with, that the switch is
contact unoperated. At
this time,
7=
secondary
is
stable
Chap. 13
INTUITIVE
APPROACH TO SEQUENTIAL CIRCUIT SYNTHESIS
185
Now
assume that the switch

is
is
moved
to the closed position.

is
still
For a
brief
period of time, the coil
energized, but the contact
unoperated.
During
this time,
y
this time,
Y=
secondary
is
unstable
This unstable condition will terminate
when
the contact operates,
and
at
Y=
switch
is is
secondary
is
stable
Now assume that the

period of time, the coil
returned to the open position. For a brief

is
still
deenergized, but the contact
operated.
During
this time,
y
and
Y=
secondary
is
unstable
its
This unstable condition will end

state,
when
the contact returns to
normal
at this time, again,
Y=
secondary
is
stable
Basic Sequential Circuit Operation Refer to the two preceding schematic diagrams of sequential switching
circuits
(Figs.
13-1
and
13-2).
The
states
of the outputs (Z's) and the
secondary excitations (7's) are functions of the states of the inputs (x's) and the secondary states (y's). Note that the secondaries enter into their
own
control.
Assume a
sequential circuit to be stable.
change in input
states (x's)
not cause a change in the secondary excitations (7's). If a change in F's does occur, the corresponding secondary states (y's) will,
or
may
may
a delay, also change. If following the change in y's, the circuit is no further change will occur. If the circuit is unstable, another change in 7's will occur, followed by a change in the corresponding y's.
after
stable,
These changes
will
continue until a stable circuit
is
reached.
in time so
Successive input changes must be spaced far

that sufficient time
is
enough apart
all
allowed for the completion of
required secondary
action before another input change occurs.
Intuitive
Approach to Sequential
Circuit Synthesis
is
Before the formal method of sequential circuit design

intuitive
examined, an
be discussed. For the more simple sequential circuit requirements, the intuitive approach can be satisfactorily applied. For the
will
approach
more complex requirements, the
intuitive
approach can become more
186
SEQUENTIAL CIRCUITS
Chap. 13
difficult
to
apply,
and an optimum solution may not be obtained or
recognized except by the formal method of synthesis.
In the
occur.
first
A circuit is to have two inputs, *i

x
example to be considered, there is only one sequence that can and x 2 and one output, Z. Starting
,
from a condition of both inputs off, x will turn on first. While x is still on, x 2 will turn on, and then later turn off. Following this, x will turn off, the inputs returning to their original state. The output, Z, is to turn on when x 2 turns off, and the output is to remain on until x turns off. This sequence
r
x x
can be shown in a timing chart (Fig. 13-4). In a timing chart such as

2
*\
1 I
Fig.
13-4,
3
1
4
1
vertical division is allotted to
each input state
in the sequence. sents
Each
division actually repre-
*z
| I
some
interval of time during

exists.
corresponding input state

3-4
which the Although the
duration of these time intervals

Figure
1
convenient on the timing chart to
may vary, it is make all divi-
sions of equal length. A horizontal line is drawn through those intervals in which the corresponding input or output is
on; the absence of this line indicates the off condition. The intervals are
numbered
sequentially for reference.
and 4 on the timing chart of Fig. 13-4 indicate the sequential same input conditions exist during intervals 2 and 4; however, the output requirements are not the same, no output being desired during interval 2 but an output being desired during interval 4. When two or more intervals have the same input conditions but different output conditions, secondaries must be used to differentiate one interval from the other. In the example, therefore, secondaries must be used to differentiate between intervals 2 and 4. The intuitive approach is generally as follows:
Intervals 2
aspect of the circuit requirement: the
(1)
(2)
Determine which intervals must be differentiated from one another. Devise an operating sequence of secondaries that will accomplish
this differentiation.
(3) (4)
Design the secondary excitation Design the output circuits.
circuits.
It is
generally desirable to minimize the
number of secondaries required

and the
(step 2),
and to minimize the secondary
excitation circuits (step 3),
output circuits (step 4). It is, of course, most desirable to minimize the total circuit, and towards this end one should be aware that the secondary excitation circuits and output circuits may be able to share logic blocks or
contacts in
common.
Returning to the example, how can secondaries differentiate intervals 2 and 4? Inspection of the timing chart shows that if a secondary is off during interval 2 and on during interval 4, the two intervals will be differentiated.
Chap. 13
INTUITIVE
187
To
accomplish this secondary action, the secondary must turn on in interval turn off in interval 5. (A secondary that was on during interval 2 and 3, and off during interval 4 would also accomplish the differentiation. However, this secondary action would necessitate turning on the secondary in interval 4 5 3 2 1, and it is generally common design practice not to turn on any secondaries in interval 1 the *z "normal" or "power-on" interval.) Only one (Y) secondary is therefore required, and its operat,
ing sequence
is
incorporated
in
the
timing
chart (Fig. 13-5).
The secondary excitation Y is not normally shown on a timing chart and is shown here only for discussion purposes. Also, the time intervals A, B, C, and D are labeled for reference purposes only. Note the time delay between the excitation and change of
BCD
Figure 13-5
state
of the secondary.
assume relay implementation. The energization of the secondary relay is indicated by Y on the timing chart, and the operation of the relay is indicated by y. During the time interval labeled A, the relay is energized but unoperated
To
review the concept of
stability,
(y
=0, Y
=
At
1,
secondary unstable). During time interval B, the relay
is
Y=\, secondary stable). During time 1, energized and operated (y 1, Y 0, secondary interval C, the relay is deenergized but operated {y
unstable).
all
other times, the relay

stable).
is
deenergized and unoperated

required,
(y
0, Y = 0,
Now that it
secondary
has been determined that one secondary
is
and the
operating sequence of the secondary has been prescribed, the next step is the design of the secondary excitation circuit. Although, in such a simple
problem, the circuit can be designed by inspection of the timing chart, a map will be used for later comparison with the formal method of synthesis.
The map
panying
for the secondary excitation
Y is shown
in Fig. 13-6.
The accom-
table,
showing the
states
of the variables, their corresponding timing

is
chart intervals,
and
excitation Y,
given for reference.
Timing chort
00
y
01
ii
10
*\
xz y
inter vol
1;
5-D
2
1 i
1 1 1
Z-A Z-B
4
Y=*2+x<y
1
I
b-C
'Optional-never occur
Figure
3-6
SEQUENTIAL CIRCUITS
Chap. 13
tronic
The secondary excitation circuit is shown in Fig. 13-7, with both elecand relay implementation. Note that the secondary enters into its own control. Next, the output circuit is designed. The output or Z-map, accompanying table, and output circuit are shown in Fig. 13-8.
Note, in the total circuit (Fig. 13-9),
circuit
and output
how the secondary excitation have been combined in both implementations.
circuit
*\
xz
Y
Delay
/
AND
OR
*\y
*z
Figure 13-7
Timing
chart
00
>
01
1!
10
*k*z y
interval
1;
5-0
2
1
1 1
3-4 3-5
4
1
--
x xz y
s
b-C
\Optional-never occur
J
*\
*z
NOT
y-
AND
*i
*r
Figure 13-8
/,
xz
ll
V
Delay
r
AND
OR L_
*r
xz
^Z
AND
Figure 13-9
Chap. 13
INTUITIVE
189
Sometimes a secondary operating sequence cannot be achieved unless
more secondaries
In this example,
are used than at

it
first
appear necessary, as in Fig. 13-10.
is
necessary to differentiate only between intervals 3
and
5,
since these are the only
two
intervals with the
same inputs but with
different outputs.
Inspection of the timing chart shows that the differentiation could be achieved by having a secondary off during interval 3 and on during interval
5.
This secondary, therefore, must turn on in interval

is
4.
However,
interval
4,
4
it
the same as interval 2, and
if
the secondary
is
turned on in interval
would also turn on in interval 2 and be on in interval 3, and no differentiation would be accomplished. An attempt to have the secondary on during interval 3 and off during interval 5 would meet with the same result. Two secondaries are therefore required, and an operating sequence is shown in Fig. 13-11. y turns on in interval 3, and stays on during interval 4, making interval 4 differ from interval 2. y 2 turns on in interval 4, and stays on during interval 5, making interval 5 differ from interval 3.
x
Figure 13-10
Figure 13-11
As
sequential circuit requirements

less attractive;
become more complex, the
intuitive
approach becomes
involves the
one may not be sure that the solution
minimum number
is
of secondaries, or that the secondary oper-
ating sequence chosen
the one leading to the most economical circuit.
For example, one secondary might turn on in any one of four intervals, and turn off in any one of three intervals, giving twelve possible operating sequences for that secondary alone. Sequential circuits are generally more complex when alternative sequences are possible.
Example
A
13-12.
is
sequential circuit
is
to function according to the timing chart in Fig.
Any
of the four alternative sequences can occur. Only one secondary
required.
It is
suggested that for an appreciation of the difficulty in solving such
a problem intuitively, the reader solve this problem on his

referring to the solution in Fig. 13-13.
own
before
190
SEQUENTIAL CIRCUITS
Chap. 13
x xz
\
*3
/
Zs
Zz
x xz
\
y
*3
,
Zk
Zz
x
\
*2
xz
xi
xs
z,
y
Z\
Zz
*\
Zz
xz
xb
z<
xz x5
y
Zk
Zz
Zz
xz
xi
z,
Zz
Figure 13-12
Zz
x xz x%y
\
Figure 13-13
Flow Table
Preparatory to the examination of the formal method of sequential circuit design, the concept of the flow table will be discussed.
flow flow table describes the circuit action of a sequential circuit. unique table somewhat resembles a map, each entry being defined by a combination of variables. (In fact, in the synthesis procedure, secondary
and output or Z-maps, are obtained from the flow tables.) The variables consist of all of the inputs (x's) and secondaries (y's); the inputs define the columns of the flow table, and the secondaries
excitation or Y-maps,
define the rows.
There
is
these states
an entry in the table for every possible circuit state. Some of are stable, some are unstable, and some may be optional. For
Chap. 13
FLOW
state, the stability
TABLE
191
a given input
or instability of a circuit state
is
solely a
function of the secondaries.
The concept of the flow table and its relationship to the secondary excitation map, or F-map, is illustrated in Fig. 13-14. This example relates to the first example in the preceding section, and in particular to Figs. 13-15 and 13-16. Note the slight modification in the manner of drawing a map, the actual squares being omitted.
Referring
first
to the Y-map, the

*\*z
XiX 2 y
state,
= 000 entry represents a stable

since the present state of the
00
01
11
10
00
01
11
10
secondary, y, equals 0, and the excitation, or next state, of the secondary, Y,
equals
XiX^y
= 000).
(map entry for The XiX 2 y = 100 entry
3 -
1
Flow table
K-map
also represents a stable state, since
Figure 13-14
= F = 0. x&y = 101
Y=\.
an arbitrary
The Xj*^
111
and
entries also
represent stable states, since for these entries,
y=
In the corresponding flow table, each stable state entry

circled
is
denoted by
in each
number,
(1), (2), (3),
and ,
respectively, in the figure.
All unstable state entries will be uncircled numbers, the
number
case denoting the stable state in which the circuit action will terminate.
The XxX y
2
10 entry represents an unstable state since

1,
Y=
is
1.
Since
Y=
the next state of the secondary will be
1,
y = and and the next

will
circuit state will
be XiX 2 y
=
3,
111.
The x x 2 y
x
110 entry in the flow table
therefore an uncircled
(3).
denoting that secondary circuit action
terminate in stable state

x xz
x
XyXZ
01
11
00
'*/? 1 ' c
10
00
/,/2
01
01 01
*\*z
*\*z
10
00
01
1
2-5 3
00
y\/z
01
10
00 00
01
1
11
ll
10
4@ 6
1
10 ti1
00
01
1
1
0-1
1
y yz 00
{
00
01
11-
10
01
ii
10
11
ii<i
y|-map
11110 11
1-0
10 00 10
11
10
10
111
10
10
>2 _ma P
Flow table
Figure 13-1 5
Y- map
Figure 13-1 6
The x^x 2 y
= 001
Y = 0,
entry represents an unstable state, since
Y = 0.
Since
the next state of the secondary will be 0,
1 and and the
next circuit state will be 000.

therefore an uncircled
1,
The x x 2 y
t
001
entry in the flow table
is
denoting that secondary circuit action will termientries are optional, indicating either
nate in stable state d).
The x^x^y
= 010
and x x 2 y =011
x
192
SEQUENTIAL CIRCUITS
Chap. 13
that these circuit states can never occur, or that

circuit action will
we do not
care
what the
be
if
they do occur.
F-map in Fig. 13-14, let us examine For example, assume that the circuit is initially in stable state (l), and that the inputs change from the x x 2 = 00 state to the x x 2 = 10 state. The circuit will now be in stable state (2), and no secondary action takes place. Now assume that the circuit is in stable state (2), and that the inputs change from x^x 2 = 10 to x x 2 = 11. The circuit will now be in unstable state 3 (in this state, y = and Y = 1), and after a delay, the secondary state will change from y = to y = 1, circuit action terminating in stable state (). Or assume that the circuit is in stable state (4), and that the inputs change from x x 2 = 10 to x x 2 = 00. The circuit will now be in unstable state 1 (in this state, y = 1 and Y = 0), and after a delay, the secondary will change from y = 1 to y = 0, circuit action
Referring to the flow table and
possible circuit action.
some
terminating in stable state
(T).
example of a flow table with two secondaries is shown in Fig. 13-15, with the associated F-map. The F-map is actually a Fr map and F2 -map
all left-hand entries defining Y and all right-hand entries, maps were drawn separately, they would appear as in Fig. 13-16. As an example of some possible circuit action related to the above flow table and F-map, assume that the circuit is in stable state (6) and that the inputs change from x x = 11 to x x =01. The circuit will now be in
An
superimposed,
2.
If the
unstable state 4; in this state

(y 2
After a delay, y 2 will change from y 2 and circuit action will terminate in stable state (J).
1
2
is
stable (jj
= Y =
x
1),
but y 2
is
unstable
and
F =0).
to
y2
= 0,
Note that a change in input states is represented by a horizontal movement in the flow table, while a change in secondary states is represented by a vertical movement.
Optional states
occur, or because
transition.
may arise either because certain transitions can never we don't care what the circuit action is for a particular
14
Sequential Circuits
II
Synthesis of Sequential Circuits

In the synthesis of sequential
simplify
circuits, the circuit
requirements are
first
completely described in a flow table. Systematic methods are then used to
and modify the flow

Y) and output (Z)
table.
The flow
table
is
then transformed into
maps
that are read in the usual combinational sense to give the secondary
(
excitation
circuit expressions.
In more
(1)
detail, the steps in the synthesis
procedure are as follows:
A primitive flow
problem.
table
is
constructed from the
word statement of
the
(2)
The primitive flow table is tested for redundant states, and number of stable states can be reduced if redundancy is found.
table.
the
(3)
(4)
A mergedflow table is obtained by merging rows of the primitive flow A merger diagram is used to obtain an optimum merger. A secondary state assignment is made for the merged flow table. A transition map is used to determine the assignment.
193
194
SEQUENTIAL CIRCUITS
II
Chap. 14
(5)
A secondary excitation or
tation circuits are read
Y-map
is
obtained from the flow table with
secondary assignment, and the expressions for the secondary exci-
from the F-map.

obtained from the flow table with secondary
(6)
An
output or Z-map
is
assignment and the primitive flow table: The output state for each
stable state
is
identified in the primitive flow table,

is
and
its
location
in the
Z-map
identified in the flow table with secondary assign-
ment. Also, the actual state to state transitions are identified in the
primitive flow table, this information being used in the assignment
of output states for the unstable read from the Z-map.

(7)
states.
The output
expressions are
The
sequential circuit
is
drawn from the secondary
excitation
and
output expressions. Circuit hazards must be checked for and eliminated.
Each of these
circuits will
steps in the procedure for the synthesis of sequential
now be
individually examined.
Primitive Flow Table
The
first
step in the synthesis of sequential circuits
is
the construction
of a primitive flow table from the word statement of the problem. In a primitive flow table, each stable state (circled entry) is assigned a separate
row. This implies that a different secondary state
state,
is
assigned to each stable
although actual secondary state assignments are not

is
made
at this
time. It further implies that every input change
followed by a secondary
change in accomplishing a transition from one stable state to another. These implications apply only to the primitive flow table, which is the initial step in the synthesis. The primitive flow table is later modified, and
more than one stable state may be assigned the same row (secondary state), and transitions from one stable state to another may be accomplished by
input changes only.
In the primitive flow table, the output state for each stable state
is
recorded at the right in the corresponding row.
For study, the simple sequential

*\*z
12
jr,
00
01
11
10
circuit
problem, solved intuitively

13,
is
*z
Timing chart
- " - - 3 - - - -
2
in Chapter
Fig. 14-1,
summarized in
together with a related
primitive flow table.
The flow
table stable state
num-
bers are arbitrarily chosen to corre-
Primitive flow table
Figure 14-1
spond with the timing chart interval numbers. Since the fifth interval
Chap. 14
PRIMITIVE
FLOW
TABLE
\95
is
equivalent to the
first interval, it is
assigned the same number.
The op-
tional entries in the flow table indicate circuit states that can never occur.
The flow
table can be seen to represent a complete description of the required
circuit action.
Example:
sequential switching circuit
is
to have
two
inputs,
x and x 2 and one

t
,
output, Z.
is
to turn
2
on when x a turns on, provided

off.
Xj
is
already on.
at a time.
first
Z is to turn off when x

due to the
Only one input can change state Development of the primitive flow table can be started by
turns
con-
sidering the sequence for turning

entries are
on the output
(Fig.
14-2). All optional
restriction to single
(2),
changes of input.
If the circuit is in stable state
and the inputs change from

(5).
x^ =
2
10
to XjX 2
= 00,
1
the circuit can return to stable state

is
If the circuit
in stable state
(3),
and the inputs change from XiX t

state (2) (the
is
to
x^ =
Z=
10, the circuit
can return to stable

If the circuit
2
output changing
from
to
t
Z = 0).
in stable state
(3),
and the inputs
change from x x 2
stable state
11 to
x^ =01,
1.
the circuit must change to a

the inputs change from
().
new
,
11,
for which
Z=
, and
x x2
x
=01
the
1
to
x x2
x
If the circuit is in
stable state
circuit
(2),
and the inputs change from XiX 2

state
= 01
to
x x2
x
Z = 0).
to
( tne
output changing from

is
= 00, Z=
x x2
x
to
in
The
primitive flow table at this stage of development
shown
Fig. 14-3.
, and
the inputs change from
= 00
= 01
x^ = 01,
x x2
x
the circuit must change to a
new
stable state
(5),
for which
Z=0.
If the circuit
is
in stable state
(5),
and the inputs change from x x 2

x
to
= 00,

t
0.
stable state
circuit
(5), and the inputs change from x x 2 =01 to XjX 2 must change to a new stable state (6), for which Z = 0.
11, the
jr,*2
00
*1*2
*l*2
01
11
10
00
II
01
11
10
2
00
01
10
3
(3)2
3
5-2 - 3 3
Figure 14-2
Figure 14-3
Figure 14-4
96
SEQUENTIAL CIRCUITS
II
Chap. 14
(6),
and the inputs change from

(5).
jCjJCg
to XiX 2
= 01,

x
x
stable state
circuit
(),

in Fig. 14-4.
and the inputs change from x x 2 = 11 to x x 2 = 10, the state (2). The completed primitive flow table is
shown
Construction of the primitive flow table forces the logical designer to completely account for all possible circuit action. There may have been
designer had not initially considered. However, in the construction of the flow table, these sequences are called to his attention, and he must decide what the circuit action will be when
certain input sequences that the
these sequences occur (or else determine that the circuit action
is
optional).
"
Power-on
"
Output State
specifications of a sequential circuit
The output
may be complete
is
with
regard to the circuit action required once the circuit
"in operation,"
but the output state when the power is first turned on may be arbitrary. For example, consider the following circuit requirement: A sequential circuit has two inputs, x and x 2 and two outputs, Z and Z Only one input can change at a time, and the input state x x 2 = 1 1 can
x , 1
never occur.
When
x x2
x
= 01
or
10,
Z(Z 2
= 00
Z Z = 01
X
When
x x2
x
= 00, 00,
the
following
x x2
x
= 01, =
10,
When
x x2
x
following
x x2
x
ZZ
X
10
If
x^x 2
= 00
when
power
is first
turned on, what should the output

or
be?
It
may be
that either output
Z Z 01
X
ZZ =
X
chosen as the "power-on" output
state. If so,
10 may be arbitrarily 2 assuming that stable state

tables in
is
the power-on stable state, either of the
two primitive flow
Fig. 14-5
would be
satisfactory.
*1*2
*\*2
00
01
11
01
10
00
01
11
10
3
1
Z,ZZ
10
00
10
4 01 4
3-4
1
Z Zz
y
10
" 00
00
3 2- " 00 - - 00
4 01
- 5 00 4 5 01 (2) 4 5 10 (D 2 (4) - - 00 3 - - l 00
4
Figure 14-6
z,z2
Figure 14-5
Chap. 14
ELIMINATION OF REDUNDANT STABLE STATES
197
If
preferred
one of the two output conditions, and specified as the power-on output
another possibility
state. If so,
is
Z^ = 01
state,
or
ZZ =
X
10,
is
only one of the above
flow tables would, of course, be satisfactory.

Still
that
Z Z = 00 may be desired as the power-on

X
output
the primitive flow table in Fig. 14-6
would describe the
circuit action.
out of the
state
(l).
first
Note that once row of the flow

(T)
circuit action starts, causing a
movement
Unless
table, the circuit will never return to stable

state.
Stable state
thus serves only as a power-on stable
they are specifically required, such additional stable states should be avoided,
since they generally lead to less economical circuits.
Elimination of
Redundant Stable States

it is
In the construction of the primitive flow table,
possible to introduce
more
stable states than are needed. This

it
is
sometimes done inadvertently
because
is
not apparent that two or more stable states are actually
equivalent. If
two stable states are equivalent, one of them is redundant and may be removed, eliminating a row of the primitive flow table. Once
synthesis
is
the primitive flow table has been completed, then, the next step in the
to test for any redundant stable states that
if:
may be
present.
Two
(1)
stable states are equivalent
They have the same input
state (they are in the

state,
same column),
and
and
(2) (3)
They have the same output
For each possible input change there is a stable states to the same or equivalent states.
1
transition
from these
Example
In
f
equivalent.
are (2) and They have the same input state, x x 2 = 01 they have the same output state, Z Z % = 10; and since the remaining entries in both the second and fourth rows are identical, column for column, for each possible
he primitive flow table of Fig. 14-7, stable states

x
2-6 00 4-6
y
00
01
II
10
-,
*\*z
00
01
11
10
10
10
10
6 01
2-6 2-6 1
7 7
00
10 10
6 01
1
Figure 14
Figure 14 -8
198
SEQUENTIAL CIRCUITS
II
Chap. 14
input change there
is
a transition from these stable states to the same

it is
state.
customary to eliminate the one with the higher number. All occurrences of the higher number are replaced by the lower number, and the row containing the higher-numbered
stable states are equivalent,
stable state is eliminated entirely.
When two
dundant
stable state
removed
is
The primitive flow shown in Fig. 14-8.
table with the re-
Example
2:
In the primitive flow table of Fig. 14-9, the equivalence of stable states
and (4) can be immediately established as in Example 1. Stable states and (3) have the same input state and the same output state, and therefore the first two criteria for equivalence are satisfied. Examination of the first and third rows shows that the remaining entries are identical, column for
(2)
column, except for the x^ 2 01 column. In this column, there the first row, and a 4 in the third row. The equivalence of stable
is
a 2 in
states
(D
(3)
and and
(3),
(4).
dependent upon the equivalence of stable Since the equivalence of (2) and (J) has been established,
therefore,
is
states (2)
and
are equivalent also.

*)*2
The reduced
primitive flow table
is
shown
*\*z
in Fig. 14-10.
00
01
11
10

2
1
z,z2 6 00
10
00
00
01
10
01
1 1
t-yt-i
7 7
00
10
10
00
10
2-6
1
Z,Z2
00
10
3-5 5
4-6
1
6 01
1
5 5
00
10
6 01
6 01
1 1
Figure 14-9
Figure 14-10
Figure 14-11
Example
In the primitive flow table of Fig. 14-11, the equivalence of stable states
(1) and (3) is dependent upon the equivalence of stable states (2) and 0. The equivalence of (2) and , however, is dependent upon the equivalence of (D and (3). If (D and (3) are made equivalent and (2) and (4) are made equivalent, analysis will show that the circuit action is the same as that prescribed by the original flow table. The reduced primitive flow table for this example is identical to that in Example 2. Equivalences can thus be made when they are interdependent upon each other, or when they are dependent upon other established equivalences. The requirements for equivalence can, in fact, be stated in another, and
Chap. 14
ELIMINATION OF REDUNDANT STABLE STATES
199
perhaps more directly usable, way: two stable states with the same input
state
and
the
same output
state can be
made
equivalent unless the equivalence
depends upon a nonequivalence.

It follows that an efficient approach in testing a primitive flow table for redundant stable states is to establish all nonequivalences (within a column) first; all pairs of stable states, with the same input state and the same output state, not established as nonequivalent can then be made equivalent.
Example 4
illustrates this
approach.
Example
4:
Examination of the primitive flow table of Fig. 14-12 shows that there (l), , and @; between (D, (7), and (9) between (), (6), and (fl) and between () and (). Immediately established nonequivalences (within a column) are between stable states ()
are possible equivalences between stable states
; ;
and
(16),
and between
(8)
and
(Tfi).
00
01
II
10
263
4
z,z2
758
1
17
2
00
1
I
6 01
00
10
3 10 3
12
1
12
12
@
To
be helpful
:
17 6
11
1 1
10
I
I
01
I
10 10
00
Figure 14-12
aid in establishing further nonequivalences, a tabular approach can
A table is constructed with a row for each possible equivalence, and a column for each possible equivalence and established nonequivalence. All nonequivalences are circled for identification. Check marks are placed
in the proper locations of the table, a check
equivalence in the corresponding
row
is
mark indicating that the dependent upon the
possible possible
equivalence or established nonequivalence in the corresponding column.
The table for Example 4 is shown in Fig. 14-13. The nonequivalences 3-10 and 8-10 are circled for
identification.
Any
200
SEQUENTIAL CIRCUIT
II
Chap. 14
stable states
whose equivalence
is
dependent upon a nonequivalence must

(5)
themselves be nonequivalent. In Fig. 14-13, the check marks in the 3-10
column
establish that the stable states

(5)
and
(6)
are nonequivalent,
and
that the stable states
(Q) H2
1-4
1-12
@ are nonequivalent. The 5-6 and 5-11 column @) @> (Q) (j-j) 9 @) (P!)
and
7'
6-11
3' 8
(8-j)
/
/
/ /
4-12
2-7
2-9
7-9
y
/
/ / / / / / /
Figure 14-13
5-6
5-11
6-11
/ / / /
/ / / /
3-8
designation are therefore circled.

*\*'<
these
01
II
00
10 3 3
4
1
Z^Z^
2-7
are
6
5
00
1
The check marks in and are nonequivalences. These column designations also circled, and the check marks in these four
two columns
establish that 1-4, 2-9, 4-12,
7 7 7 2
6
5
3 3 10
3
01
(0
1 t
00
10

6 6
columns indicate the nonequivalence of 2-7, 2-9, 1-4, 4-12, 5-6, and 5-11. These nonequivalences have already been established, and since no new nonequivalences are found, the
procedure
is
completed. All
10
I
1
(z)
column designations indicate equivalences that can be made: 1-12, 7-9, 6-11, and 3-8. The primitive flow table can therefore be reduced
uncircled
to eight
Figure 14-14
rows
(Fig. 14-14).
Pseudo-Equivalence
Two stable states may be equivalent in both of the following conditions

(1)
all
respects except for
one or
For a given input change, there

second stable state
is
is
a transition from one of these
stable states to a prescribed state, whereas the transition
from the
optional.
(2)
An
scribed,
output state associated with one of these stable states is prewhereas for the second stable state, the corresponding
is
output state
optional.
Chap. 14
PSEUDO-EQUIVALENCE
20'
If either of the
above conditions
exists,
the two stable states are said to
be pseudo-equivalent, and can be considered as equivalent. These conditions

are illustrated by the following
two examples.
Optional Transition
*\*z
00
01
11
.10
7 7
1

Stable states
x
3 3
4 00 4 00
^
~"
00
01
10
A?z
00
^-
Figure 14-15
and (2) are pseudo-equivalent, since an input change x x 2 = 11 results in a transition from stable state (1) to (5), whereas the transition from stable state (2) is optional. Since the optional entry can be replaced with a 5, stable states and (2) can be made equivalent.
(T)
from x x 2
00
to
Optional Output
*\*z
00
01
10
00
01
II
10
(2)
00
Z ZZ
K
00
0Figure 14-16
In this example, stable states

stable state
(T),
(T)
and
(2)
are pseudo-equivalent, since for

state
(),
Z =
2
0,
whereas for stable
is
optional. Since
the optional entry can be replaced with a 0, stable states
and
(2)
can
be made equivalent.
A
states
stable state
may
be pseudo-equivalent to two or more other stable
which themselves are nonequivalent.
Example
*\*z
00
01
10
4-7 566
6
1
Figure 14-17
202
SEQUENTIAL CIRCUITS
II
Chap. 14
Stable states CD
and
()
are pseudo-equivalent, stable states
(2)
and
(3)
are pseudo-equivalent, whereas stable states
and
(2)
are nonequivalent.
The
three possible reductions are
shown
in Fig. 14-18.
*\*z
*\
xz
01
II
00
01
II
10
00
10
4 5 L =
7
00
01
11
10
6 6 6
467 567 1
state reduction
Figure 14-18
In the
last reduction, stable state (3)
and
(2)
since the optional entry in the

5.
can be made equivalent to both (T) x x 2 = 01 column can be replaced

x
with a 4 or
Although not the case
in the
example above,
maximum
may
require that a stable state be
made
equivalent to two or
more other
stable states
which themselves are nonequivalent.
Example:
*\*z
00
01
It
10
*\*z
(2)5
00
01
10
-7
3
or

3 2
-(6
-
and
(3)
5or 6
5
Figure 14-19
Figure
14-20
Stable states
(5)
(2)
are nonequivalent,
and
(5)
(6)
are also nonequivalent. Stable states

if stable states
(7),
and therefore stable states (2) and (4) can be made

(3)
equivalent
of
and
in turn,
(3)
the equivalence of
and can be made equivalent; the equivalence and 0; dependent upon the equivalence of dependent upon the equivalence of and
(7)
is is
(6)
and
of
(7);
(2)
and the equivalence of (6) and (7) is dependent upon the equivalence and . The following equivalences can therefore be made
Chap. 14
PROBLEMS
203
@= =
the
=
=
(7)
and the reduced table appears as in Fig. 14-20. Note that the 4 and 7 in first row can each be replaced with either of two equivalences. A flow table with pseudo-equivalences is also called an incompletely
specified flow table. In general, reduction of such a flow table to the mini-
mum
number of rows can involve
trial
and error procedures
(see Related
Literature section).
PROBLEMS
1.
A sequential circuit is to have two inputs,

The
inputs represent, in binary, the
*i and x 2 and one output, Z. through 3. numbers

,
x x2
x
Number
representation
00
01
1
10
11
2
3
If a
is
change in input increases the represented number by one, the output
to turn on, if not already on. If a change in input decreases the
represented
number by
is
one, the output
is
to change state.
No
other
input change
possible.
2.
to cause any change in output. All input changes are
Draw
a primitive flow table for this circuit requirement.

x ,
and x 2 and one output, Z. through 3. If a change numbers in input increases the represented number, the output is to turn on, if not already on. If a change in input decreases the represented number,
A sequential circuit is to have two inputs, x

represent, in binary, the
The inputs
the output
sible
is
to turn off, if not already
off.
All input changes are pos-
except that both inputs will never turn off simultaneously.
Draw
a primitive flow table for this circuit requirement.

*3.
A sequential circuit is to have two inputs,

If the
if
x and x 2 and one output, Z.

t
number of
inputs that are on increases, the output

the
is
to turn off,
not already
off. If
numbers of inputs that are on decreases, the
is to turn on, if not already on. No other input change is to cause any change in output. Both inputs will never turn off simultaneously; otherwise, all input changes are possible. Draw a primitive flow table
output
for this circuit requirement.
204
SEQUENTIAL CIRCUITS
II
Chap. 14
4.
Draw
a primitive flow table equivalent to Fig.

states.
14-21,
but with no
redundant stable
x^x z
00
01
11
10
11
9
7 8
10
10
39I1
1
9 8
12
10
011
3
1
4
6
14 8
2
10
Figure 14-21
*5.
Make
all
possible equivalences (Fig. 14-22)
and draw a primitive flow
table with a
minimum of stable
X\X Z
states.
00
01
11
10
!
Q) 571 48"
1
9
8 7
(g)
161 141 14 8
1
(6)
10
(fj)
Figure 14-22
6.
Test the primitive flow table of Fig. 14-23 for any redundant stable states
that
may be
present.
1 1
Chap. 14
PROBLEMS
205
x xz
y
00
01
11
-35 -47
1
10
<-\
*-z
00
00
1 1
2
1
" 8 9
"

4
3
7 6
2
1
3 10
4
10
01
10
10
Figure 14-23
15
Sequential Circuits
Merged Flow
Table;
Merger Diagram
After testing for and eliminating any redundant stable states, the next
step
is
to
merge rows of the primitive flow table and obtain a merged flow
is
table.
In the primitive flow table, each stable state

all
assigned a separate
between stable states involve both an input change and a secondary change. Merging reduces the number of rows in the flow table by placing more than one stable state in the same row. Transitions between stable states in the same row are realized by input changes only. The advantage of merging is that by reducing the number of rows in the flow table, the number of required secondary states is reduced, and often, as a consequence, the number of required secondaries is reduced also. These reductions generally lead to greater circuit economy. It should be noted that merging reduces the number of rows of the flow table, but it does not reduce the number of stable states. The rules for merging are as follows
transitions
row, and
206
Chap. 15
MERGED FLOW TABLE; MERGER DIAGRAM
207
(1)
Two
flicting state
more rows can merge if, within the rows, there are no connumbers in any column. For example, two rows can merge if each column contains either two like state numbers, one 's. or two state number and a
or
(2) All state
numbers in the merging rows are written in the respective columns of the merged row. If a state number is circled in one of the merging rows, it is circled in the merged row, retaining the stable
state designations.
The output states for each stable state, recorded in the primitive flow no way affect merging, and are not repeated in the merged flow table. The primitive flow table is referred to later for this output information.
table, in
Example:
The merger of the two rows
in Fig. 15-1
is
shown
in Fig. 15-2.
x *z*%
\
000 001
Oil
010 110
3
111
101
100
5
Z
1
*\
xZ x i
Oil
4 4
000 001
010 110
3
111
101
100
Figure 15-1
Figure 15-2
Generally, there
table,
is
more than one way of merging the rows of a flow
and the choice of mergers can affect circuit economy. In obtaining
an optimum merger, a merger diagram is useful. To construct a merger diagram, the stable state numbers, are arranged in a basically circular array. The numbers are used here only to identify the rows of the primitive flow table. If, in the flow table, two rows can be merged, the corresponding stable state numbers in the merger diagram are connected by a line. All pairs of rows are examined for a possible merger, and after all connecting lines have been drawn, the merger diagram is
inspected for the
optimum way of merging. The aim,
in general,
is
to
merge so as to obtain the minimum number of rows

table.
in the
merged flow
A
Fig.
and
its
associated merger diagram are
shown
in
15-3. Referring to the

1
merger diagram, note that row 2 can merge

1
and 3 cannot merge with each other. merge into one row, and a choice 1, 2, must be made between the merger of rows 1 and 2 and the merger of rows 2 and 3. A merger of rows 1, 2, and 5 cannot be made for the same reason, and a
with row
3,
or row
but that rows
Therefore, rows
and 3 cannot
all
208
SEQUENTIAL CIRCUITS
Chap. 15
*1*2
00
01 5
11
10 2
6 6
1 1
o1
"A \
*1*2
00
01
II
10
2
dX.
2 2
1
@4
1
(5) 4
^3)
Merger diagram
@ @
6
2
Merged flow table

Figure 15-4
Figure 15-3
choice must be
made between
the merger of rows
and 2 and the merger
of rows
and
5.
1 and 5, 2 and 3, and 4 and 6 result in a three-row optimum. A merger of rows 1 and 2 would not be would leave rows 3 and 5 unmerged, and the resulting
The mergers of rows

flow table, which
desirable, since
it
is
flow table would contain four rows.

table
is
The optimum three-row merged flow
shown
in Fig. 15-4.
Rows 1, 2 and 6 can all merge one row, as can rows 3, 4 and 5. Note that a four-row merger between rows 2, 3, 5 and 6 is not possible, since rows 2 and 5 cannot merge and rows 3 and 6 cannot merge.
Figure 15-5 illustrates three-row mergers.
into
00
01
11
10
z
1
00
01
11
10
5 5
"
2
3 - -
@@
5
Merger diagram
Merged flow table
Figure 15-5
Figure 15-6 is an example of a four-row merger. Rows 1, 2, 5, and 6 can merge into one row, and there is also a two-row merger between rows 3 and 4. Often there may be more than one way of obtaining a minimum-row merger. In Fig. 1 5-7, there are four different ways of reducing to a four-row merged flow table. When there is more than one minimum-row merger, all of them should be considered, since there is no way of knowing at this stage of design which merger will result in the most economical circuit. Once the merged flow table has been obtained, the next step is the
all
Chap. 15
CYCLES
209
2) 3)
12/34/5/678 12/34/56/78
14/23/5/678
[6)
(5)
14/23/56/78
Four possible mergers to four rows
Figure 15-6
Figure 15-7
this,
assignment of secondary states to the rows of the flow table. Following a secondary excitation or 7-map is obtained from the flow table with
secondary assignment. The expressions for the secondary excitation circuits are read from the 7-map. Before these steps are examined, however, the
concepts of cycles, noncritical races, and critical races should be understood.
Cycles
Until now, the discussion of unstable states has been limited to the case
in
will
which following a secondary change a stable state is reached. The case now be considered in which an unstable state leads to another unstable state. Such a succession of two or more secondary changes is called a cycle. An example of a cycle is illustrated in the x x 2 00 column of the flow table and associated 7-map in Fig. 15-8. "1*2 "1 "2
x
In a flow table (Fig. 15-8)

to
all
/,/2
00
01
11
10
/,/, 1 c
-
00 00 00
01
01
11
10
unstable state numbers correspond

the stable
state
all
00
01
11
1)
!
that
will
be
00
01
11
01
reached
when
secondary circuit
action terminates.
to indicate
Arrows are used the movement from an
10
11
10
10
Flow table
Cycle
y-map
unstable state to another unstable

state.
The absence of an arrow Figure 15-8 unstable state leading from an number indicates that the next state is the corresponding stable state. In this flow table and associated 7-map, if the circuit is in stable state (2), and there is an input change from x x 2 = 01 to 00, there will be a cycle of
x
three
successive
secondary changes before stable state
is
reached:
y y2
x
=
=
10 tO 11 tO 01 tO 00.
(3),
and there
x x2
x
10 to 00, there will be a cycle of only

stability is
is an input change from two successive secondary
changes before
reached: y x y 2
11 to 01 to 00.
is
, and there
an input change from
210
SEQUENTIAL CIRCUITS
III
Chap. 15
XiXz
= 01
to 00, stable state

x
is
reached following the single secondary
change from y y 2
=01
to 00.
Races
In the cycles and single secondary changes discussed so far, each secondary excitation differed from the present secondary state in only one variable, that is, only one secondary was unstable at a time. If more than one secondary is unstable at a time, a race condition is said to exist. An example of a race is illus<*i
*2
11
jt,
xz
01
11
trated in the
10
00 01
00
01
11
10
00
the flow table

in Fig. 15-9.
If the
x^ 2 = 00 column of and associated Y-map
oo 00 01 00
11
circuit is in stable state
00
11
10
10 00
Flow table
J'-
map
and there is an input change from x x 2 =01 to 00, the excitation, 7j Y2 = 00 will differ from
(2),
x
Non-critical race
the secondary state,
Figure 15-<9
two
variables,
y y2 = 11, in and both secondx
aries will attempt to change state However, the physical response times of the secondaries may differ, and one secondary may respond faster than the other. If both secondaries respond at the same time, the next secondary state will be y y2 00, and no further secondary action will take place since this state is stable. If y responds first, the next secondary state will be ^1^2 =01. This state is unstable, and a further secondary change to the stable y y 2 = 00 state will take place. If y 2 responds first, the next secondary state will be y y 2 = 10. This state is unstable, and a further secondary change to the stable y y 2 = 00 state will take place. In the example above, no matter what the outcome of the race (y responds first, y 2 responds first, or y\ and y 2 respond together), circuit action terminates in the desired stable state. Such a race is termed noncritical. A more complex example is shown in Fig. 15-10. If the circuit is in stable state (2), and there is an input change from x x 2 = 01 to 00, there will be a race condition from the yiy 2 y 3 = 111 state to the y y 2 y 3 = 010 state. Depending upon the outcome of the race, the next secondary state may be y y 2 y 3 =010, 110, or Oil. The 010 state changes to the stable 000 state. The 110 state cycles through the 100 state to the stable 000 state. The 011 state attempts to change to the 000 state: another race condition, the next secondary state being 000 (stable), 010 or 001. The 010 and 001 states both change to the stable 000 state. Therefore, no matter what
at the
same
time.
the outcome of the races, the circuit action eventually terminates in stable state y x y 2 y 3 000, and the races are thus noncritical. All possible circuit
Chap. 15
RACES
211
*\*z
00
01
11
10
00
01
11
10
000
001
000 000
001 000
011
011 000
010
110
111
010 000
1
10 100
11
Flow table
010
111
101
101
100
100 000
K-map
Figure 15-10
001
actions are illustrated diagrammatically at the right in Fig. 15-10.

If a race
A\ A z
A\ A z
00 00
01
11
01
11
10
/,/ 2
00
01
11
10
can terminate in any of

stable
it
two or
states (or
more nonequivalent
can endlessly
is
00 00
01 01
cycle),
is
(D
11
00
11
said to be a critical race.

ple of a critical race
An
exam-
10
10
00
K-map
illustrated in
Flow table
Critical race
the
xx
x
table
15-11.
column of the flow 2 and associated Y-map in Fig.

(3),
= 00
Figure 15-11
and there
is
an input change from

x
= 01 to 00, there will be a race condition from the y y = 11 state to the y y = 00 state. Depending upon the outcome of the race, the next secondary state may be y y = 00, 01, or 10. If both secondaries respond at the same time, the next secondary state will be y^y = 00 (stable state ). If y responds the next secondary state will be y y = 10, followed by a further secondary change to y y = 00 (stable state ). If y responds
x x2
t
first,
first,
the next secondary state will be
y y =01
x
(stable state
(2)),
which
is
not the circuit action desired.

dictable,
The behavior of a circuit with a critical race condition is thus not preand critical races therefore represent improper design and must
1
be avoided.
tial circuit
However, noncritical races and

design, but they
cycles are not only permissible in sequen-
may
be desirable.
critical races
Cycles
may be
used to avoid
or to introduce desired addi-
tional time delays in secondary transitions. Noncritical races are useful
where short transition times are
desirable. Cycles or noncritical races
may
lead to the most economical circuit in a given case.

Critical races may be avoided if one secondary, inherently or by the insertion of additional delay, responds slower than another. In the discussion that follows, however, it will be assumed that the relative response times are indeterminate.
212
SEQUENTIAL CIRCUITS
III
Chap. 15
Secondary State Assignment and Y-Map

The next two steps in the synthesis of sequential switching circuits are (a) making secondary state assignments to the rows of the merged flow table and (b) obtaining a 7-map from the flow table with secondary assignment and reading the secondary excitation circuit expressions from the 7-map. It is advantageous to consider these two steps concurrently. will always be placed in the first row of the Arbitrarily, stable state and flow table, and will be assigned the all-0 state: all input states equal all secondary states equal 0. The all-0 secondary state will thus always be
assigned to the
first
row.
two-row flow table presents no secondary assignment problems. One for the first row, and secondary is required, with the assignment y =
for the second row. In
making secondary assignments
to flow tables
of three or more rows, we cannot assign secondary states arbitrarily, or critical races may result. For these flow tables, a transition map is helpful
in deriving assignments with the
minimum number of
variables,
and that
are free of critical races.
Transition
Map
are the variables of a transition
The secondaries
map
representing a secondary state.

are
possible;
A
map, each square in the With two secondaries, four secondary
states
with three secondaries, eight secondary states are

possible,
01
11
y.
/,
y /z 00
and so
forth.
10
variable transition
Fig.
Two- and threemaps are shown in
15-12.
As a first
Three-variable
transition
step in determining a secon-
Two-variabie
transition
dar V assignment, each row in the merged

flow table
is
map
Figure
1
map
assigned a letter reference.
5-1
The assignment of a secondary state to a row in the flow table is associated

letter in the
with the entry of the row reference

the transition
corresponding square of
map.
:
In the assignment of secondary states to the rows of a merged flow table, the possible row-to-row transitions must be examined if there is a
transition between
two particular rows, the secondary states for the two rows must either differ in only one variable, or if they differ in more than one, either a cycle or a noncritical race must be prescribed." Critical races
must be avoided. Note that secondary
state assignments differing in only
one variable are
Chap. 15
TRANSITION MAP
213
represented in the transition

is
map by
"adjacent" entries. Therefore,
if
there
a transition between two particular rows, their reference
letters
must
either
appear in adjacent squares of the map, or
if
not, either a cycle or
a noncritical race must be prescribed.
Example:
Row
is
(Fig. 15-13) is arbitrarily assigned the
y y
x
= 00
state,
and an a
entered in the corresponding square of the transition map.
Examination of the flow table shows that all row-to-row transitions must be accomplished by single secondary changes, since no cycles or
noncritical races are possible.
00
01
10

5 7 8
a
~c
d
b
3
S
Transition
map
Merged flow table

Figure 15-13
There
is
a transition between rows a and c (stable states
@ or
()
to
(5)).
Therefore, the secondary assignment for

either
assignment in only one variable, that is, 01 or 10. The y y 2 01 assignment y y2

x
from the row a the assignment for row c must be

c
row
must
differ
is arbitrarily chosen, a c t being entered in the corresponding square of the transition map.
and d (stable states (D or (2) must therefore be assigned the y y 2 = 10 state, a d being entered in the corresponding square of the transition map. The transition between rows b and d (stable states (3) or (4) to ) requires that the two corresponding row assignments differ in only one variable, and row b must be assigned the remaining y y % =11 state, a b being entered in the corresponding square of the transition map.
is
There
also a transition between rows a
to
(8)).
Row d
It
remains to be determined whether this assignment
satisfies all
other
transitions in the flow table.
The remaining
(3)
(5)
transitions are
between rows
b and c (stable states
or or or or or
(6) (6) (8) (8)
to to
to
(8)) (J)) (2))
and c and d and d and

c
b (stable states a (stable states a (stable states b (stable states
(5) (7) (7)
to to
(T))
(4))
All transitions are between adjacent
map
entries,
and the secondary
214
r,<r
SEQUENTIAL CIRCUITS
Chap. 15
assignment, as indicated in the transition map,

01
II
is
y y 00
10
therefore satisfactory.
Oo|
01
1
1
5 2
10

3 7
dary assignment
so that the
is
The flow table with shown in Fig. 15-14.

is
secon-
Note that the order of the rows
rearranged
secondary states are in the reflected
ordering, preparatory to obtaining excitation
and
Flow table with
secondary assignment
Figure 15-14
output maps from the flow table.
An
assignment free of
critical races is
not always
possible with the initial
number of
variables,
and
additional secondaries
may be
required, as will be
described in the following chapter.
r-Map
In obtaining a
it is
convenient to
Y-map from the flow table with secondary assignment, make the map entries for the stable states first. Each
map
the
entry (secondary excitation) corresponding to a stable state will be
same as the present secondary state. A partially completed 7-map from the preceding flow table is shown in Fig. 15-15. Each map entry (secondary excitation) corresponding to an unstable state will be the same as the next secondary state. Since no cycles are prescribed in this example, each map entry corresponding to an unstable state will be the same as the map entry for the corresponding stable state. The completed F-map is shown in Fig. 15-16. All left-hand map entries in Fig. 15-16 define Yu and all right-hand entries define Y2 The expressions for the secondary excitation circuits follow.
.
Y\
j
2
XiX^y^ + XxX%y2 = XiX^yi ~r
-f-
x zyi
^2^2
^l-x^.yi
When, in a column of a flow table, an unstable state number appears more than once, a cycle or a noncritical race may be prescribed in that
column.
*\*z
10
*\*z y V
1
\'Z
00
01
11
10
00 00
01
1
1 1 1
01
01
00
00
11
1 1
10
01
00 00
01
1
00
01
01
11
11
10
01
10 00 10
11
10
10
Fl
10
10
K-map
F igure
gure
5-1
15-16
Chap. 15
Y-MAP
215
Example:
*\*z
yy JZ 00
'\
i
01
II
10
00
01
II
10
a
c
d
b
00
01 map
1
1
1
15

3 7
(7)4
6
4 3
2
a
c
Transition
10
7 d
Partiolly--completed
flow table with
Merged flow table

Figure 15-17
Figure 15-18
A column having only one stable state need not be of any concern in making a secondary assignment, since cycles and noncritical races can be prescribed in such a column. Therefore, ignoring the x x^ = 00 column
x
temporarily (Fig.
15-17),
the row-to-row transitions in the other three
columns lead to the secondary assignment shown in Fig. 15-18. = 00 column can be treated are shown The optional ways that the 15-19 in Figs. and 15-20. It should be remembered that transitions from one unstable state to another are denoted by arrows; the absence of an arrow leading from an unstable state number indicates that the next state
x^
is
the corresponding stable state.

-#1 -#2
X\
-f2
The options
-#1
are
numbered
for reference.
#3
X\
-#4 -#5
f\
-#6
*1 *2
#1
*i
-#2 -#3 -#4 -#5 -#6 -#7

X\*2
X\
*2
*2
*2
*!
*2
*2
X\X%
*\*2
*\*2
*\*2
*\*2
*\*2
yy 00
00
01
1
1
00
00
00
00
00
00
00 00
01
1

P
i
00 00 00 00 00
01
00 00
01
1
00
1
00 00
01 01
00
10 10
10
; i
P P 1*1' p p i' p
Figure 15-19
i/
10
00 00
10
10
00 00
*)*2
=
00
00
X\X 2
00 column
of flow table
00
column of
K-map
Figure
15-20
x
is
In option 11 row to the y y 2 00 row 1, the transition from the y y 2 accomplished by a noncritical race. In option #2, it is accomplished by a cycle: y y 2 11 to 01 to 00. Option #4 is similar to option #2 except
x
x
from the 10 row to the y y 2 00 row, instead of accomplished by a cycle: y y 2 10 to 11 to 01 to 00. Option #6 is similar to option #2 except that a noncritical race enters into the transition from the y y 2 10 row. Options #3, #5, and #7 are similar in type to options #2, #4, and #6
that the transition
x
j^ =
x
being direct,
is
respectively.
216
SEQUENTIAL CIRCUITS
Chap. 15
is
The completed flow table with secondary assignment, using option #1, shown in Fig. 15-21, with the associated F-map and secondary excitation
expressions.
X XZ
K
vv 00
01
11
10
y v
00
01
01
11
10
00
01
1
1 1 1
@
2
00 00
01
I 1
00
1
10
01
01
00
01
11
1
00
10
10 00
00
10
Flow table with secondary assignment
Y-mop
Figure 15>21
When
various options are possible, as in the example above, or
when
alternative assignments are possible, they should all be investigated, since

at this stage of design there is
the most economical solution.

tion
and output
circuits
no way of knowing which one will lead to The economy of both the secondary excitacan be affected by the choice of assignment and
the choice of optional transitions.
PROBLEMS
1.
Merge
the primitive flow table in Fig. 15-22.
*1*2
X\XZ
01
II
00
10
00
01
II
10
428
1
4
3
"5
5
4
9
-
7 7
6 7
1
8
1
36"2.
2 -

7 6 7
5 2
8
-
9
-
Figure 15-22
Figure
15-23
Merge
the primitive flow table in Fig. 15-23.
16
Sequential Circuits IV
Utilization of
Spare Secondary States
A secondary assignment for a three-row flow table can always be achieved with two secondary variables, although
sometimes the "spare" fourth secondary state must be utilized to avoid critical races. This requirement occurs when
there are transitions between
all
00
01
11
10
three pairs of rows, ab, ac,
and
be, as illustrated in Fig. 16-1.
No matter how secondary
23 5
4
Figure 16-1
assignments are made, a transition will be required between two rows whose secondary state assignments differ in two
variables.
transition
For example, with the secondary assignment shown in the map in Fig. 16-2 rows a and c are each adjacent to row b, but are not adjacent to each other. However, transitions between rows a and c can be made without introducing
critical
race conditions: cycles through the spare
yî =01
Figure 16-2
217
1 1
218
SEQUENTIAL CIRCUITS
IV
Chap. 16
secondary
this
state, arbitrarily
labeled d, can be prescribed.

is
The flow table with

Y-map.
shown
in Fig. 16-3, with the associated
y.y 9
00
01
II
10
00
01
1
.3
3
a
4
f
y.y.
00
01
10
00 00
01
1
d
c
II
1 1
10
01
11
1
00
-tl
00
01
10
10
10
10
10
Flow table with

/-mop
Figure 16-3
shown and 16-5, one in which rows b and c are not adjacent, and the other in which rows a and b are not adjacent. The three secondary assignments shown (Figs. 16-3, 16-4, 16-5) will,
other secondary assignments for the same problem are
in Figs. 16-4
in general, lead to different solutions.
Two
A secondary assignment, without critical races, for a four-row flow table can not always be achieved with two secondary variables, and three secondaries may be required. With three secondaries, eight secondary states are available four for assignment to the four rows of the table, and
:
four as spares.
y\
00
01
11
10
LA
e
00
01
1
23 @
4
y yz 00
y
2
r
a
d
01
1
^2
10
5
Flow table with
10
@ @
4
6-5
b
c
Figure 16-4
Figure
of a four-row flow table requiring three secondaries is shown in Fig. 16-6. This example illustrates a "worst case" condition in which there are transitions between all six pairs of rows, ab, ac, ad, be, bd, and cd.
An example
Three secondaries may be required, however, for four-row flow tables in which there are transitions between as few as three of the six pairs of rows,
as Fig. 16-7 illustrates.
Chap. 16
UTILIZATION OF SPARE
SECONDARY STATES
219
00
01
11
10
00
01
11
10
234 (2)(7^ 86
5
1
234 @
I
(8)
@(4
Figure 16-6
Figure 16-7
Sometimes
it
may
is
appear, at
first,
that additional secondaries are needed
when
left
actually this
not the case. For
example, in Fig. 16-8, analysis of the

three columns of the flow table
00
01
II
10
shows transitions between rows a and b, b and c, c and d, and a and d, and
the transition
map
so far represents
a satisfactory secondary assignment.

transition
The x,x 2 from d
10 column contains a
to
c,
234 @
5
a
1
d_
Transition
map
Flow table
Figure 16-8
for which the

is
still
secondary assignment shown

satisfactory.
However,
this
also contains a transition
column from a to c, which, with the assignment shown,
involves a change of two secondary variables.
A critical race can be
avoided
without the use of an additional secondary, however, by the cycle adc

being prescribed for this transition.
The following
analysis of secondary assignment patterns
is
intended
to give the reader an appreciation for the
number of ways in which secondary a feel for the types of variations him and give made, to assignments can be purposes only, and are reference for numbered The patterns are possible.
It
presented for analysis.
should not be inferred that in a particular problem,
some pattern should be "chosen." The secondary assignment should most generally be "tailor made" for each problem; the reader, having studied the patterns, should have a more thorough understanding of the variations possible.
When three secondaries are required for a four-row flow table, there are seventy ways of selecting four out of eight secondary states for assignment
to four rows
8!
4! 4!
70)
220
SEQUENTIAL CIRCUITS
IV
Chap. 16
Pattern
Word description
hx am\lie
y,yz
w and x
differ in
one variable
#1
x and y differ in one variable y and z differ in one variable

z
00
w
1
01
11
10
and w
differ in
one variable
Figure 16-9
#2
x and w differ in one variable x and j differ in one variable x and z differ in one variable
/,/2
'3-
00
01
II
10
Figure 16-10
#3
w and x differ in one variable x and y differ in one variable y and z differ in one variable
z and
y oo o f
oi
n
/
z
io
differ in three variables
Figure 16-11
y yz
x
#4
* and w differ in one variable x and >> differ in one variable x and z differ in three variables
00
01
II
10
Figure 16-12
w and x
differ in
one variable
y oo o< o w X
i
#5
y and z differ in one variable w and y differ in three variables
n
y
io
x and z
differ in three variables
Figure 16-13
/,/2
#6
All pairs of states differ in two variables
y 7 3
00
01
'
II
10
Figure 16-14
Chap. 16
SECONDARY STATES
221
Analysis shows that each of the seventy combinations

different patterns.
falls
into one of six
word
description of each pattern, with an example

is
of each in a transition map,

arbitrarily labeled w, x, y,
given on p. 220.
in the
it
and z to aid
The selected word descriptions.
states
are
can be used for any four-row flow table in which there are transitions between five or fewer of the six pairs of rows, but it can be used only for some worst case conditions. Patterns #2 through #6 can be used for any four-row flow table. For each combination, there are twenty-four permutations of row
The
application of pattern
#1
is
limited:
assignment
( 4 i>4
=4!=24)
selected secondary
that
is,
there are twenty-four
ways of assigning four
states to four rows.
Analysis shows that for each pattern, certain
row
assignments lead to solutions that are equivalent with secondaries interchanged. The number of nonequivalent row assignments for each pattern
follows
Number of
nonequivalent row
Pattern
assignments
3
#1
#2 #3 #4 #5 #6
4
12
12
6
1
38
If three secondaries are required for a four-row flow table, there are thus
thirty-eight secondary assignments that will, in general, lead to different
solutions (thirty-five in cases in which pattern
#1
is
not applicable).
shown in Fig. 16-15. The pattern variations in the fourth example of pattern #2, and in the last six examples of patterns #3 and #4, are made to retain the y!y 2 y 3 = 000 assignment for row a. Each pattern will now be examined in more detail and illustrated by a flow table example. For each pattern, a resulting flow table with secondary assignment, and its associated Y-map, will be shown for study.
Examples of the
thirty-eight assignments are
Exceptions can occur when cycles are required as part of the original
cations; see section
circuit specifi-
on Transient Outputs; Cyclic
Specifications. Cyclic specifications are
not considered in the discussion that follows.
222
SEQUENTIAL CIRCUITS
IV
Chap. 16
Pattern
-#5
00
#
10
Ki
01 11 10
^00
a
w
01 II 10
'.'*
00
a
01
II
10
>5
00
01
II
00
01
II
10
b
1
c
~~d
c
~~d
1
b
c
0__b__
d
c
d
y<y t
d y,y 2
oo
a
t
oi ir io
00
a
01
110
00
01
II
10
'.4 00 01
11
10
00
a
1
01 11 10
a_b_
c
ob_d__
c
d
y,y z
d
00
a
A*
01 11 10
*,
00
a
01
11
10
00
a
01 It 10
yt 00
1
y 00 01
11
10
f,
01 11 10
d b
c
d b
A
d
1
b d
y,yz 00 01
a
c
/,
11
10
y2 00 01
a
c
H
d
~b
10
00
a
01
10
y,yr 00 01
a
c
1
to
d
~b
d b
00
01 II
10
*,
00
01
1 1
10
o_d_
c
q_d_b__
c
1
d
b
e
y yz 00 01
K
11
10
00
01
II
10
ode
~b
ode
~b
K3
00
01
11
10
a d
1
00
a
01
11 10
00
01
II
10
q_c^
*3
00
b
01
II
10
/s 00
a
1
01 11 10
d c
1
d
c
/,/2
K,
00
c
01 14 10
/s 00
1
01 11 10
b
1
d
b
y,yt
00
e
01
II
10
00
a
01
MO
a_4_
y,y 2
y.
d e b 00
00
a
01 11 10
/j
01
11
10
b c
1
d 00
a
d b
io
y<yt
01 It 10
oo
o
01
~T~b~c
for four-row flow tables
Examples of three-variable secondary assignments
Figure 16-15
Chap. 16
SECONDARY STATES
223
Pattern
#1
map
of pattern
In the transition
#1
K '3
(Fig. 16-16), the
e, f, g,
1
y yz 00
{
01
10
w
z
four spare secondary states are labeled arbitrarily,
and
z,
h.
Figure 16-16 Transitions between states w and x, x and y, y and and z and w are direct, since they involve the change of only one variable. Critical races in the transitions between states w and y can be avoided by the utilization of the spare states. The cycle
wefhy
or the cycle
weghy
or the cycle with noncritical race
wehy
can be prescribed. If a race from e to h is prescribed, / and g must also be directed to h if a race from h to e is prescribed, /and g must be directed to e.
;
The
three variations can be
summarized by the notation

we(fg)hy
which
signifies that
the transitions between e and h
may
involve a non-
The notations apply in both directions; for example, for transitions from w to y and from y to w. Transitions between states x and z can be similarly prescribed as follows
critical race
or a cycle through
/ or
g.
xf(eh)gz
The limitation on the application of pattern #1 is that transitions between states w and y and between x and z cannot occur in the same column because of the conflicts that would result in the direction, in that column, of the sp?re states utilized in both transitions. Therefore, if there are transitions between two pairs of rows in the same column, the assignment of states w and y to one pair, and states x and z to the other pair, cannot be allowed. If such an assignment cannot be avoided, pattern # 1 cannot be used. The following example illustrates this condition. In the x x 2 = 00 column of Fig. 16-17, there are transitions between
t
rows a and d, and between b and c. Therefore, the assignment of states w and y to rows a and d, and the assignment of states x and z to rows b and c, or vice versa, is not allowed. In the x x 2 =01 column, there are transitions between rows a and b, and between c and d. Therefore, the assignment of states w and y to rows a and b, and the assignment of states x and z to rows
y
x xz
s
00
01
11
10
V ^^ 5
2
86
\ 1
o,yV)t(
(7^ A
j 4 ()($) 7
and
d,
or vice versa,
is
not allowed. In the x^x^
11
Figure 16-17
224
SEQUENTIAL CIRCUITS
IV
Chap. 16
00 column. In the XiX 2 XxX 2 rows a and c and between b and

d,
column, there are transitions between the same pairs of rows as in the 10 column, there are transitions between d. Therefore the assignment of states w and y to rows a and c, and the assignment of states x and z to rows b and
or vice versa,
is
not allowed.
z in the same column, and pattern
There
is
thus no assignment that will avoid transitions between states
w and y and between x and

be used for
used.
this
flow table. In the example that follows, pattern
# #
cannot
can be
in
The x x 2
x
= 00
and x x 2
x
= 01
columns
states
in Fig. 16-18 are the
same as
the preceding example, and therefore the assignment of states
w and y
c,
to
rows a and
versa
b,
is
d,
and the assignment of

states
x and
z to rows b and
or vice
not allowed; and the assignment of states
w and y
and
d,
to rows a
and
is
and the assignment of
x and z
to rows c
or vice versa,
also not allowed.
00
01
11
10
@ @
2
M
>3
00 a
01
11
10
e
b
c
/
ft
d
Fifi
Figure 16-18
ure 16 19
All six possible transitions occur in the flow table, but the remaining
two transitions occur in different columns: the transition between rows b and d occurs in the x^x 2 = 11 column, and the transition between rows a and c occurs in the x x 2 = 10 column. Therefore, states w and y can be assigned to rows b and d, and states x and z can be assigned to rows a and c, or vice versa, and pattern #1 is thus applicable. The assignment in Fig. 16-19 is chosen. Transitions between rows a and c are prescribed by
x
ae(fg)hc
and
transitions
between rows b and d are prescribed by

bf(eh)gd
resulting flow table with secondary assignment,
and
its
associated
Y-map, are shown in Fig. 16-20. The cycle dgefb is chosen for the d to b transition in the x x 2 = 11 column. The cycle with noncritical race aehc is chosen for the a to c transition in the x x 2 = 10 column. The choices of
x x
optional transitions in this and the following examples are arbitrary, and are selected to illustrate the various types of transitions possible.
The flow
table in Fig. 16-21 will be used as a running
example in the
Chap. 16
SECONDARY STATES
225
examination of patterns
pattern
is
#2
through #6. The assignment
illustrating
each
chosen
arbitrarily.
x.x. \*z
X[
xz
01
11
00
01 2
11
10
00
'l>2 >3
10
000
001
01
1
4
,6
000 000 010 000 100

001 000 001 101 001
01
1
011 001 01
011
010
110
1
1
010 Oil 010 010 010

I
10
1
II
010

100
11
Oil
111
101
101
100
100
110 111
Y map
16-20
Figure
x.x-
\*z
00
01
II
10
234
1
86
(8)<S) 7
Pattern
5k
Figure 16-21
#2
y,y z
00 a
f
01
II
10
e
c g
Figure
16-22
Transitions between rows b and a, b and
c,
and b and d are
direct.
The
remaining transitions are prescribed by

aec
afd
cgd
226
SEQUENTIAL CIRCUITS
IV
Chap. 16
*l*2
00
01
11
10
y*y-n.
00
01
If
10
ooo
001
01
I
000 000 010 00

001 000
01
1
100
1
01
*\*z
001 Oil 011 010

1
00
01
11
10
010
1
010
1
10
010 010 010

1 1 1
10
1
10
1 <
10
-
010 110
5 -
4
9
-
01

__-
6
1
7 (3) 7 3
(5)
9 9
-
8
-
101
101
...
100
Flow table with
100
.._
110
6
-
7 5
8
(8) 3
K-map
Figure 16-23
Pattern
#3
00
a
f
01
II
10
b
g
Figure
16-24
Transitions between rows a and
b,
b and
c,
and c and d are
direct.
The
remaining transitions are prescribed by

aec
bgd
a{ef)hd
If the
or
af(gh)d
However, the spare
a to d transition afhd is chosen, there can, of course, be no conflicts. states e and g can be utilized in more than one type of
For example, consider the transitions involving and aehd. Transitions from a to c and from a to d cannot occur in the same column. Transitions from c to a and from d to a, even if they do occur in the same column, cause no conflict, e being directed to a in both transitions. Also, of course, transitions from a and to a cannot occur in the same column. When there are two types of transitions, with a row of a flow table common to both, for example, row a in the preceding example, the same
transition without conflicts.
the spare state e: aec
spare states can be utilized in both transitions without conflict.

If
two types of transitions have no rows of a flow
table in
common,
the
L
Chap. 16
SECONDARY STATES
227
same spare
if
states
can be
utilized in
both transitions, without
conflict,
only
the transitions
do not occur
in the
same column
(see
examples in the
discussion of pattern #1).

there is a choice of transitions between two rows, the one selected any particular column is independent of that chosen in any other column. With pattern #3, for example, aehd might be chosen for the a to d transition in one column, and afgd might be chosen in another column.
for
When
In the flow table in Fig. 16-25, the cycle with noncritical race dfa
x
is
chosen for the d to a transition in the x x 2 = 00 column and the cycle aehd is chosen for the a to d transition in the x x 2 = 1 1 column.
;
x
*\*z
00
01
10
00
a
f
01
11
10
000
^01
01
I
000 000 010 100 100

001 ooo
01
1
010
110
1
1
( /
5
1
8 6
001
010
b
c
010
1
110 010 OtO 010

11
1
10 110
1
010
110
// 1
'
d
h e
001
ooi
111
111 011
III
101
100
VA
3'
101
---
110
100 ---
101

Fig lire
^-map
16-25
Pattern
#4
4/?
y>
00
a
01
11
10
e
b
g
1
C
h
igu re
6-3 6
Transitions between rows a and b, and b and c are direct.

transitions are prescribed
The remaining
by
aec
a(ef)d
c(eh)d
bg(fh)d
228
SEQUENTIAL CIRCUITS
IV
Chap. 16
Note
that the spare states
e,
f and
h can be utilized in
more than one type

is
of transition, similar to the spare states in pattern #3.

In the flow table in Fig. 16-27, the noncritical race da
chosen for the
x x 00 column; the cycle aed is chosen for the a to d transition in the x x 2 = 11 column; the cycle ced is chosen for the c to d transition in the x x 2 = 01 column; and the cycle with noncritical race dgb is chosen for the d to b transition in the x x 2 = 10 column.
to a transition in the
*\*Z
*\*Z
00
01
11
10
00
01
11
10
000
001
01
i
000 000 010 100 100

001 000
01
...
1
Ih
1
1
01
...
010
010
I
10
1
4
If
4
010
1
10 010
10 100
010 010
10
1
010
10
1
01
101
lvv'
8
3
101
000
101
101
101 01
100
100 000
101 110
Flow toble with secondary assignment
^-map
Figure 16-27
Pattern
#5
Wz
y 00
a
1
01
11
10
e
fact/
Figure 16-28
b,
Transitions between rows a and

transitions are prescribed
and
and d ate
direct.
The remaining
by
a(ef)d
b(gh)c
aehc
or or
afgc
bhed
bgfd
All spare states can be utilized in
more than one type of

in
transition,
subject to the following restriction: since transitions between rows a
and
and between rows b and d involve no rows
common,
if
both types of
: 1
Chap. 16
SECONDARY STATES
229
transitions occur in the

utilized in
same column, the same spare states cannot be both, and the choice of transitions must be restricted to
a(ef)d
b(gh)c
a(ef)d
b(gh)c
aehc
afgc
bgfd
bhed
In the running example, the above restriction must be observed since,

in the
x x2
x
10 column, there
is
a transition from row a to
c,
and from
to b.
In the flow table in Fig. 16-29, the noncritical races da and be are chosen
dto a and b to c transitions in the XiX 2 = 00 column; the and chb are chosen for the respective a to d and c to b transitions in the x x 2 = 11 column; and the cycles aehc and dfgb are chosen for the respective a to c and d to b transitions in the x x 2 = 10 column.
for the respective
cycles afd
x x
*1*2
*\*z
00 JiAA '1 '2 '3
01
11
10
u u
'1
00
01
11
10
'2 '3
000
001
01
1
O
1
2,3
a
f
000 000 010 001

001 000
011
1
100
011
101
010
110
1
5 5
M
6
8
11
1 1
010
b
h
010
1
010 010 010
10 111
1
101
010
110
101
111 111
1 1
c v
101
\m c
111
(D\\/ d
101
000
101
001
\
100
too 000
10
Flow table with
Figure
Y map
16-29
Pattern
#6
y*y->
00
01
11
10
e
a
1
9
C
b
h
Figure
16-30
The
transitions are prescribed as follows
230
SEQUENTIAL CIRCUITS
IV
Chap. 16
a(eg)b a(fg)c
a(ef)d
b(gh)c
b(eh)d
c(fh)d
Note that
all spare states can be utilized in more than one type of transition. Also note that noncritical races can be used for all transitions.
In the flow table in Fig. 16-31, the cycles dea and bgc are chosen for the
d to a and b to c transitions in the x x 2 00 column. The cycle aeb and the noncritical race cd are chosen for the respective a to b and
respective
x
c to
transitions in the
x x2
x
=01
column. The noncritical races ad and cb
are chosen for the respective a to
d and
c to b transitions in the
x x2
x
column. The noncritical race ac and the cycle deb are chosen for the spective a to c and dtob transitions in the x x 2 10 column.
x
re-
*1*2
*\*z
01
11
00
10
ooo
001
01
I
y
t
y->y*
00
01
11
10
1
a
f
000 000 100

001 --- 101
01
1
101 01
1 e
34
6
101 01
1
(86
4
c 9
011 101
010
1
010
1
on
10
10 011
10 Oil 10 110
10
1
c
8
<D
6
(3)
,7
b
h
to 010
1
101
10
101
\(8)
d
e
101
100 101 101 100

1
too ^1
100 000
10 101
110

Figiire
Y-xnap
16-31
Assignment of Multiple Secondary States

to a
Row
far has
The discussion of secondary assignments so

assignments in which each row of a flow table
state.
is is
been limited to
assigned one secondary

required, however, rows
state,
When
the use of spare secondary states
of a flow table can be assigned more than one secondary

type of secondary assignment will
and
this
now
be examined.
Chap. 16
MULTIPLE
SECONDARY STATES TO A
ROW
231
A secondary assignment
row flow
secondary
table previously
state.
for the three(Fig.
*,
xz
cm 2
examined
00
(T)
5
to
16-32), requires the use of the spare fourth
3(4)
:
In a previous
in
example,
16-33
(2)(s)(7)b
d
c
the secondary assignment
Fig.
@{8)@4
state,
was made. In the transitions between rows a and c, critical races were avoided by
cycles
Figure 16-32
Figure 16-33
through the spare y y 2

x
= 01
secondary
labeled
d,
being
prescribed.
spare
The preceding assignment can be modified by the assignment of the y y 2 01 state to row a or row c, which still avoids critical races
t
in the transitions
between rows a and
c.
Example:
When more
than one secondary state
is
assigned to the same row, rows
with equivalent stable states are created in the flow table with secondary
assignment. Subscripts are used to differentiate these rows and equivalent
stable states for transition identification. stable states are the same,
The output conditions of equivalent

critical
and the
selection of equivalent states for a
particular transition
is
based fundamentally on the avoidance of
races. Refer to Fig. 16-34.
Transitions from b to a are directed to

are directed to a 2
;
row
a,; transitions
x ;
transitions
from a 2 to b cycle through a
from c to a and transitions

7-map,
from
#! to c cycle
through a 2
The flow are shown in
table with secondary assignment,

Fig. 16-35.
and
its
associated
00
>i/2
01
II
10
00
0\
01
11
10
00
01
1
1
.2/3
^ S
5
0\
b
c
10
@
42
state
00 00
01
1
10
01
11
11
00
01
01
az
c
01
1
00
11
10
10
10
10
oz

Figure 16-35
Y map
Figure 16-34
Subscripts are used
on unstable
numbers where necessary to

for the
specify
to which of equivalent stable states a transition occurs.
Figures 16-36 and 16-37
show another assignment
same problem,
a.
with the y y 2
x
= 01
secondary state assigned to row c instead of row
232
SEQUENTIAL CIRCUITS
IV
Chap. 16
X\*z
y y z 00
s
00
01
11
10
a
C\
23,

52
K.
00
01
11
10
00 00
01
1
10
01
11
01
01
11
00
0i
1 1
01
1
00
01 10
cz
>9
a
1
b
cz
10
10
10
10
C\
Flow table with secondary assignment Figure 16-37
Y map
Fig ure 16-; 16
The assignment of multiple secondary states to a row can be modified by the replacement of some equivalent stable states with the corresponding unstable states. For example, the flow table in Fig. 16-37 could be modified
as
shown
in Fig. 16-38.
00
01
11
10
oo
01
1

,5
*5
3,
4
x
10
@t @
4
(|j
Figure 16-38
When
three secondaries are required for a four-row flow table,

is
and the
assignment of more than one secondary state to a row

additional patterns
16-43), in
considered,
many
become
possible.
Some examples
follow (Figs. 16-39 to
which all eight secondary states are assigned to rows. Notice that the pattern in Fig. 16-43 differs from the others in that no
rows with equivalent stable states are adjacent, but each row is adjacent to one of each type of nonequivalent row, so that all transitions are direct.
y<yz
y. 3
y yz
s
y^y*
00
\
01
*i
11
C\
10
cz
1
00
0\
01
10
Cz
>3
00
a
01
11
C\
10
cz
b
d\
C\
az
bz
* dz
az
dz
dz
dx
dz
d*
d4
Figure 16-39
v,y z
Figure 16-40
Figure 16-41
y,yz
01
11
K 00
\
10 *3
dz
/, '3
00
0\
01
bs
11
C\
10
d<
b
d\
az
dz
cz
dz
az
bz
Fig ure 16-'12
Fig ure 16-413
Chap. 16
SPARE
SECONDARY STATES SUMMARY
233
Utilization of
Spare Secondary States
Summary
and four-row flow been discussed in some detail. The many examples studied are to make the reader aware of the variations possible the selection of patterns; the selection of assignments for each pattern; and the selection of
utilization of spare secondary states for three-
The
tables has
The concepts more than four rows. The ultimate selection of a flow table with secondary assignment is most generally based on circuit economy. When circuit economy is the criterion,
optional transitions and modifications for each assignment.
discussed can be extended to flow tables of
the comparison of different flow tables with secondary assignment cannot
be made directly; the associated Y-maps and Z (output)-maps must be obtained, the secondary excitation and output expressions obtained from the maps, and the resulting total circuits compared. Blank entries in a flow table result in corresponding optional entries
in the associated Y-map. Optional entries are, of course, generally desirable
from a circuit economy standpoint. Having made a "trial" assignment and obtained the corresponding Y-map and Z-map, it might be observed that better groups, i.e. simpler
expressions, could be obtained if particular
map
entries
were
l's
instead
of O's, or vice versa. Making such a change might necessitate the assignment of multiple secondary states to a row.
One should
also take the fullest advantage of the generally wide selection
of optional transitions and modifications for an assignment. For example,

in Fig. 16-41, the possible transitions
(a)
from d to
x
c are:
d^ct
x
(b)
(c)
d dd3 c
x
d d d3 c
x
(d)
(e)
(f)
d d2 d3 diC2
x
dc x with
, ,
d3
directed to c
d d2 d3 c2 with
x
d directed to c2
(g)
d d3 c with d2
x
x ,
directed to directed to
and
d directed to
3,
c x or c2
.
(h)
dd
x
c2 , with
and J4 directed to
c2
Note that in
transitions (e) through (h), circuit action

.
may
terminate in
either c x or c2
The choice of secondary assignment may
also be based
on the speed
of transition. For example, pattern #6, with noncritical races prescribed for all transitions, might be chosen if it were desired that all transition
times be short; whereas pattern
#1
might be chosen
if
a long time delay
were desired for a particular
transition.
234
SEQUENTIAL CIRCUITS
IV
Chap. 16
PROBLEMS
1.
Make
a secondary assignment for the flow table in Fig.
6-44,
draw the
associated Y-map,
and
obtain the secondary excitation expressions.

x x2
\
00
01
11
10
25

3
10 5
Figure 16-44
*2.
Make
a secondary assignment for the flow table in Fig. 16-45, draw the
associated Y-map,
and obtain the secondary

00
01
excitation expressions.
10
@
4
7
F'SMf* 16- 45
3.
Obtain the y-map from the flow table in Fig. 16-46.

00 01
11
10
1V3 000
001
01
1
3v
6^8
6/V 8 \
010
1
/
4,
10
11
U)
101
r
100
Figure 16-46
*4.
Obtain the Y-map from the flow table in Fig. 16-47.
1 1
Chap. 16
PROBLEMS
235
00
01
II
10
000
001
011
3,
42
7x
\
83
010
1
5-
&\
10
11
,1
101
[ V I
J
7 ?
100
84
Figure 16-47
5.
Obtain the secondary excitation expressions from the Y-map in Fig. 16-48. Find all optimum solutions.
00
/1/2
01
11
10 01
00 00 00
01
11
11
10
01
01
1
01
11
11
10
10 --
00
11
--
Figure 16-48
*6.
Obtain the secondary excitation expressions from the Y-map in Fig. 16-49. Find all optimum solutions.
*\*z
00
>i/2
01
01
11
10
00 00
01
11
1 1
10 01
1
00
01
01
11
11
10
10 --
--
11
00
Figure 16-49
17
Sequential Circuits
Z-Map
The output expressions
from the flow
are read
table with secondary assignment
from the Z-map. The Z-map is obtained and the primitive flow
table: The output state for each stable state is identified in the primitive flow table, and the location, in the Z-map, of the output state is identified
in the flow table
with secondary assignment. Also, the actual state to state
transitions are identified in the primitive flow table, this information being
used in the assignment of output states for the unstable states. Figure 17-1 shows a primitive flow table and a corresponding merged flow table with secondary assignment.
In constructing the Z-map, the output state for each stable state
entered in the
is
each stable state is found in the primitive flow table; the location, in the Z-map, of the output state corresponds to the location of the associated stable state in the flow table
first.
map
The output
state for
236
Chap. 17
Z-MAP
237
00
01
11
10
00
01
11
10
234 12 5
1
2
1
*\*z
00
01
11
10
Merged flow table with secondary assignment
Partially-completed
Z-map
Figure 17-2
Figure 17-1
with secondary assignment. The partially-completed

Fig. 17-2.
Z-map
is
shown
in
In the assignment of output states for the unstable states, the following
rules are observed
(1) If, in
a transition, the states of an output for the initial and final stable states are the same, this same output state must be assigned for all unstable states involved in the transition. Transient changes
in output state are thus prevented.

(2)
The output
states for all unstable states
not covered by rule
may
be optional except that in all state, the output must change state only once. The exception must be noted only when there are two or more unstable states involved in a transition; oscillatory changes of output states are thus
prevented.
transitions involving a change in output
The preceding Z-map
will
now be
completed. The flow table with sec-
ondary assignment indicates that unstable state 2 may be involved in a to (2) transition to (2) or from () to (2). The transition from stable state specifies no change in output state (the initial output state is 0, and the Anal output state is 0). If this transition does in fact occur, the output state must be for unstable state 2. Reference to the primitive flow table shows must to (2) transition does occur; therefore the output state that the
be assigned to unstable state 2. The flow table with secondary assignment indicates that unstable state or from () to 0. The (3) to 4 may be involved in a transition from
to
transition
is
the critical one in this case; both the initial

1.
and
final
output states are

(3)
to
Reference to the primitive flow table shows that the transition occurs; therefore, the output state must be 1 for
4.
unstable state
The flow
1
table with secondary assignment indicates that unstable state
may be involved in a transition from (2) to , from (5) to 0, or from transitions both specify no change in and to to 0. The (2) to
238
Chap. 17
w. ^v, 01 y 00
1 ,
1
.
10 .
1
OOOii 1-001
1
output
state
state;
if
either
transition
occurs,
1.
the
output
must be
for
unstable state
The
primitive
flow table shows, however, that neither of these transitions occurs. Since unstable state
transition specifying
1
Z map
Z
-
is
not involved in a
Figure
*,/+ *,7^
K
no change
in output state, the out1.
or x
+ x
zy
put state
17-3
may
be optional for unstable state
shows the completed Z-map
and the output

outputs.
Figure 17-3
expressions.
Figure 17-4 shows an example with two
The
is
not shown, but from
it
has been obtained the
output state for each stable state; these output states appear in the partiallycompleted Z-map. All left-hand map entries define Z all right-hand map
x ;
entries define
The
primitive flow table also shows that
all
transitions
indicated in the flow table with secondary assignment
do
occur.
X\*Z
'.
K, 7
00
01
01
01
11 11
10
10
*\
xz
01
1
*\*z
1
00 00
01
11
ry z
y
00
10
v
_
00
10
00
01
1
10
lith
01 00
1
01 01
1
00 00
01
11
11
o-
10
-1
11
01 01
10
10 10 00
Z map
11
10 10 00
Merged flow table

Partially- completed
Z, \
--'
x XyY
Z
{
+ X *Z + xz y
K
K
Z--map
x y- + x z
Figure
17- 4
Figure 17-5
The Z-map
tions
will
now be
completed. Unstable state 2
is
to
(2),
output states 00
involved in transi1 1
>
01
and
(f)
to
(2),
output states
>
01.
(2)
Examination of the two outputs independently shows that the (D to

Output states
Transition
Z\
(D
transition specifies
to to
(D
in the
(3)
1
no change
output
state,
requiring
Z =
x
for
unstable state 2; and that the
to
(2)
transition specifies
no change
X
in the
2
Z
is
output
state,
requiring
Z =
2
for unstable state 2. Therefore,
Z Z =01
is
required for unstable state
2.
The output
transition
state requirement,
Z Z^ =
X
10, for unstable state
similarly
determined: the
to
x
(4)
1.
transition requires
Z =0,
2
and the
()
to
(4)
requires
Z =
Unstable state
requires the
output state
Chap. 17
Z-MAP
239
Z Z = 00,
x
the
(2)
transition requiring
to 0, and the to (D transition requiring Zj requires the output state Unstable state 5 0. 2
Z =
(5)
ZjZ
(5)
= 01,
the
(2)
to
transition establishing both the
and
Z Z
output
states.
The output
states for unstable state 6
can be optional, since in the
requires the output state Z,
to to (D transition, both outputs change state. The for unstable state 7, whereas
transition
2
can be
optional since
state
it
changes
state.
The
(5)
to
(8)
transition requires the output
Z =
2
for unstable state 8, whereas
can be optional since
it
changes
state.
Unstable state 3 requires the output state

the output expressions are
Z Z^ =
X
11.
The completed Z-map and

multiple output change,
neously.
all
shown
in Fig. 17-5.
Sometimes there may be a requirement
that, if a transition involves
output state changes are to occur simultathis requirement, in the (5) to (6) transition in
For example, with
the preceding example, the output states for unstable state 6

restricted to either
would be
Z Z =01
X
or
ZjZ2
10.
Timing considerations may sometimes take precedence over circuit economy, and definite output states may be assigned in place of optional ones. For example
If
it is
desired that all outputs be of as short a duration as possible,
all
optional entries can be replaced by 0's

If
it is
desired that
all
outputs be of as long a duration as possible,

l's;
all
optional entries can be replaced by

If
it is
desired that
all
output changes occur as soon as possible,
all
optional entries can be replaced by the output entries for the corre-
sponding
If
it
final stable states

all
is
desired that
output changes occur as late as possible,
all
optional entries can be replaced by the output entries for the corre-
sponding
initial stable states.
Such timing considerations may, of course, apply to particular

tions only.
transi-
Some examples
in cycles
of output state assignments for unstable states involved

follow.
and races
Cycle No Change
in
Output State
00
oo
01
ii
01
11
10
00 00
01
1
01
11
10
10
10

Figure 17-6
Z-map
240
Chap. 17
Z = must be assigned to change occurs.

Cycle Change
all
unstable states so that no transient output
in
Output State
*\*2
00 y y z
(
01
II
10
oo
01
1
<
/,/ 2
00
01
11
10
00
01
1
10
10

Figure 17-7
Z-map
The output must change

optional output states
is
state only once,
and therefore the choice of
restricted to the solutions in Fig. 17-8.
*\*z
*\*z
01
1
*\*z
01
11
*\*z
01
11
y,y z
00
10
/,/2
00
10
y,y z
00
10
00
01
11
10
oo
01
1
00
01
1
oo
01
1
00
01
1
10
10
10
10
Z maps
Figure 17-8
Race No Change
in
Output State
^xz
y yz
K
00
01
11
10
00
01
11
10
00
01
1 1
00
01
10
10
Z-map
Figure 17-9
Z=
must be assigned to
all
unstable states so that no transient output
change occurs.
Chap. 17
TRANSIENT OUTPUTS; CYCLIC SPECIFICATIONS
241
Race Change
in
Output State
*\*z
'\'Z
y.
y~
00
01
11
10
00
01
11
10
00
01
t
1
1
1
00
01
10
10
Flow table with secondary oss ignment

Figure
Z-map
17-10
The output must change

optional output states
is
state only once,
and therefore the choice of
restricted to the solutions in Fig. 17-11.
*\*z
VlVl
*\*z
x\*z
00
01
11
10
00
oo
01
01
11
10
/,/ 2
00
01
11
10
00
01
1
1
00
01
1
10
10
10
*\*z
>j/ 2
00
01
11
10
>j/ 2
00
01
10
oo
01
1
00
01
1
10
10
Z maps
Figure 17-11
Transient Outputs; Cyclic Specifications

Transient outputs, associated only with particular unstable states,
may
sometimes be specified in a sequential

state 2
circuit requirement.
For example,
in the flow table in Fig. 17-12, a transient output associated with unstable
might be desired, the expression for
this
output being
Z = x^yjz
Cycles may be prescribed for the express purpose of introducing a series of transient outputs, as in the example in Fig. 17-13. continuous series of transient outputs is sometimes desired, as in the
example in Fig. 17-14.
When an
input change to
x x
t
= 01
occurs, the
242
*\*z
Chap. 17
00
y yz
y
00
01
^
II
10
01
11
10
oo
X\XZ
=
~*\
00
01
1
2>
01
01
11
00
y,y z
10
2)
10
Z\
*
00
01
1
10
2
*z y\
*\ xz /1
Z\
2
x xz Y\ ^z
\
Z2 = A"
*,*2/i/2
'1*2/1/2
10
Figure 17-12
^3
'1*2/1/2
Figure 17-14
Figure 17-13
circuit will cycle continuously,
producing the
series
of transient outputs
until
another input change occurs.

a cycle
is
When
the
required as part of the original circuit specifications,
series of transient outputs, transitions from and to same rows of a flow table occur in the same column, imposing restrictions on the applicability of the secondary assignment patterns previously discussed. For example, in the left three columns of the flow table in Fig. 17-15, transitions between all six pairs of rows occur. As far as these left three columns are concerned, the secondary assignment (pattern #5) in Fig. 17-16 is satisfactory. However, this assignment is not satisfactory for the x x 2 = 10 column. If the a to b transition is prescribed by the cycle afgb, the b to c transition must be prescribed by the cycle bhc, and there are then no spare rows adjacent to c to accomplish the c to d transition. If the a to b transition is prescribed by the alternative cycle aehb, the b to c transition must be prescribed by the cycle bgc, and again there are no spare rows adjacent to c to accomplish the c to d transition. Alternate secondary assignments with the same pattern may be applicable when such a condition exists. For instance, the assignment in Fig. 17-17
such as in furnishing a
is
satisfactory.
Pattern
x xz
s
#6
is
unique in that
it is
applicable to any four-row flow table,
regardless of any type of cycle that
may be
prescribed.
00
01
11
10
3
1
/,/ 2
2
(2)
7v
y
00
a
01
11
10
00
a
1
01
II
10
e
7^
(3)4/
b
9
Figure 17-15
Figure 17-16
Figure 17-17
Chap. 17
HAZARDS
243
Hazards
The
physical devices used to implement switching circuits are not ideal
in the sense that the relationships

if if
X = 0,
X=l,
then then
X= X=
do not always
exist.
During
transition times, the relationships
or
X=X= X=X=
may briefly exist. Some examples
of the consequences, in sequential
circuits,
of the imper-
fection in devices will
now be
studied. Implementation of the expression
AB + AC
will
be used as a running example.
Example:
Consider the relay implementation in Fig. 17-18, in which the transfer A are of the break-before-make type. Assume a condition of relays B and C operated, and relay A changing state. The circuit is closed before and after the change, but for a brief interval of time during the transition of relay A, both the A and A contacts are open, and the circuit is therefore open. Such a false circuit condition
contacts on relay
is
called a hazard.
Circuit hazards are undesirable not only because of the

false
momentary
output conditions;
if
the hazard exists in a secondary excitation circuit,
the
more
serious consequence of incorrect circuit operation can result.
t~;j
Figure 17-18
t;i;x
Figure 17-19
The hazard
relationship
in the
above
circuit
can be eliminated by making use of the

(A
AB + AC =
when both
C)(A
B)
this
and implementing the circuit as in Fig. 17-19. With the A and A contacts are open during the
implementation,
transition of relay A,
244
Chap. 17
the circuit remains closed, a path being established through the closed
and
C contacts.
:
Example
Now
contacts
consider the relay implementation in 17-20 in which the transfer
on relay A are of the make-before break or continuity transfer type. Assume a condition of relays B and C unoperated, and relay A changing state. The circuit is open before and after the change, but for a brief interval of time during the transition of relay A, both the A and A contacts are closed, and the circuit is therefore closed.
TXT
Figure
B\A
17-20
Figure 17-21
This hazard can be eliminated by implementing the circuit as in Fig.

17-21.
With
this
implementation,
when both
the
A and A
contacts are
closed during the transition of relay A, the circuit remains open, the open
B
in
and C contacts preventing any path from being established. The two types of hazards just discussed are illustrated in timing charts Fig. 17-22. Note that the hazards actually exist only if the assumed
conditions occur.
Break-before-make Make-before-break
transfer contacts
transfer contacts
i
r
i
-I-/J
-&B-r-
Lj J -A CAB+AC
Circuit
output
U
No hazards
Hazards
TXT
(A+C)(A+B)
-A-t-A-
Circuit
output
n
No hazards
Figure 17-22
Hazards
Example:
Electronic implementation will
is
now be
considered, in which an inverter

is
used to implement
(Fig.
17-23). There
an inherent delay between
Chap. 17
HAZARDS
245
a change at the inverter input and the corresponding change at the inverter
output, as illustrated in the timing chart in Fig. 17-24
NOT
Figure 17-23
X
Figure 17-24
Implementation of either expression,
AB + AC
can
result in
or
(A
C)(A
B)
illustrated
one of the types of hazards previously discussed, as
in the timing charts in Fig. 17-25.
hazards.
Maps can be used in the identification and elimination of The map associated with the preceding examples
such possible
is
shown
in
Fig. 17-26.
The expression
Fig. 17-27.
AB + AC
not
in
is
obtained by grouping the
-squares as in
hazard can
states
exist
when a
the
circuit
between
two
same
change causes a movement group; for example, between
AND
not|^
I I
HnpLfc. j-1" AND

I
Circuit
l"^ output
U
Hazard
AB+AC
notI^
mLP
OR
OR
AND
Circuit
'output
Hazard
{A+C)(A+B)
Figure 17-25
AB
00
01
11
10
AB
00
01
11
1
10
10
/T\
CT ~7)
W
Haz ard
AB+AC
Fig ure
Figure 17-26
17- 27
246
Chap. 17
ABC = 011
exists, as
and
111, as indicated
can be eliminated by grouping the
by the arrows in Fig. 17-27. The hazard 1 -squares between which this movement
corresponding circuit in Fig. 17-28. The
shown
in the
map and
hazard
is
eliminated since the logic block corresponding to the term
BC
maintains the circuit output in the on state
when
BC =
11.
AB
00
01
11
A
10
AND
f\\
1
-NOT
A
AND
OR
CP 5 2/
AND
AB+AC+BC
Circuit with
hazard eliminated
Figure 17-28
approach can exist and 100, grouping

in
to
The expression (A + C)(A + B) is obtained by using the complementary and grouping the 0-squares on the map as in Fig. 17-29. A hazard in this case, when there is a circuit change between ABC = 000 as indicated by the arrows. The hazard can be eliminated by these 0-squares, as shown in the map and corresponding circuit Fig. 17-30. The hazard is eliminated since the logic block corresponding the factor (B + C) maintains the circuit output in the off state when
BC = 00.
To
eliminate hazards in sequential circuits, redundancy
is
thus some-
times required.
AB
Hazg rd
A
01
11
OR
00
10
AB
c
OCv'Ol
11
1
Lnot
10
OR
n
1
AND
(_
1 1
5>
1
/oV
OR 1
(A+C)(A+B)(B+C)
Circuit with
{A+CUA+B)
Figure 17-29 Figure 17-30
hazard eliminated
Another Example:
In Fig.
17-31,
if
a circuit
is
implemented from the expression

is
CD
+ BC + AD, a hazard can exist when there a circuit change between ABCD = 1000 and 1001, as indicated by the arrows. The hazard can be
eliminated by adding the term
AC
to the expression,
and implementing
CD + BC + AD +
AC.
Chap. 17
MOST-ECONOMICAL
CIRCUIT CONSIDERATIONS
247
If the circuit is
implemented from the expression (A
-f
-f
D){A
C)
(C
/)),
obtained by the complementary approach, Fig. 17-32, no hazard
can
exist.
AB
CD 00 <L A
01
1
AB
01
II
00
10
CD
00
Hazard
000 "
'
,0
1
K j>
/y
\1
01 (d\
1
10
10
W &
dN
oj
>
CD+BC+AD
Figure 17-31
(A+B+D){A+C){C+D)
Figure 17-32
Hazards may occur in secondary excitation (Y) or output (Z)

Before modifying a circuit to eliminate a possible hazard,
it
circuits.
should be
This
determined whether or not the corresponding condition can actually occur. is done by reference to the merged flow table with secondary assignflow table with secondary assignment
exist
ment, the primitive flow table, and the physical implementation. The merged may show that the hazard cannot
because the associated circuit change
if
is
can never occur.
On
the
other hand,
the change
table
the merged flow table indicates that the change

verified
may
occur,
in the
primitive flow table.
may show
that the circuit change can never occur

if it is verified
The primitive flow and that therefore
the hazard cannot exist. However, the type of change

Figs. 17-22
that the change can occur,
to
1,
to 0, or both
and
the states of the other
variables are correlated with the physical implementation (see, for example,
and
17-25) for the final determination of whether the condition
can actually occur.

If the condition
can never occur, then no hazard actually
exists. If
the
condition can occur, then the hazard must be eliminated.
ality,
The literals A, B, C, and D, used in this section, were chosen for generand may represent either x's or y's. The hazards discussed in this section are called static hazards. Other types
of hazards are discussed in the literature (see Related Literature section).
Most-Economical Circuit Considerations

There are many factors involved in obtaining the most economical circuit. Although it is generally desirable to remove all redundant stable states,
it
occasionally
is
economically advantageous to retain or even purposely
add redundant
states.
The choice of mergers can
affect circuit
economy,

248
Chap. 17
as can the secondary assignment for the assignment.
and the choice of optional
transitions
As
circuits
in the case of
any multi-output
circuit, the entire circuit
must be
evaluated as a whole, since the various secondary excitation and output
may be
able to share logic blocks or contacts in
common. When
ways of reading the maps, consideration should be given to the compatibility of expressions from an over-all circuit economy standpoint. The following example illustrates this point.
there are alternate
Example:
*1*2
k
00
01
It
10
OO
-
01
It
10
1 1
I
/-mop
y'
-
Z map
+ xz
*i x z
Z--y
x z (J,+/)
Figure 17-33
17-34.
The expressions above lead to The y contact in the output
the relay implementation

circuit
shown
in Fig.
if
can be eliminated, however,
the
alternate output expression
= * (*i + y)
2
is
used. This expression
is
identical to that for the secondary excitation,
and the same
circuit is thus
made
to serve
two functions
(Fig. 17-35).
*2
T]
i
vJUUL*
*i
i
>.
*\
Y
I
yJtSJU
*z
Figure 17-34
Figure 17-35
Illustrative
Problem
The following problem, from word statement to final circuit (Figs. 17-36 through 17-40), reviews some of the principles discussed. An electronic sequential switching circuit is to have two inputs, Xj and x 2 and one output, Z. Z is to turn on when Xj turns on; Z is to turn off when x 2 turns off.
,
Only one input can change
state at a time.
Chap. 17
MOST-ECONOMICAL
CIRCUIT CONSIDERATIONS
249
00
01
II
10
3 -
GMD
"
7
3 -
4 (3
" 2
8
7
Merger diagram
Figure 17-36
*\*Z
00
00
k,
01
11
10
01
II
10
1 1
00
4 4
3
,4
6
a b
c
7 2@
6
o_d_
1
01
1
\ K
r
2
10
Transition
map
Merged flow table

Figure 17-37
Flow table with sec ondary assignrr lent
Figure 17-38
*\*z
*\*i
/,/ 2
00
01
11
10
01
y yz 00
s
01
II
10
1
00 00 00
01 01
1
01
II 11
00
01
1
1
1 1
H
11
01
10
10
10 00 00 10 10
10
Y map
>W2/2+/l/2+*l/l
Z-Yz
(or
z--map
^x^+y\y
z ->rx 7L
yz
x,y
'
+ 7\Yz+ *zYz)
Figure 17-3 9
1 1
250
Chap. 17
X\
xz
Yz
/2
Delay
Yx
Delay
NOT
AND
AND
AND
OR
AND AND
1
OR
Circuit
diagram
Figure 17-40
PROBLEMS
1.
From
the flow tables in Fig. 17-41,
draw the Z-map and obtain the
output expressions.
*\*Z
"1*2 01
11
00
10
2-3 45 1
z,z?
10
1
/ X. 7
\
00
01
11
10
3
'z
00
01
1
7
2
(D
8
01
6
5
00 00
1
10

2
'
3 01
7 (6) 8
Fl
10
gure 17-41
*2.
Using another merger of the primitive flow table in Fig. 17-41, draw the Z-map and obtain the output expressions.
3.
A sequential
The output
circuit is to
is
to be
have two inputs, x and x 2 and one output, Z. on only when x x 2 =01, or when x^ 2 = 11 immet
Chap. 17
PROBLEMS
251
= 01. The output state is optional for x x = 11 immediately following x x = 00. All input changes are possible. Design
diately following
jc^
the circuit for electronic implementation.

*4.
A sequential circuits is to have two inputs,

2 2
x
x and x 2 and one output Z.

x
,
Z is to turn on when x turns on, provided that x is on at the time. Z is to turn off when x turns off. If x changes state simultaneously with
x
x 2 turning
possible.
on, the circuit action
is
optional. All input changes are
Design the
circuit for electronic
implementation.
18
Pulse-Input Sequential
Circuits
I
In preceding chapters, electronic sequential circuits of the level-input type were discussed. In these level-input sequential circuits, the memory and delay properties were realized by feedback paths, and level-outputs
were obtained. In
the
this
and the next chapter, pulse-input
electronic se-
quential circuits will be discussed. In these pulse-input sequential circuits,
memory and
delay properties are obtained with bistable electronic
devices called flip flops,
and pulse-outputs or level-outputs can be obtained. In level-input sequential circuits, a change in circuit state is initiated
level, that is,
by a change in input voltage ." or from "+" to "
a change from "
"
to
"+,"
In pulse-input sequential circuits, a change in circuit state is initiated by an input pulse a change from one voltage level to the other, followed by a return to the initial voltage level, the time during which the voltage deviates from the original level being of relatively brief duration compared with the time between deviations. For example, an input may normally be " " level, change to the "+" level, and after a relatively brief interval at the
:
252
Chap. 18
FLIP
FLOPS
253
of time, return to the

brief deviation to the
is
" " level. "+" voltage
This
level
Jl_
Positive pulse
called a positive pulse.
similar devia-
"If
Negative pulse
tion
is
from the
"+"
level to the
" "
level
Figure 18-1
called a negative pulse.
Flip Flops
flop is a "memory" device having two stable states which will be "on" and "off." A flip flop may have one, two, or three pulse-inputs and has two complementary /eve/-outputs, y and y. One of the flip flop outputs is at the "+" voltage level and the other is " " voltage level at any time. When the y output is at the "+" at the " " level, the flip flop is said to be voltage level, and the y output is at the "on"; when y is "-" and y is "+," the flip flop is said to be "off." A flip flop responds to pulses at the inputs. A flip flop will remain in a given state until a proper input pulse is applied; that is, an input pulse causes a flip flop to change its state from "off" to "on" or from "on"
flip
called
to "off."
Several types of
circuits will
flip
flops
be discussed
the set-reset or
S-R
flip
modifications shown.
and their applications in pulse-input sequential At this time, one common type of flip flop, flop, will be described in some detail, and some basic flip flop circuit is shown in Fig. 18-2. The
later.
S-R
flip
flop
Figure 18-2
Flip flops respond also to changes in input level, but this
mode
of operation
is
not
considered here.
254
Chap. 18
inputs are Xi and

is
x 2 and the outputs, y and y. Vacuum tube implementation

,
illustrated;
however, the
flip
flop can be similarly
implemented using
is
transistors.
At any given
time, one triode

is
is
conducting and the other triode
not.
When
level
the left-hand triode

is
conducting,
is
at the lower or
" "
voltage
on.
and y
at the higher or
is
"+"
voltage level, and the
flip flop is
When
the right-hand triode
conducting,
is
at the
" "
voltage level
and y is at the "+" voltage level, and the flip flop is off. The flip flop will not change its state until a pulse of the proper polarity is applied to one of its inputs. For example, assume the flip flop to be on. The left-hand triode is conducting and its plate is at the lower voltage
level.
Since the plate of each triode
is
cross-coupled to the grid of the other

is
triode, the lower voltage level at the plate of the left-hand triode
applied
The lower voltage level at the grid of the right-hand triode prevents this triode from conducting, and since it is not conducting, its plate is at the higher voltage level. The higher voltage
to the grid of the right-hand triode.
level at the plate
of the right-hand triode

flop
is
is
applied through the cross-
coupling to the grid of the left-hand triode, maintaining conduction in this

triode.
Thus, the
the
flip
is
in
a stable
state.
When
triode
is
flip
flop
in the opposite stable state, off, the right-hand

is
conducting and the left-hand triode

the
flip
not conducting.
flop to
Assume
on to
off,
flop to be on.
To
cause the
flip
change
state,
from
a negative pulse can be applied at the x x input, or a positive pulse
can be applied at the x 2 input. Assume, for the sake of example, that a negative pulse is applied at x This pulse momentarily causes the grid of
x .
the left-hand triode to go negative, preventing conduction in this triode.
The
plate of the left-hand triode goes positive,
and
this positive voltage is
applied to the grid of the right-hand triode, causing this triode to conduct.
Conduction through the right-hand triode causes its plate to go negative, and this negative voltage is applied to the grid of the left-hand triode, preventing this triode from conducting even though the negative pulse at the Xi input is no longer present. The pulse thus causes the flip flop to change its state from on to off. If the flip flop is on, a positive pulse at the x 2 input causes the same circuit action, and the flip flop turns off. If the flip flop is on, a positive pulse at the x input or a negative pulse at the x 2 input causes no change in the flip flop state, and the flip flop remains on. If the flip flop is off, a positive pulse at the x input or a negative pulse at the x 2 input causes the flip flop to turn on. If the flip flop is off, a negative pulse at x or a positive pulse at x 2 causes no change in the flip flop state, and the flip flop remains
x x
x
off.
summary of
the effects of positive and negative pulses at the two
inputs with the
flip flop initially in
each
state is given in the following table.
Chap. 18
FLIP
FLOPS
255
Initial state
of
flip
flop
ON
Negative pulse at Xi
or
Positive pulse at
OFF
Flip flop stays
Flip flop turns
x2
OFF
Flip flop stays
OFF
Flip flop turns
Positive pulse at Xi
or
Negative pulse at x 2
ON
ON
The symbol used shown in Fig. 18-3.
for the
S-R
flip
flop
is
5-/?
A
flip
pulse at the
(set)
input causes the

on, depending
Figure 18-3
flop to turn
on or
s,tay
upon
its initial state.
pulse at the
(reset)
input causes the

Fig. 18-2
flip
flop to turn off or stay off.
Which of
the inputs in
depends upon the polarity of the input pulses with positive input pulses, x would be labeled S, and x 2 would be labeled R; with negative input pulses, x 2 would
:
would be labeled S and which would be labeled
be labeled S, and x would be labeled R.

x
If,
in the flip flop circuit
shown
in Fig.
*
+,
18-2,
both
flip
grids
are
connected
input,
through
a trigger
capacitors
to
or
Figure 18-4
T
flip
flop results.
common An
input pulse to a
flop causes the flip flop to
change
state: if the flip flop is initially on, the pulse
will turn
it
off; if it is initially off, the pulse will
turn
it
on.
The symbol used
for a
If,
T flip
in
shown in Fig. 18-4. the circuit shown in Fig. 18-2, one of

flop
is
the cross-coupling resistors
removed, a mono-stable device called a single-shot or one-shot multivibrator results. The triode with the grid cross-coupled only by the capacitor is the one normally conducting. If, say, a negative pulse is applied to the grid of this triode, the circuit will change state only temporarily, and then return to its original state. The length of time that the circuit remains
is
in
its
unstable state
is
dependent upon the values of the

is
circuit
components.
The
single-shot multivibrator
useful for obtaining delays or for "pulse
stretching."
If both cross-coupling resistors are
removed (and the grid
resistors
and
the cathodes are placed at the same negative voltage), an unstable device
called a multivibrator results. This circuit requires
no
inputs, the circuit
continuously oscillating on and off as the triodes alternately conduct. The

length of time that the circuit remains in each state
is
again dependent
256
Chap. 18
upon
the values of the circuit components.
multivibrator
is
useful as a
pulse source.
Pulse-Input Sequential Circuits
schematic diagram of a pulse-input sequential circuit
is
shown
in
Fig. 18-5.
Note both the
similarities
and
differences
between
this
diagram
and the analogous one for level-input sequential circuits shown in Fig. 13-1. The sequential circuit inputs (x's) are in the form of pulses. The flip flops are the secondaries. The flip flop inputs (5"s, Ts, and i?'s) are in the form of pulses. Pulses at the flip flop inputs provide the secondary excitation. The flip flop outputs (/s and j's) are in the form of levels. The
states
of the
flip
flop outputs are the secondary states.
(x
1
* t1 "O
'
Inputs L. (pulses) 1 z
1/
Flip flop
Flip
Outputs
^Mpulses
inputs
or
flop outputs
(levels)
_ , *Z)
levels)
(pulses)
5,
r,
Flip
Combinational
circuit
*i
flop
'7
52
rz
/?2
h
Flip
flop
h
y
Flip
flop
y
"1
j~
^
<
_^-
Schematic diagram of pulse-input

sequential switching circuit
Figure 18-5
The
or they
circuits.
circuit input pulses
may be
directly applied to the flip flop inputs,
may be
switched with the

input might be
flip
flop outputs
through combinational
circuitry for
For example, a Boolean expression describing the

flip flop
pulsing a
=x + x y,y
l
'
Chap. 18
257
Since the
corresponding
form of pulses, every term in the must contain an "x." The sequential circuit outputs (Z's) may be in the form of pulses or levels. If pulse-outputs are specified, they are realized by switching together circuit input pulses and flip flop outputs. For example, an expression for a pulse-output might be
flip
flop inputs are in the
flip
flop excitation expression
Zi
=x
y y2
1
If level-outputs are specified, they are realized
by switching the
flip
flop
outputs only. For example, an expression for a level-output might be
Zj
=j!j
It is assumed that the duration of the input pulses is relatively short compared with the response time (delay) of the flip flops. Thus, an input pulse "initiates" a change of state of a flip flop, and this change occurs after the pulse has "come and gone." An input pulse to a flip flop may therefore be switched with an output on this same flip flop, the flip flop entering into
its
own
control.
Example:
AND
*1
OR
"
AND
-i
Figure
8-6
flop response time
The relative durations of input pulses and be depicted by the timing chart in Fig. 18-7.
flip
may
When
the
flip
flop
is
off (y
1),
y output, turns the

input pulse,
output, turns the
flip
flop on.
When
an x input pulse, switched with the the flip flop is on (y = 1), an x 2

r
switched with the y

flip
Input pulse /,
flop
off.
Note, by reference to the preceding

circuit
Input pulse xz
JL
JL
Off r
Output pulse
Flip
diagram and
timing
on
chart, that the output pulse
Off
is
flop
-I
coincident with an
ir-
input pulse
flop
is
-Ilk
(delay)
occurring
when
the
^Flip flop/
off,
flip
response time
even though
ates
same pulse the turning on of the flip

this
initi-
flop.
Figure 18-7
258
Chap. 18
Because of the relative durations of input pulses and

time,
flip
flop response
state
two or more flip flops may simultaneously be caused to change by the same input pulse without a concern about race conditions.
Example:
AND
r"
i
OR
OR
Figure 18-8
an x input pulse, switched with the y and on. Even if one flip flop responds faster y2 than the other, no race condition exists. For example, if it is assumed that
both
flip flops
When
are
off,
outputs, turns both
flip flops
flip
Input pulse
Flip flop
*{
flop
responds faster than

the
flip
#1
Off
On On
flop 2, the circuit action
may be
in
Flip flop
#2
Off
depicted by
Fig. 18-9.
timing chart
Response time of flipflop#1Response time

of flip flop
The problem of making secondary assignments to avoid critical

races
#2'
Figure 18-9
therefore
does not exist for

flip
these pulse-input sequential circuits

as
it
did for level-input sequential circuits, and the secondary or
flop
assignments can be arbitrary (although one assignment
may
lead to a
more
economical
circuit
than another).
is
Another assumption that

This time
is
made
is
that there
is
sufficient
time between
flop with the
successive input pulses for the flip flops to complete their change of state.
governed by the slowest
flip flop,
that
is,
the
flip
longest response time.
In circuits in which the preceding assumptions do not hold true, that

if
is,
flip
flop response time
is
shorter than the duration of an input pulse,

its
or
if
successive input pulses can occur before a flip flop has completed
state,
change of
the problem of critical races
and a
flip
flop
may
not be able to enter into
may have to be its own control.
considered,
Synthesis of Pulse-Input Sequential Circuits
The
steps in the synthesis of pulse-input sequential circuits are
summa-
rized below.
Chap. 18
FLOW DIAGRAM
259
(1)
The word statement of the problem is transformed into a flow table and usually also into a flow diagram. This flow table is different from the one used in the synthesis of level-input sequential circuits and rather more closely resembles the table used in the synthesis of reiterative circuits. The flow diagram contains the same information as the flow table, but permits a more graphic visualization of the
entire circuit operation.
(2)
The flow
table
is
tested for redundancy,
and any redundant
states
(3)
can be eliminated. A secondary assignment

of
flip
is
made
for the flow table, a combination
flop states being assigned to each circuit state.
(4) Flip flop excitation
maps
are obtained
differ
secondary assignment. These maps

regard to the entries.
flop inputs are
flops,
from the flow table with from the usual maps with
flip flip
The excitation expressions for pulsing the read from the maps. There are many types of
is
and for each type there
specific set
of rules for reading

table with
the maps.
(5)
The output expressions

secondary assignment.
are read directly
from the flow

excitation
(6)
The
sequential circuit
is
drawn from the
and output
expressions.
Before discussing the construction of a flow diagram or flow table from a word statement of a problem, the diagrams and tables themselves
will
be described.
Flow Diagram
In a flow diagram, each circuit state
is
represented by a circled arbitrary
number.
Example:
All circuit states are stable, and transitions from
state to state are effected
by input
pulses.
Each of

Figure
1
8-1
these transitions
is
represented on the
diagram by
transition;
an arrow labeled with the input pulse causing the the arrow leaves the circled number representing the "initial" state and terminates in the
circled
number
representing the "next" state.
Example:
The next
state
may be
the
same
as the initial state
for example, in Fig.
260
Chap. 18
18-11, if the circuit

in state
1
;
is
in state
is
if
the circuit
and an x 2 pulse occurs, the circuit remains and an x pulse occurs, the circuit remains in state 3. Note that, in the flow dia1
in state 3
gram, there
circled
will
be as
it
many arrows
is
leaving each
number
initial
as there are input pulses (unless

state
for
an
impossible for certain

is
input pulses to occur or the next state
optional).
If the outputs are pulses, they are associated
with certain transitions and the

input pulses; on the flow
corresponding
pulse-out-
diagram,
puts are labeled adjacent to the associated transiFigure
18-n
tion input pulse labels.
Example
In the example, a with an x

state 2,
x
output pulse
is
coincident
is
pulse occurring
when
is
the circuit
in
and a
output pulse
coincident with
is
an x 2 pulse occurring when the

3.
circuit
in state
If the outputs are levels, they are associated
with certain circuit states; on the flow diagram,

level-outputs are labeled adjacent to the associFigure 18-12
ated circuit state circled numbers.
Example:
Z,
Z,
01
)ZZ, =10
Figure 18-13
In Fig. 18-13, the
output
is
on when the
circuit is in state 3,
and the
output
is
on when the
circuit is in state 2.
Flow Table
flow table contains the same information as a flow diagram. There

state,
is
a row in the table for each circuit
and a column for each input
pulse.
Chap. 18
WORD
STATEMENT
261
Each
circuit state is assigned
an arbitrary number which
labels the corre-
sponding row. Each column
is
labeled with an input pulse.
Each row
label represents
an
the
initial state.
indicates the next state that will be reached
the state labeling that
row and
labeled
Each "entry" in the table when the circuit is initially in input pulse labeling that column occurs.
Pulse-outputs
are
adjacent
*i
to the entries corresponding to the as-
sociated
transitions.
Level-outputs are
xz
1 1
*\
xz
1
designated at the
right
of the rows
to
2
3,Z,
2 3 3
z,z2 00
01
labeled by the associated circuit states.
Flow
tables
corresponding
the
3
1,Z2
preceding two flow diagrams are shown

in Fig. 18-14.
10
Figure 18- 14
Word Statement
Flow Table
to Flow
Diagram and
In the construction of a flow diagram or flow table,

(a)
it
must be determined
how many
circuit states are needed,
and what
is
the associated infor-
mation pertaining to past input sequences leading to each of these states, and (b) with the circuit in each of these states, to which state will a transition occur upon receipt of any input pulse. (a), above, may be determined by the study of the problem statement, before starting the actual construction of the flow diagram or table, or it may
(b), by starting the construction with an and adding additional states as required by the indicated transitions. The latter method is more commonly used. The construction of a flow diagram and flow table from a word statement of the problem will now be illustrated by the use of some examples. The circuit requirements in the first four examples involve two pulseinputs, x and x 2 and one pulse-output, Z.
be determined concurrently with
initial circuit state
Example
An
output pulse
Z is
to be coincident with the
first
x2
pulse immediately
following an
pulse.
2
x
\
1,Z
Flow diagram
Figure 18-15
Flow table
262
Chap. 18
In this problem,
last
it is
sufficient to recognize
two
different conditions
the
input pulse that occurred was an Xt pulse, or the last pulse was an
x2
pulse.
Thus, two circuit states are required, and they are assigned as follows
1
:
the last input pulse was an the last input pulse was an
x2 x
t
pulse.
pulse.
An
output pulse
is
associated with an
x 2 input
pulse occurring
first
when
the
circuit is in state 2, since
such an x 2 pulse will be the
immediately
following an x t pulse.
It is
assumed
in this problem,
1
and
in all of the
is,
problems that follow,

the
that circuit state
is
the "power on" state, that

1.
when
power
is first
turned on, the circuit will be in state
In this example, the circuit states were assigned as shown, rather than
is an x 2 pulse, x pulse not being preceded by an a^ pulse. If the assignments had been made in the reverse order, and the first pulse was an x 2 pulse, an output pulse would occur.
in the reverse order, so that if the very first pulse to occur
no output pulse
will occur, this
If the
problem statement were revised to read, "An output pulse

first
is

state assignments
if
of a sequence of consecutive x 2 pulses," the
the
first
pulse were an
would be made in the reverse order (Fig. 18-16) so that x 2 pulse, an output pulse would occur.
*z
>=?=>
2
2,Z
2
Flow diagram Figure 18-16
Flow table
Once the
circuit is
"in operation," both assignments give the
same
pulse.
circuit action ; in other
words, both problem statements are equivalent except

first
for the output requirement of the very
input pulse
if it is
an x 2
initial
In pulse-input sequential circuit design, the assignment of circuit state

1
is
frequently determined by the output requirements of an
input
sequence.
It is
suggested that, for practice, the reader draw his

tables for the examples that follow,
own
flow diagrams
his results
and flow
and then compare
with those given.
Example 2
An
output pulse
Z is
to be coincident with the second of a sequence of
consecutive
pulses immediately following an
pulse.
Chap. 18
WORD
STATEMENT
263
Flow diagram
Flow table
Figure 18-17
There are three conditions that must be recognized in this problem: the input pulse was an Xi pulse; the last input pulse was the first x 2 pulse immediately following an jc pulse; the last input pulse was an x 2 pulse other than the first immediately following an x pulse. Thus, three circuit states are required, and they are assigned as follows:
last
x x
the last input pulse was an
x 2 pulse other than the
first
immediately
following an x x pulse.
2: the last input pulse
was an Xi pulse. was the first x 2 pulse immediately following an
Xi pulse.
An
output pulse
is
associated with an
x 2 input pulse occurring when the
such an x 2 pulse will be the second consecutive

x
one immediately following an x pulse. Again, circuit state 1 was assigned so that if the first two input pulses were x 2 pulses, no output pulse would occur coincident with the second x 2 pulse. If the problem statement were revised to read, "An output pulse Z is to be coincident with the second of a sequence of consecutive x 2 pulses," the state assignments would be reordered as in Fig. 18-18.
*2
3,Z
3
Flow diagram
Flow table
Figure 18-18
Example
An
output pulse
Z is to
be coincident with the

Xi pulses.
first
x2
pulse immediately
following two or
more consecutive
264
Chap. 18
*z
1
2 3
\,Z
Flow diagram
Figure 18-19
Flow table
Three conditions must be recognized in

pulse was an
this
problem: the
last
input
x2
pulse; the last input pulse
consecutive x t pulses; the last
was the first of a sequence of input pulse was the second or more of a
sequence of consecutive *i pulses.
The
1
:
three required circuit states are assigned as follows
the last input pulse was an
the last
x 2 pulse. was the first of a sequence of consecutive x pulses. input pulse was the second or more of a sequence of con1
secutive *! pulses.
An
output pulse
is
associated with an
x 2 input pulse occurring when the

first
such an x 2 pulse will be the

x
one immediately
following two or
more consecutive x
pulses.
Example 4:
An
output pulse
Z is
first
x 2 pulse immediately
following exactly two consecutive Xi pulses.

XZ
X
i
xz
4
4
Flow diagram Figure 18-20
1.Z
I
Flow table
Four conditions must be recognized and their assigned circuit states are
1
:
in this
problem; these conditions
the last input pulse was an the last input pulse was the
x2
pulse.
2
3
first
of a sequence of consecutive x pulses.

t
the last input pulse was the second of a sequence of consecutive

pulses.
the last input pulse was the third or

Xi pulses.
more of a sequence of consecutive
::
Chap. 18
WORD STATEMENT
associated with an
265
An output pulses is
is
x 2 pulse occurring when the

be the
first
circuit
fol-
in state 3, since such
an x 2 pulse
jc x
will
one immediately
lowing exactly two consecutive
pulses.
The
inputs,
circuit
t
requirements in the next two examples involve two pulse,
x and x 2 and one

5
is
level-output, Z.
Example
If the If the
output
is
off
it
(Z
is
= 0),
it is
to turn
on (Z
1)
with an x 2 pulse.
output
on,
to turn off with the second of a sequence of
consecutive x t pulses immediately following an
x2
pulse.
No
other input
sequence
is
to cause any change in output.
Z=0
z--\
Flow table
Three conditions must be recognized these conditions and their assigned

;
circuit states are

1
:
3:
Z = 0. Z= Z = 1.
1
.
The The
last last
input pulse was an
pulse.
x
input pulse was an x
pulse
the
first
following an
x2
pulse.
Example 6
If the
output
is off, it is is
to turn
on with the
first
of a sequence of x 2
to cause any change
pulses. If the output
on,
it is
to turn off with the second of a sequence

is
of consecutive x 2 pulses.
in output.
No
other input sequence
z=o
Z=l
*\
*Z
<LJ
1
1
2 3 3
2
*z
4
1
*z
3
'
X>2
Z=
z=o
Flow diagram
Flow table
Figure 18-22
266
Chap. 18
Four conditions
states, follow:
1
:
that
must be recognized, and
their assigned circuit
2:
Z = 0. Z = 1.
The The
The
last pulse last
was an x pulse occurring when Z = 0. pulse was an x 2 pulse the first of a sequence of
t
consecutive
3
:
pulses.
Z = 0.
Z=
1.
last pulse
was an x 2
pulsethe
second or more
Oi*
sequence of consecutive x 2 pulses.

4:
The
last pulse
was an x pulse occurring when

t
Z=
1.
Many
of these examples
will
be used in
later discussions.
Elimination of
Redundant States
redundancy may inadvertently be circuits, redundant
As
states
in level-input sequential circuits,
introduced in
the
design
of pulse-input sequential
being present in the flow diagram or flow table.
The concepts of equivalence and pseudo-equivalence in pulse-input sequential circuits are basically the same as those for level-input sequential circuits, and reference should be made to Chapter 14, in which the subject is covered more thoroughly. The concepts are restated briefly here.
Two
(1)
circuit states are equivalent if:
The output
conditions, pulse or level, associated with both states
(2)
and For each possible input pulse there to the same or equivalent states.
are the same,
is
a transition from these states
If
two
states are equivalent,
one of them
is
redundant and
all
1
may be
eliminated.
only a portion of the flow table
Following are shown some basic examples of equivalence. In is shown, and in all examples,
examples,
2.
(1)
1
Xi
x%
3
4 4
3 3
(2)
1
Xi
1
1
x%
Xi
x%
3,Z 3,Z
3,Z
(3)
1
Xi
X*
3 3
X\
x$
3
2,Z 2,Z
1,Z
Chap. 18
ELIMINATION OF REDUNDANT STA TES
267
(4)
X\
x%
X<l
7
1
1
Z
=
1
1
3
3
(5)
Xi
X<l
X\
x%
7
1
z
=
1 1
2
1
3 3
1
1
in all five
Following the practice of retaining the smaller-numbered circuit state, examples every occurrence of a 2 is replaced by a 1. The two
rows then become identical and are replaced by a single row. The requirements for equivalence can also be stated in another way two circuit states with the same output conditions can be made equivalent unless the equivalence depends upon a nonequivalence. (Note the interdependence of the the equivalence in the fourth and fifth examples.) An example with equivalence follows.
:
Example:
A pulse-input sequential circuit is to have three inputs, jc 1} x 2 and x 3 and one pulse-output, Z. The output pulse is to be coincident with the first x 2 pulse immediately following either an Xj pulse or an x 3 pulse. A flow diagram and flow table for this circuit requirement are shown
, ,
in Fig. 18-23.
Examination of the flow table shows that

for each input pulse there
is
states 2
and
3 are equivalent
since the output conditions associated with both states are the same,
and
a transition from these states to the same

table are
state.
The reduced flow diagram and flow
shown
in Fig. 18-24.
x,,Z
1
'i
xz
1
x 1>
2 2
2
2 3
l,Z 3
l,Z
3
x,,Z
*3 Flow diagram
2
Flow table
1,Z 2
Flow diagram
*3
Flow table
Figure 18-23
Figure 18-24
Two circuit states may be equivalent both of the following conditions
in all respects except for
one or
268
Chap. 18
(1)
For a given input

second circuit state
pulse, there
is
circuit states to a prescribed state,

is
a transition from one of these whereas the transition from the
optional.
is
(2)
An
output condition associated with one of these circuit states

optional.
exists,
prescribed, whereas for the second circuit state, the corresponding
output condition
If either
is
of the above conditions
the
two
circuit states are said to
be pseudo-equivalent, and can be considered as equivalent.
Some
basic examples follow. Again, only a portion of the flow table

1
is
shown and
= 2 in
all cases.
(1)
Optional transition
Xi
x2
3
Xi
x%
3
A,Z A,Z
(2)
4,Z
Optional output
Xi
*2
3 3
Xi
X%
3
4,Z
4,Z
4,
(3)
Optional output
Xi x% Xi
Xz
Z
4 4
3 3
Z
4
3
made
In the next example, state reduction requires that a circuit state be equivalent to two other circuit states which themselves are
nonequivalent.
Xi
x2
Z
2
1
3
3
1
States
if
states 2 and 3 can be

is
however,
States 1 and 3 can be made equivalent made equivalent. The equivalence of states 2 and 3, dependent upon the equivalence of states 1 and 3. Therefore, the
and 2 are nonequivalent.
Chap. 18
SECONDARY ASSIGNMENT
269
equivalences
=3
and 2
=3
can be made, and the flow table reduces to
X\
x%
Z
2
1
2
2
1
Secondary Assignment
In making a secondary assignment for a flow table, each circuit state
assigned
is
some combination of
flip
flop states. Since race conditions are of
no concern, the assignment can be arbitrary. For two circuit states, only one flip flop is required, its "off" state being assigned to one circuit state, and its "on" state to the other. Two flip flops
are required in circuits having three or four states; three
sufficient for
flip
flops are
up
n
to eight circuit states;
circuit states,
flip flops
and so forth. In m. are required, where 2 n
general, for
more economical
other.
one assignment may lead to a is no need to try all possible assignments, however, since many of them are trivial variations of each
Although the assignments are

circuit
arbitrary,
than another. There
For example, with four
circuit states, there are twenty-four possible

trivial variations
assignments but only three need be tried, there being eight
of each of the three.

is
An
arbitrary set of three nonequivalent assignments
shown
in the following table.
#1
y\yt
1
#2
Jiâ
#3
JiJa
00
01
11
00
01 10
11
00
11
2
3
01
10
10
By interchanging
assignments
is
flip flops,
an alternate for each of the three above
obtained
J'lJ'l
1
yiy*
yiy 2
00
10
11
~00
10
01
11
00
11
2
3
10
01
01
270
Chap. 18
By interchanging the on and off states of one or both flip flops, three more variations can be obtained from each of the six assignments above,
accounting for
all
possible (24) assignments.

x
circuit
y y 2 = 00, will arbitrarily be assigned to "power on" state, and furthermore, only the three 1, assignments #1, #2, and #3 will be considered throughout the rest of
The
"all flip flops off" state,
state
the
this chapter.
Three examples of flow tables with secondary assignment are shown in 18-25 through 18-27. Note how these flow tables differ from those used in the synthesis of level-input sequential circuits. In the next section, these examples will be used to obtain flip flop excitation maps. Note, in Fig. 18-27, that there are only three circuit states, and that flip
Figs.
flop
state
y yz
x
y y 10 row
x
10 never occurs. Dashes are therefore entered in the
as optional entries.
*\
*z
1
*1
*z
00
01
1
01
11
00
00
i,z
1
10
10
oo.z
10
00
-#-1
Flow table from example \ 4
Figure 18-25
*\
*2
\
v*
1
<*i
xz
00
1
00
00
00, z
2 3
01
4 4
\z
1
01
10
10
10
00
#3
Figure 18-26
*z
1
*z
00 00
01
1
1
01
3
1
2
2
01
00
01
10 -Flow table from example \ 5
Flow table with secondary assignment #1
Figure 18-27
Chap. 18
PROBLEMS
271
2,"
In general, for an r-row flow table which requires n flip flops, where n n n possible r)! ways of selecting r out of the 2 r, there are 2 !/r!(2 m
>
combinations. For each of these ways, there are r! permutations of assigning the r combinations to the r rows, making the total number of possible
assignments
2 n !r!
r!(2"-r)!
For each of these assignments there are 2n ways of interchanging the on and off states of the flip flops and there are n! ways of interchanging
flip flops.
There are thus

2"!r!
(2"table.
1)!
r!(2"-r)!2 n -!
non-trivial assignments for
(2"-r)!!
an r-row flow
Some
values are tabulated below.
n
1
Number
of non-trivial assignments
1
2
3
2
2
3
3
3 3
4
5
140
6
7
8
420
840 840
10,810,800
3 3
PROBLEMS
1.
Draw
ment:
a flow diagram and flow table for the following circuit require-
A sequential circuit is to have three pulse-inputs x u x 2 and x 3 and two pulse-outputs Z and Z 2 The Z pulse is to be coincident with the first x 2 pulse immediately following an j^ pulse. The Z 2 pulse is to be coincident with all consecutive x 2 pulses immediately following an x 3 pulse.
x
.
2.
Draw
ment:
a flow diagram and flow table for the following circuit requireA sequential circuit is to have two pulse-inputs Xj and x 2 and one
pulse-output Z.
consecutive
Xi pulses.
jc 2
The
Z pulse
is
to be coincident with the second of
pulses immediately following exactly
two two consecutive
272
Chap. 18
3.
Draw a flow diagram and flow table for the following circuit requirement: A sequential circuit is to have two pulse-inputs x and x 2 and one pulse-output Z. The Z pulse is to be coincident with the third and any further consecutive x 2 pulses immediately following exactly three
x
consecutive
*4.
pulses.
Draw
ment:
a flow diagram and flow table for the following circuit require-
sequential circuit
is
to have
two pulse-inputs x and

t
jc s
and
one pulse-output Z. The

secutive
Xi pulses.
Z pulse is
to be coincident with the third con-
pulse immediately following three or
more consecutive
19
Pulse-Input Sequential
Circuits
II
Flip
Flop Excitation
Maps
In the next step of the procedure, flip flop excitation maps are drawn from the flow table with secondary assignment. The expressions for pulsing the flip flop inputs are read from these maps. A map is drawn for each combination of circuit pulse-input and flip flop. For example, if there are two circuit inputs, say x and x 2 and three flip
t
,
flops required, six
maps
are drawn.
It is
convenient to arrange the maps

in the
so that
all
and
all
maps corresponding to a particular flip flop are maps corresponding to a particular circuit input
all flip flops
are in the
same row, same
column.
The outputs of
are variables for

is
all
maps. In addition, the
circuit pulse-input defining a
map
a variable for that map.
set
of maps for three
flip flops
FFU FF
and
FF
3,
and two
circuit
pulse-inputs
x and x 2
x
is
shown
in Fig. 19-1.
273
274
II
Chap. 19
*z
y '6
00
01
10
h
1
00
01
11
10
FF
1
y,yz
y,y z
01
1
00
10
00
01
10
/,/2
00
01
11
10
00
01
11
10
FF*
Figure 19-1
Map
Entries
flip
The
entries
flop excitation
maps
differ
of there being only three possible entries,
from the usual maps in that instead there are five possible 0, and 1
,
1, 0,
1,
0,
map entry represent an map entry represents an

flop
The
flip
flop output states defining a particular
initial state.
The
circuit pulse-input defining that
input pulse occurring
when
the circuit
is
in the defined initial state.

flip
Consider a
map
associated with a particular
and
pulse-input.
If the flip flop is 0#for an initial combination of flip flop output states, and following the input pulse, turns on, the corresponding map entry is
a large one
(1).
is initially
If the flip flop
on,
is
and following the input

a large zero
(0).
pulse, turns off, the
corresponding
map
entry
and following the input the corresponding map entry is small a one (1).
If the flip flop is initially on,
pulse, remains on,
If the flip flop
is initially off,
and following the input

is
pulse, remains off,
the corresponding
map
is
entry
a small zero
(
(0).
).
An
optional entry
indicated
by a dash
An
optional entry
may
Chap. 19
MAP
ENTRIES
275
arise because a certain
combination of
initial flip flop
flip
flop states can never occur; or
because for a certain
state,
a particular input pulse can
never occur; or because for a certain
initial flip flop state,
we don't
care
what the
circuit action is for
a particular input pulse.

flop being represented
The map
on state by a
entries for
each possible circuit action are summarized in the

flip
following table, the off state of a

1.
by a
Xr> x z
0,
and the
X. *,
Circuit action
Map
entry
00 00 01
01
1
0->-l
1
01
01
--
->0
00
--
-H
10
1
Flow table
0-*0
Optional
flop excitation
from example \ 5 Secondary assignment

Figure 19-2
#1
As an example,
Refer to the
is y\y<i
flip
maps
will
be drawn from the flow

initial flip flop state
x
table with secondary assignment

first
in Fig. 19-2.
table, in
row of the flow

x
which the
= 00.
If
an x pulse occurs, the new

flip flop
1,
flip
flop state
circuit action
final
of
that
is,
the transition
is y y % = 00. The from the initial to the
output
is
state,
can be represented by
entry
therefore 0.
The
entry
first
circuit action
is
* 0, and the corresponding map 0, and the of flip flop 2 is also

*
corresponding
Still refer
x
map
(Fig. 19-3).
row of the flow table, in which the initial flip flop an x 2 pulse occurs, the new flip flop state is y y = 01. y y2 The circuit action of flip flop 1 is > 0, and the map entry is 0. The circuit * 1, and the map entry is 1 (Fig. 19-4). action of flip flop 2 is
to the
state is
= 00.
If
9j
X\
xz
y\
1
1
X\
xz
1
'2
h
1
^
1 1
Jf
1
1
'a
>2
J*. 7 2
FF z
1
1
1
FF t
Figure
1<9-3
Figure \\>-4
276
II
Chap. 19
Now
y y2
x
refer to the
is
2
second row of the flow table, in which the

If
initial flip
is
flop state
y^y =01.
an x
of
pulse occurs, the

flop
>
new
flip
flop state
is 1. 1, and the map and the map entry is 1 (Fig. 19-5). Still refer to the second row of the flow table, in which the initial flip flop state is y y 2 =01. If an x 2 pulse occurs, the new flip flop state is y^y 2 = 01. The circuit action of flip flop 1 is 00, and the map entry is 0. The > 1, and the map entry is 1 (Fig. 19-6). circuit action of flip flop 2 is 1
11.
The
circuit action
flip
1
The
circuit action of flip flop 2 is
entry
is
1,
y\
1
y\
1
FF.
1
1
FF
1
y\
1
yz
1
FFo
\
FFn
1 1
Figure 19
Figure 19-6
row of the flow table, in which the initial flip flop pulse occurs, the new flip flop state is y y 2 = 00. an x y y2 The circuit action of both flip flops is 1 > 0, and each corresponding map
Refer
is
now
to the third
11. If
state
entry
is
(Fig. 19-7).
Still refer
to the third
flop state
row of
is
the flow table. If an
x 2 pulse occurs when

is is
the initial
flip
y y2
x
=
1
The
circuit action
flip
of
flip
is
1
flop
1 is
11, the
new
flip
flop state
action of
flop 2
0,
and the map entry

is
1.
0-
y y t =01. The circuit

x
1,
and the map entry
FF,
1
FF,
y<
1 1
y\
1 1
FF*
i
FF n
1 i
Figure 19-7
Figure 19-8
Chap. 19
MAP
ENTRIES
277
Since the
table),
all
y y
x
10
flip
flop state
is
optional (refer to fourth

are
corresponding
map
entries
's.
row of flow The completed flip flop

flop excitation
Figs.
excitation
maps
are
shown
in Fig. 19-8.
For practice, it is suggested that the reader draw flip maps from the flow tables with secondary assignment in 19-10, and compare his results with the maps shown.
19-9
and
*2
*\
v. v..
*z
0__0
FF,
00
01
1
01
11
00
00
00,
10 10
z
1
10
00
1
Flow table from example \ 4 Secondary assignments
FFo
^ 1
1
o~~o
maps
Flip tlop excitation
Figure 19-9
*z
*\
'\
*z
V. K '2
00
1
00
1
FF.
01
00
00,
01
10
z
1
y>
1
10
10
00
1
FF,
i
Secondary assignment#3
Flip tlop excitation
maps
Figure 19-10
Note that with regard to flip excitation, the maps contain the same information as the corresponding flow table with secondary assignment. The information as contained in the maps is simply in a different and more useful form. The information pertaining to the outputs is retained in the flow table. The three flip flop excitation map sets obtained in this section
will
be used as examples in the next section.
278
II
Chap. 19
Reading the
The
Flip
Flop Excitation
Maps
flop inputs are read
will
expressions for pulsing the

flip flops
flip
from the maps.
There are many types of

type there
is
a specific
set
be discussed, and for each of rules for reading the maps.
which
The advantage of the method presented here is that only one map set need be drawn. The flip flop excitation expressions for all types of flip flops can then be read from this map set merely by following the rules for each type of flip flop. In other methods, a map set must be drawn for each type
of
flip
flop considered, each type having a specific set of rules for going
table to the maps.
from the flow
flip flops will be discussed: S-R, S-R-SR, T, S-R-T, and S-R-SR-T. Their operating characteristics will be analyzed, and from these characteristics their input pulse requirements will be obtained. From the input pulse requirements, their map-reading rules will be derived. The method is general, and is adaptable to any other type of flip flop
Five types of
as well.
S-R
Flip
Flop
The S-R flip flop has two inputs S^set) and i?(reset). If the flip flop is off, a pulse on the S input will turn it on; a pulse on the R input will cause no change. If the flip flop is on, a pulse on the R input will turn it off; a pulse on the S input will cause no change. The S and R inputs of this flip flop must never be
:
S-R _
y
pulsed simultaneously, since the resulting

cuit action
is
cir-
indeterminate.
These operating
characteristics are
summarized in the follow-
Figure 19-11
1
ing table. In the "Input" columns,

represents input pulsed
represents input not pulsed
Where no
allowable.
circuit action is indicated, the
corresponding input pulsing
is
not
Input
0-+0
1
-+1
0-*
1
-+1
0-^0
1^0
S-R
flip
flop
Operating characteristics
Chap. 19
READING THE
FLIP
FLOP EXCITATION MAPS
279
Based on the preceding operating

notation for input pulse requirements
characteristics, the
S-R input pulse
requirements for each possible circuit action are obtained. The following
is
used
1
Input must be pulsed Input must not be pulsed Input
may
or
may
not be pulsed
Map
entry:
Circuit action
The S input must be pulsed. The R input must not be pulsed.
Circuit action:
Map
entry
The R input must be pulsed. The S input must not be pulsed.
Circuit action
Map
entry:
The S input may or may not be pulsed. The R input must not be pulsed.
Circuit action:
Map
entry:
The R input may or may not be pulsed. The S input must not be pulsed.
Circuit action:
Optional
or
Map
entry:
Any
input
may
may
not be pulsed.
The S-R input
pulse requirements are summarized in the following table.
280
II
Chap. 19
Input
Circuit action
Map
entry
0
1 1
-+0

flop
0^0
Optional
S-R
flip
Input pulse requirements
The map-reading
rules for the
S-R
flip
flop can be read
from
this table
Every 1 must be accounted for in the expression for pulsing the
input. input.
Every

or
in the expression for pulsing the
Any Any
or
may be used optionally in the S input expression. may be used optionally in the R input expression.
it is
In the examples that follow,
suggested that, for practice, the reader

flip
obtain the expressions for pulsing the

results
flop inputs,
and compare
his
with those given.
Example
FF
1
i
FF,
i
Flip flop excitation
maps
-#-1
from example
4.
Secondary assignment
Figure 19-12
Reading the
the
FF maps
l
for
an S-R
Sx
flip flop,
the expression for pulsing
S input
is
= x^
Chap. 19
READING THE
FLIP
281
and the expression
for pulsing the
R input
is
Rl
=X
Reading the
FF maps
2
for
an S-R
flip flop,
Rz
= Xip! -^l^l +
-*2
Example
o__0
FF
t
o~|~0
FE>
i
o~~o
maps
}
from example
4.
#3
Figure 19-13
S-R
flip flops:
^1
R2
= XlJ'lJ's + *2 = XjJ =xyy +x

2
1
S-R-SR
Flip
Flop
S-R-SR
y
Figure 19-14
The S-R-SR
flip
flip
flop has the
same operating
characteristics as the
S-R
one exception: the S and R inputs may be pulsed simultaneously, in which case the flip flop will change state. These operating characteristics are summarized in the following table.
flop with
282
II
Chap. 19
Input
Circuit action
1 1
01 0-0
0*1
flip
1>1 1*1
10
1>0
S-R-SR
flop
The S-R-SR input

Circuit action:
pulse requirements are:
Map
pulsed.
entry:
The S input must be pulsed. The R input may or may not be
Circuit action
>
Map
pulsed.
entry:
The R input must be pulsed. The S input may or may not be
Circuit action:
> 1
Map
not be pulsed.
pulsed.
entry:
The 5 input may or may The R input must not be
Circuit action:
Map
pulsed.
entry:
The R input may or may not be The S input must not be pulsed.
R
Map
pulsed.
Circuit action: Optional
entry:
Any
input
may
or
may not be
Chap. 19
READING THE
FLIP
FLOP EXCITATION
MAPS
283
The S-R-SR input

table.
pulse requirements are summarized in the following
Input
Circuit action
Map
entry
01
1-^0
1
Optional
S-R-SR
flip flop
The map-reading
table:
rules for the
S-R-SR
flip
flop can be read
from
this
Every 1 must be accounted for in the

Every
S input
expression.

1,
in the
R input expression.
Any Any
0,
or or
1, 0,
may be used optionally in the S input expression. may be used optionally in the R input expression.
Example:
A
"o|0
1
FF
FFo
i
V~6
maps
I 4.
from example
Secondary assignment #-3
Figure 19-15
S-R-SR
flip flops:
284
II
Chap. 19
Rl
R'2
Xj = ^1^2 =xy = *lJPl

r
H~
4" ^2
Example:
*z
FF,
FF9
i
maps
from example
5.
Secondary assignment -#M
Figure 19-16
S-R-SR
flip flops:
=x
y2
-^2
R-l
>J2
== X\ T" == ^2
R =
2
xtft
Flip
Flop
The Tflip
the
flip
it
flop has
one input:
flop
is
flop
is off,
a pulse on the
flip
it
T (trigger). If T input will

on the
turn
on. If the
will turn
on, a pulse
T input
table.
off.
These operating charin
acteristics
Figure 19-17
are
summarized
the
following
Input
0-^0
1
01
T flip
flop
1>0
Chap. 19
READING THE
FLIP
285
The
T input
pulse requirements are
Circuit action:
Map
pulsed.
entry:
The T input must be
JL
1
Circuit action
Map
pulsed.
entry
The T input must be
JL
1
Circuit action:
> 1
Map
pulsed.
entry:
The T input must not be
JL
o
Circuit action:
Map
pulsed.
entry:
The T input must not be
JL
Map
pulsed.
entry:
The T input may or may not be
The T input
pulse requirements are summarized in the following table.
Input
Circuit action
Map
entry
0*1 1>0
1
Optional
T flip
flop
The map-reading
rules for the
flip
flop can be read
from
this table
286
II
Chap. 19
Every 1 and
in the
T input
expression.
Any
may be used optionally in the T input expression.
Example:
*z
0_J)
1
\
FF
o|0
1
Ft,
1
maps
-#-1
from example
4.
Figure 19-18
T flip
flops:
T = Xtpipt +
2
îîâ
+xy
2
Example:
FF.
1
1
1 1
FF,
i
maps
from example
4.
Secondary assignment #-3

Figure 19-19
Chap. 19
READING THE
FLIP
287
T flip
flops:
T =
x
Xxpi
x
T =xy
2
+xy +x + x,y
x
Note that the term x y

x
need be implemented only once,
this
implemen-
tation being used in both the
and
circuits.
S-R-T
Flip
Flop
The S-R-T flip flop has three inputs S, R, s y and T, and has the combined operating characT S-R-T teristics of the S-R flip flop and the T flip flop. R y If the flip flop is off, a pulse on the S input or Figure 19-20 T input or both will turn it on; a pulse on the R input will cause no change. If the flip flop is on, a pulse on the R input or T input or both will turn it off; a pulse on the S input will cause no change. The S and R inputs of this flip flop must never be pulsed simultaneously, since the resulting circuit action is indeterminate. For the same reason, the S and T inputs must never be pulsed simultaneously when the flip flop is on, and the R and T inputs must never be pulsed simultaneously when the
flip
flop
is off.
These operating characteristics are summarized in the following
table.
Input
Circuit action
0^0 0^1
1 1
0->0 0-^1
0
-*0 -+0
> 1
S-R-T flip
flop
The S-R-T input
pulse requirements are
288
II
Chap. 19
Circuit action:
* 1
Map
entry:
Either the
or
T input
must be pulsed; the other may or may not be pulsed.
The
input must not be pulsed.
s
1
Circuit action
:
Map
be pulsed; the other
entry:
Either the
or
T input must
may
or
may
not be pulsed.
The S input must not be
pulsed.
R
1
Circuit action
:
>
Map
entry:
The S input may or may not be pulsed. The R input must not be pulsed. The T input must not be pulsed.
Circuit action
>
Map
pulsed.
entry:
The R input may or may not be The S input must not be pulsed. The T input must not be pulsed.
Map
entry
Any
input
may
or
may
not be pulsed.
The S-R-T input

table.
Chap. 19
READING THE
FLIP
FLOP EXCITATION
MAPS
289
Input
Circuit action
Map
entry
S
1
1 1
0-^1
1^0
1-^1
1
o-o
Optional
S-R-T flip
flop
The map-reading
rules for the
S-R-T flip
flop can be read
from
this table:
Every 1 must be accounted for either in the

input expression.
input expression or the
T
T
Every
either in the
R input
expression or the
input expression.
Any Any Any

the
1 accounted for in the

5"
input expression, or any

expression, or any
or
may be
may be
used optionally in the
input expression.
accounted for in the
T input
or
used optionally in the
R input
expression.
R input
accounted for in 1 accounted for in the S input expression, any expression, or any may be used optionally in the T input
expression.
Example:
o__0
FF
t
o__0
FF
1
o"~o
mops
from example
4.
#1
Figure 19-21
290
II
Chap. 19
S-R-T flip
flops:
Rj
= x,y =x r = (unused)
S
t
R2
2
= x iyi + x T = (unused)
input,
or
=xy K =x T = x y\y
S
2
l l
it can be turned on by can be turned off" by pulsing the R or T input. Often, advantage can be taken of this "built-in" or characteristic to achieve greater circuit economy. An example of this is illustrated in the excitation of FF2 above. The first
The S-R-T
flip
flop has the characteristic that
pulsing the
or
and
it
solution can be implemented with
two and
circuits
and one or
circuit.
The second
solution
may be more
or
economically implemented with two
and
circuits, the inherent
characteristic of the
S-R-T
flip flop
being
utilized.
As
illustrated in this example,
it
may sometimes be
desirable to use
larger terms in order to take advantage of the built-in
or
characteristic:
X1.y1.y2 in
note the term x^y
in the first solution, versus the
term
the
second solution.
Example:
o__0
FF,
o|0
1 1
FF,
1
~0
maps
$ 4.
from example
Secondary assignment -#3
Figure 19-22
Chap. 19
READING THE
FLIP
291
S-R-T flip
flops:
=xy
}
R =x T = x,y
x
or
2
=xy Ri = x T = x,y
Si
x
= (unused) = X ^2 T =xy
S
2 2 2
l
l
The
circuit,
first
solution for the excitation of FF^ leads to a

x
more economical
this imple-
term x y need be implemented only once, mentation being used in the S and T2 circuits.
since the
x
v
S-R-SR-T
Flip
Flop
The S-R-SR-T flip flop has the same operating characteristics as the S-R-T flip flop with one exception: the S and R inputs may be pulsed simultaneously, in which case the flip flop will change state. The S-R-SR-T flip flop thus has the combined operating characteristics of the S-R-SR flip flop and the T flip flop. When the flip flop is on, the S and T S y inputs must never be pulsed simultaneously
unless the
flip
input
off,
is
also pulsed.
When
the
S-R-SR-T
y
flop
is
the
and
R
Figure 19-23
inputs must
never be pulsed simultaneously unless the

input
is
also pulsed.
table.
These operating characteristics are summarized in the following

Input
Circuit action
0>0
1
0-^1
1
0-^0
1
1-0
1
01 01
0-*l
01
flop
1-0 1-0 1-0
S-R-SR-T flip
292
II
Chap. 19
The S-R-SR-T input pulse requirements

Circuit action
:
are:
> 1
Map
may
or
entry
Either the
If the
or T input must be pulsed; the other

is
may
not be pulsed.
input
pulsed, the
input
may
or
may
not be pulsed;
otherwise, the
input must
not be pulsed.
s
1
Circuit action
:
>
Map
pulsed; the other
entry:
Either the
If the
or
is
J input must be
pulsed, the
may
or
may
not be pulsed.
input
input
may
or
may
not be pulsed;
otherwise, the
input must not be pulsed.
R
1
Circuit action
:
> 1
Map
entry:
The S input may or may not be pulsed. The R input must not be pulsed. The T input must not be pulsed.
Circuit action:
>
Map
may
not be pulsed.
pulsed. pulsed.
entry
The R The S input must not be The T input must not be

input
may
or
Map
entry:
Any
input
may
or
may
not be pulsed.
Chap. 19
READING THE
FLIP
293
The S-R-SR-T input

table.
Input
Circuit action
Map
entry
0>1
1>0
1-*1
flop
0-^0
Optional
S-R-SR-T flip
The map-reading
table.
rules for the
S-R-SR-T
flip
flop can be read
from
this
Every 1 must be accounted for either in the

input expression.
input expression or the input expression or the
Every
either in the
input expression.
Any
the
1 accounted for in the
T input
1
expression, any
accounted for in
or
may be used optionally in the S may be used optionally in the R

accounted for in
expression, any 1 accounted for in
input expression.
the
Any accounted for in the T input S input expression, or any or

for in the
input expression.
Any 1 accounted
the
input expression, any
may be used optionally in the T input

five flip flops discussed are
expression.
The input pulse requirements for the marized in the following table.
sum-
294
II
Chap. 19
Flip flop input pulse requirements

Circuit action
Map
entry
S-R
S-R-SR
T
T
1
S-R-T
S-R-SR-T
S
1
S
1
S
1
>
1 1
1^0
1
0^0
Optional
The following example

five flips flops.
is
used to review the reading of the maps for these
Example:
00 oo
01
1
01
11
1
10
FF
1
10
Figure 19-24
pulse-input sequential circuit requires four

is
flip flops.
A map
for the
excitation of one of these flip flops
shown
flip flop,
in Fig.
19-24.
Obtain the
expressions for pulsing the inputs of this
considering the five types
S-R, S-R-SR, T, S-R-T, and S-R-SR-T.

Flip flop
Type
Input
Si
S-R
Ri
S-R-SR
S,.
Ri
= x y y y + xJJî = xÛ^ + Wi) = *iJ>i yJi + Xxyiyiy,, = x y (y y + y,y = x y y + xjî = x^Ji + x y,y
1 i
A)
Chap. 19
SEQUENTIAL CIRCUIT OUTPUTS
295
T
S-R-T
Si
Ri
Ti
S-R-SR-T
Si
Ri
Ti
= xiiyJi + yJsVi + ytfty*) = xjiptyi = xMytfi, = x^y,. = XtpM = Xiy yi = XifJi

2
Sequential Circuit Outputs
The output
expressions are independent of the type of
flip
flop used,
and
are read directly
from the flow
table with secondary assignment.
Examples:
In Fig. 19-25, the optional y x y 2 11 combines with ^1^2 10, to achieve simplification. In Fig. 19-26, the optional y y 2 10 can not combine
x
some
with yiy 2
= 01,
and no
simplification results.
*2
'\
y,
*\
*z
'Z
v*
00 01
01
00 00
00,
10
10
1,*
10
1
Flow table with secondary assignment -#2

(
Z-Wk
p ulse -output)
Figure 19-25
*2
*\
*z
Ah
2 3 3
I
00
1 1
00
01
01
00
00,
1,Z
01
10
Flow table from example I 3
s

#3

(Pulse-output)
Z-xz y y z
Figure 19-26
11 1
1 1 1
296
II
Chap. 19
x
1
xz
1
*\
xz
2 3
00
1
00
00
00, z
2 3
01
4 4
\,Z
1
01
10 10
10
\
00
Flow table from example
Flow table with secondary assignment -#3

(Pu'se -output)
Z'hhh
Figure 19-27
Figure 19-28 illustrates a poor choice of secondary assignment from the

standpoint of
j>ij> 2
economy of
the output circuit. In Fig. 19-29, y^y 2

simplification, resulting in a
11
combine to achieve
=01 and more economical
output
circuit.
*\
'.
xz
01
11 11
K, 'i.
z
1
00 00
01
1
4
1
3 3
2
10
00
10
10
01
Flow toble from example I 6

(Level -output)
#1
z ' Y\Yz+ Y\Yz
Figure 19-28
x
1
1
xz
2
*\
*z
z
1
00 00
01 10
1 1
01
4
1
3
3
10
00
1
10
01
1

(Level -output)
-#-2
Z=/2
Figure 19-29
Chap. 19
SEQUENTIAL CIRCUIT OUTPUTS
297
Illustrative Circuit
Example 4, using secondary assignment #3 and S-R-T reviewed in its entirety, and the resulting circuit is shown
to 19-32).
Circuit requirement:
flip flops,
is
(Figs.
19-30
an output pulse
Z is

{
first
x2
pulse immediately following exactly
two consecutive x
pulses.
2 3
4 4
Flow diagram
\,Z
I
Flow table
Figure 19-30
*2
*1
'1 V, K '
xz
1
i
00
1
00
1
FF<
01
00
oo,z
1
1
01 10
10 10
00
1
#3
i
FF9
maps
s-R-r
flip 1flops:
Si
= = =
*\7\
xz
*\Yz
Sz
(unused
xz
*iFi
Rz =
Tz
=
'-
xzV\yz
Figure 19-31
1 1
298
II
Chap. 19
*z
>2
AND AND
7J
S-T-R
Sz
y z S-T-R
2
T z
Rz
AND
yz
Z
diagram
Circuit
Figure 19-32
Most-Economical
Circuit
Considerations
To obtain the most economical circuit, all types of secondary assignments and flip flops should generally be investigated. The same type of flip flop does not have to be used throughout; for example, FF could be an S-R flip flop, and FF2 a T flip flop. To properly evaluate a given secondary assignment and flip flop comX
bination, the entire circuit, that
is,
all flip
flop excitation expressions
and
output expressions, must be examined as a whole, since there

terms
may be
there
common
to
two or more of these
expressions.
Common
terms should
be looked for since they can lead to greater circuit economy.

are alternate
When
ways of reading a map,
it
may
even
be advantageous to give
if it is
preference to a
common
term,
if it exists,
larger than others.
not only of the combinational circuitry referred to above, but also of the type of flip flop used, since the types of
circuit cost is a function
flip flops
The
themselves can differ in cost.
PROBLEMS
1.
From
flip
the following flow table with secondary assignment, obtain the
flop excitation maps.

*\
*z
/1/2
z
I
00
10
01
11
10
00
1
0!
01
00
1 I
10
Figure 19-33
Chap. 19
PROBLEMS
299
*2.
From
the following flow table with secondary assignment, obtain the

excitation maps.
flip flop
/,/2
00
II
00
It
1 1
01
01,
01
10
10
10
00
Fig lire
19-34
3.
Obtain the
flip
flop excitation expressions indicated below.

logic,
Using the
circuit
minimum combinational
assuming that the
draw the most economical
flip flops
are listed in order of increasing cost.
FF
t
h
I
y2
1
FF,
1 1
FF
Inputs
S-R
S-R-SR
T
S'-
sz
--
R2
sz
Tz
--
--
/?2 =
r
t
--
--
S-R-T
s,
--
Sz'-
Rz
S-R-SR-T
r,
=
~-
Tz~-
Sz
=
--
Rz
TZ
z=yz
Figure 19-35
300
II
Chap. 19
4.
Design a sequential
circuit
for
the
requirements in Example
2,
Chapter
(a)
18.
(b)
(c)
Using secondary assignment 1 Using secondary assignment #2. Using secondary assignment #3.
solution requiring
A
5.
two two-input and

is
circuits as the total

all
combi-
national circuit requirement
possible in
three cases.
3,
Design a sequential
18.
circuit for the
requirements in Example
Chapter
A A
solution requiring
two two-input and

is
com-
binational circuit requirement

*6.
possible.
Design a sequential
18.
circuit for the
solution requiring one two-input

is
requirements in Example 5, Chapter and circuits as the total com-
binational circuit requirement

*7.
possible.
and write a word statement describing the sequential circuit action. From the word statement, design a more economical circuit. A secondary assignment other than the one used in the circuit in Fig. 19-36 leads to a solution requiring only two two-input
Analyze the
circuit in Fig. 19-36
and
combinational circuit requirement.
'a
h
y\
>\
AND
OR ~l
AND
51
S-R
1
AND
OR -J
AND AND
OR
T
2
h
z
AND
OR
AND
Figure 19-36
Related Literature for

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Kautz,
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Chapter 3
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301
302
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and the Design of Combi1,
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2,
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Chapter 12
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2,
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D. B. Netherwood, "Minimal Sequential Machines," IRETEC, Vol. EC-8, No.

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Scott, "Finite
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Chapter 16
(See Chapter 18 for
many
related references.)
Chapter 17
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M. Yoeli and
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11,
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31
Chapter 18
D. B. Armstrong, "A Programmed Algorithm
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for Assigning Internal
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5,
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312
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T. U. Zahle,
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Par-
Answers and Solutions

to
Problems
Chapter
1. (a) 1
(b)0
(c)l
(d)C (e)C
(f)0
2. (a) [(A
3.
+ B) C + D) E + F + W(I + TC)]H (a) (A + E) C (DF + B) (b) AF + + {A + C) D (c) B(D + E)[AC + F{G + H)] (d) C + F + (/I + B)(D + GH) (e) >C + D)[B(E + F) + GH] (f) C + EF + (AB + D)(G + ##)
(b) [S
313
314
4. (a)
AC AC + AS + CD (c) (A + B)(B + CD) = B + ACD (d) HE + DE + GH + iJFF (e) (L + P)(L + M)(Q +P + L)(P + JV) (f (A + BC)(A + D)(BC + F)(/f + 5 + C +
(b)
F)
5. (a)
(b)
(c)
AB + 5C5 + CDE 5C + ,4F

(A
5)(C
D)
(d)
(e) (f)
(g)
(5 + C + 5)04 y4D + C ABC + C> {A + 5 + C)(C
+ +
D)
Z>)(/T
+5+
E)
(h)
6. (a)
U + 5 + C)(C + D)
/<C
+ BA + 5 + C5 + GC + /)(/ + f)(P + A)(P + O + F)(C/ + f) (c) CF + i)F + FC (d) (A + F)(C + ,4)(F + D) (e) ^F + EF + AS + î> (f KL + LM + HM + GM (g) X? + XZ + YZ + XZ = XY + XZ + XZ or XZ + ?Z + XZ (h) (A + F)04 + C)(F + C)(C + A) = (A+ B){A + C)(C + /?) or 04 + C)(F + C)(C + A)
(b) (i>
7. (a)
U + DE)(A +B + C)
[5
(b)
8. (a)
+ E(F + +
F)
G)](Z)
,4
SC)
/4(5
+ ABC
(b)
9. (a)
D(E + F)G + Z>04B + C)

C4
Z> + E){A + G + C + FE) + C + FF) + A(BC + D + E) (b) [^ + B(D + E)(G + H + /)][/? + C(5 + F + F)(G + #)] or y!C(5 + F + F)(G + if ) + /?( + E)(G + H + J)
+ BC +
or y4(G
10.
+ AB + AC + AS + BC + BC = AB + BC + AC (A + C)(A +B) + BC (B + A)(B + C) + AC (C + B){C + A) + AB A(B + C) + A(B + C) B(A + C) + B(A + C) C(A +B) + C(A + B) (A + B + C)(A +B +
/JC
AB + BC + AC + C)(A + B) + BC (B + A)(B + C)+ AC (C + B){C + A) + AB

(A
C)
315
Chapter 2
1. (a)
(b)
2.
+ B)(A + C) ABC + ABC + ABC + ABC + ABC (c) (A + B + )(/? + 5 + C)(/? + 5 + C) (a) ^B + AC + D (b) (A + D)(B + C + D) (c) ABCD + ABI> + /45C5 + ABCD + ^5C5 + ABCD + /*/> + /4J5C2) + ABCD + /?CZ) + ABCD (d) (A+B + C + D)(A +B + C + D)(A +B+C + D)(A + B + C + D) (A +B + C + D)
04
Chapter 5
r
z
w
Figure 5-1
TT T
Figure
5-3A
A
1
B
|
I_
[ E
K H 6
Figure
5-4A
316
i-t-i
M
H
M
N
Figure
5-5A
FAB
H
V6 J
Figure 5-8A
ILL
Figure
10.
3-9A
6 r-B-rC-r*
{B
D
T -r
8
C
6-T+-1
r-1 C-
-H
A
u
E-
X,
(a)
A
Figure 5-1 OA
U
U)
-E-F--

A
B-
317
11.
\-A-t-B-
T
2
Figure 5-11
Chapter 6
1.
2.
AS + ACD + ABD {A + S)(A + C + D)(B + C +
D) or (A
S)(A
+C+
B)(A
+B+
D)
3.
ACB, ABC, ACD, ABD, BCD, ACD, SB, BC
4. (a) 7
6.
(UV + UWX + UXY + VWZ + VYZ + WXZ + XYZ) ABE + ACE (c) BE+ D + CE 1 /45C5 + SB + 5CZ) 2: /45C> + ACD + SB 3: ASC + ABCB + /ffiCZ)
(b)
:
Chapter 7
1. /*
3. 4. 6.
7.
8.
+ B + C + CD + 5C + AD or (/? + C)(5 + D) 55 -f CD + AD or (5 + D)(A + C + B) /f#C + ABDE + 5C/5 + ASB + /4Cfi or /45C + ABDE + 5CD + ASB + SBE or /45C + ABDE + BCB + ASB + SCE (S + D)(B + B)(A + C + E + D)(A + E + B)(A + C + B) or (S + D)(B + B)(A + C + E + B){A + E + B)(A + C + B) CDEF + CBEF + /4CZ)F + ACDE + ASB + SBEF
/f
Chapter 8
1.
Many
solutions with 1-7-7-8-8 distribution.
2.
B-r-C
D-
\-CA-
-B-
(0)
0B Tu
Figure
a-
DA(b)
8-2A
318
3.
(a) 15
(b)
(c)
(d)
5.
(2-l)-(w- jP) -(8 -4) = 11 15 (8 4) = 11 15 - (8 - 3) = 10 15 - (8 - 3) - 10
=2^
160-96
=
64
E3^ =3^
=2^
8
384-176
208
2048 - 608
1440
=2-
10
10,240-2240
8000
ny
Figure 8-3A
Chapter 9
1. (a)
ABCDEF6H
Figure 9-1
(b)
zlSSi
A B
C D E
Figure 9-1

S] ti ABCDEFG
319
(c)
= S\Â6CdEFG
Figure 9-1
(d)
Figure 9-1
2. (a)
S{ 2 ,3,iABCD
(b)
S^ X3i EFGH =
S 0<1<3 MNOP
4
(c)0
(d)
(e) (f)
SUQRST
S A ,2,iUVfVX
Figure
5. (a)
9-3A
(b)
(c)
S%ABCDE S\ABCD
S\ A BCD
320
Chapter 10
1.
1
00
001
0011(11)
4 4
2
3
0011(11)00
00
001
2
3
3
i
0011
00100
001 11 (00)
-00
-001
1 1
2
3
-0011
-00111
6.
00
2
3
001odd 001even 001odd 100

7.
11
110
11011
1
1100(11)1
8.
00
001
2
3
0011
001100
0011001
00110011(00)
4
5

10.
1
321
-00
-001
1 1 1
2
3
2
3
-0011
4
5
-00111
-001111(11)
6
1
-0011100 -0011100 -0011100 -0011100 -0011100

11.
-00
-001
-0011
7
8
-00111
9
10
-001111(11)
1
10
00
001
2
3
3 3
4
5
00100
0011
0010011 ul
4
5
1
001001
00111(00)
00100111(00)1
12.
00
001
2
3
2
3
0011
7
5
001100
0011001
00110011
00111
4
5
6
7
8

8 8
0011100
001100111(00))
00111001(00)
11
Chapter
1.
1
3 3 3 3
1x2=2 0x4=0 1x8=8

1 1
|59 [19
2'
1
2012 (base
2
3)
|_6 |_2
x 16 x 32
= =
16
32
59 (base 10)
322

x
2.
Ox
6
7=0
= =
1
6
6
|981
3
1
|163
x 49 2 x 343
294
686
981 (base 10)
6 6
4313 (base 6)
[_27
Li
.8125
4.
2 2 2 2
[13
|_6
|_3
1
1
x2
1
.6250
Li
x2
1101.1101 (base 2)
1
.2500
x2
.5000
x2
1
'
.0000
Ch apter 12
1.
1
3
2
6 2
1
1
7
1
c,
c
1
c4
1
P
1
2
3
1
1 1 l l
1
1
4
?
(Double
error,
no correction made)"
Note
that this digit could be a 5, 6, or 7:
10
110 1110
*1*2
**
> 6
7
Chapter 14
1.
00
01
11
10
457 468
2
10
1
8 8 8
7
14
2 3
6 6
Figure 14-1
323
2.
*\*Z
00
01
II
10
346
1

2 2 2
6 6
5
1
4 4
Figure
1
14-2A
=3
4=6 8=9
10
*1*2
11
00
01
11
10 10 10
10
12 10

I 1 1
4 4
8 7 8 8
4 4 4

8 8
10
(jb)
Figure
14-4A
=7
6s7
1=2
3=4
00
01
11
10
z zt
x
00
1
3 3
3
<
10 10
01
10
Figure
14-6A
324
Chapter 15
1.
"1
"2
00
01
II
10
2
8
5)(S)
147/25/368
Figure 15-1
Chapter 16
1.
*1
"2
00
01
II
10
K, K, 'VI
00
a
c
01
II
10
4 3
2 5
d
b
00
01
1
10
3@U ) s'
2
1>
"1
00
00 00
01
ii
1 1
01 01 01
11
10
10
01
1
00
1
10
10
10
'2
'
x x
\
z Y\
y\
^2
*\
2 \
x X
\
Z^2.
10 00 10
Figure 16-1
325
3.
*t*2
00
01
11
10
000 000
001
01
I
010 000
---
001
101
100
001
000
010
---
---
010 110
110
1
1
010
11 11
010
010
111
010
110 011
1 1
110
101
101
001
...
101
101
100
---
---
110
Figure
16-3A
(x x
5.
Y = x x y + XiX y + yiy Y = x x + piy + x yi + x

t
x
or
+
x x
jy 2 )(*i
2 yi 2
or
x
x x 2 +yiy 2
2)
+ x + yd(x + +xy +xy

2 2
1 1
y2 )
or
(x 2
+ y + y ){xy + x + y ){x + y
l
Note that the product of sums Yi and Y2 are optimum.

,
solutions, with (x x
+ y ) common
2
to both
Chapter 17
1.
<\*z
00 00 10
01
1
II
10
01 01
A
Z2
=*l/l
=
+/1/2 +
/
2
11 11
01
*,/,
*,/,
/,
s
1-
000
-1
or
or
x2 yz
/2 + /,/2 + x /2
t
00
11
-0
10
y + xz yz + xz ^
10
-0
/-map
/
Figure 17
1A
326
3.
123/45 145/23
Merger diagram
123/45
x.x, "2 1
145/23
00 01
II
10
00 01
2
11
10
@ @
4
I
01
11
Merged flow table

,, 2
Merged flow table

*\*2
00
01
10
00
10
10
1
11
K-mop
110
Y-mop
--
x^xz
/, (x~z
x y + /)
s
=
=
x xz
y
+
+
xz y
xz
(/,
/)
x xz
}
X\XZ
11
00 01
10
0-00
/-mop
. x2 z
110
y
o
i
00
(
01
-
11
10
1 1
Z-- x z y
/= /
or
/-map Y
AN[)
*/
Delay
Figure
17-3A
Chapter 18
1. *z
*i
327
2.
1
*\
*z
1
3 5 2 5
4
5
1,/
1
-*i
*2
1
2 3
4
7
2 2
4
5
6 7
6,/
1
Figure
18-3A
Chapter 19
*\
1/2
*z
h
\
1
h
1
00
10
01
II
10
00
1
FF
1
01 01
10
00
/t
II
1
FF 9
1
Figure 19-1
328
3.
FF
Inputs
S-R
$=<r,/2 + *zy\h
S2
2
--x2 yx
y2
y^
*,/2
* /, 2
y2
x
"
z y\
S-R-SR
5i=/,/2 + x2 y2
S2
x x
y y
y
R
{
'-
x
s
y2 +
y2
'i
R2
y\K +
x
2
--
\-' x T \~y\h +
y2
T2
S-R-T
R,--xJ z
T\ '
v
Rz
T2
x
2
XZ /2
S-R-SR -T
S,= /,/2
S2
x2 y x
Rf*\h
7J
R2
T2
-
or
R2
2 y^
/ 2 /2
x2 y
z--
h
/2
*\
JA
t
1
1
AND
7",
S-R-T
<
>
ra
I
1
Sz
AND
1
1
-c R
Figure
S-R-SR
2
h h
19-3A
329
4-(a)
*i
*2
*z
00
01
I I
01
01
01
00
1
I
2 2
\z
00,7
10
fz
-
o
-
FF
I
A
1 1
h
1
1
FF
1 1
S-R-T
Sx
*i
R\
T\
r
--
xzyz
S-R
Sz
= *i
=
Rz
*2/l
Z
/2
*\
*2 /,
*z y\
y\
AND
Ty
S-T-R
1
*x
/t
Sz
>2
S-R
AND
R2
Figure
>2
7
19-4A
330

(b)
/,/ 2
1
2
2 2
00
01
0!
01
00
10
1./
10
11
01
00,/
FF,
1
FF>
i
,-
S-R-T
S\
/?,
--
x z yz
=/,
=
7"i
*2/i
S-R
Sz
=/,
=
Rz
xz
Z
>2
*\
= x y z x
xz
y
AND
y\
J
fc
'
S-T-R
1
Sz
*
S-R
2
yi
Rz
Figure
19-4A
331
(c)
*2
*2
00
1
11
II
II
00
01
00,
\,z
01
10
FF,
"t
1
1
S-R
S, **\
R\ --*z
S-R
Sz
z =
*\
Rz
*zy\
Z
*\
'-
'2/1/2
XZ
h
/l
S-R
s?
y?
S-R
AND-
Rz
AND
+z
Figure
19-4A
332
5.
*\
*z
I
2
3
00
01
01
I 1
00 00
00,
I.
Z
10
II
h
1
FF
1
1
1
1
y\
1
FF Z
1
S-R
Sy
=
--
*\/z
Xi
*\
S-R
Sz
-*\
=
Rz
xz
xz y
Z
/2
*\
--
xz
/i
AND
Ss
S-R
*\
1
/i
y\
Sz
S-R
yz
Rz
AND
Figure
19-5A
INDEX
Boolean algebra (cont.)
method of
Adders, 161 BCD, 165
full-,
attack, 18
postulates, 5
summary, 23
theorems, 7
163
half-, 161
Addition, 9 (see also or)
Algebra, Boolean (see Boolean algebra) Alphanumeric codes, 179

Alternative sequences, 189
summary, 23 Boolean expressions, special forms (see Special forms of Boolean expressions)
Boolean operations with symmetric notations, 128 Break-before-make contacts, 61 Bridge circuits, 63
and, 2
circuit, 39, 42,
45
diode, 48
transistor, 53
function, 37, 45
Assignment, secondary state (see Secondary state assignment) (see also
Spare secondary states)
Canonical form, 30 Chart, timing, 186

Chart, Veitch, 105
BCD adder, 165 BCD code, 165, 168

Binary adders (see Adders) Binary-coded-decimal adder, 165 Binary-coded-decimal code, 165, 168 Binary number system, 160 Binary ordering, 99, 105 reflected, 98, 105 Biquinary code, 176 Boolean algebra, 1
Codes: alphanumeric, 179 BCD, 165, 168 biquinary, 176 cross-parity, 180 cyclic, 169 excess-3, 168 fixed bit, 175, 180 Gray, 169 Hamming, 176, 179 m-out-of-n, 175, 180 numeric, nonchecking, 167
333
334
Codes
(cont.):
INDEX
Diode:
174 cross-, 180 quibinary, 176

parity,
and circuit, 48
logic blocks, 48
or
circuit,
49
170 reflected binary, 169 reflected excess-3, 170

reflected
BCD,
Disjunctive normal form, 30 Distance, 171
minimum, 171
Don't care combination, 72 Dotting, 53 Dual, 7
single-error correction, 176
with double-error detection, 179

single-error detection, 174
two-out-of-five, 175
Combinational circuit, 36 Complement, 6 Complementary approach: map method, 102 tabular method, 85 Complementation, contact network, 64 Conjunctive normal form, 30 Contact networks, 57
bridge circuits, 63
Electronic logic blocks (see Logic blocks) Electronic trees, 119
most economical, 119 Elimination of redundant input

iterative networks, 151
lines, re-
Elimination
of
redundant
states,
197,
266
Emitter follower, 51 Equivalence, 197, 266
pseudo-, 200, 266
and complement, 65 complementation, 64 implementation of and, or, and not, 59

multi-output, 65
nonplanar networks, 63 series-parallel, 60 symmetric, 129

transfer contacts, 61
Equivalent expressions, 6 Equivalent states (see Equivalence) Error detection and correction, 171 (see
also Codes)
Essential
prime implicant, 78
Even
parity code, 174
Contacts, 58
parallel path,
series
Excess-3 code, 168

Excitation, secondary, 182
60 path, 59
Excitation
flip
map:
(see
transfer, 61
flop
Flip
flop
excitation
Continuity-transfer contact, 61
maps)
secondary, 190
Correction, error, 171 (see also Codes)

Critical race, 211
Exclusive or, 4, 21, 46
Cross-parity, 180
Cycles, 209
Expanded product of sums, Expanded sum of products,
27, 28
27, 28
Cyclic codes, 169

Cyclic specifications, 241
Delay, 182
Factoring on map, 109 Feedback path, 183 Fixed bit codes (see m-out-of-n codes)
Flip flops, 253
excitation maps, 273
entries,
DeMorgan's theorem, 10
Detection error, 171 (see also Codes) Detection and identification of symmetric
functions, 137
outline, 138
274
reading, 278
summary, 294
S-R, 253, 278 S-R-SR, 281
Diagram, flow, 259, 261 Diagram, merger, 206
INDEX
Logic blocks, 37, 38 electronic, 48
diode, 48
transistor, 51
335
Flip flops (cont.)
S-R-SR-T, 291 S-R-T, 287 T, 255, 284 Flow diagram, 259, 261 Flow table, 190, 260, 261
incompletely specified, 203
vacuum tube, 49
Logical circuits, 36 (see also Logic, Logic
blocks)
merged, 206 primitive, 194

Follower, emitter, 51
Full-adder, 163
M
Make-before-break contact, 61
Functions of n variables, 33
Map:
flip flop
excitation (see Flip flop excita-
Gain, 183
Graphical complementation, 64
Gray code, 169
maps) method of simplification, 97 complementary approach, 102 factoring on map, 109 maps of more than four variables,
tion
106
H
Half-adder, 161
method of
attack, 103
Hamming code,
Hazards, 243
with optional combinations, 106 summary, 109

176, 179
identification in
map, 245
212 214 Z-, 190, 236 Minterm, 30

transition,
Y-, 190, 212,
Implicants, prime (see Prime implicants)
Included factor theorem, 15 Included term theorem, 15

Incompletely specified flow table, 203
Induction, perfect, 8, 14
Intuitive approach, sequential circuit synthesis,
Memory, 182 Merged flow table, 206 Merger diagram, 206

Mesh, 64 Minimization of
partial trees,
1
14
185
Invalid combination, 72
Inverter (see
Iterative
Minimum distance, 171 Minimum factored form, 33 Minimum product of sums, 27, 30 Minimum sum of products, 27, 30
Minterm, 30
not circuit)
method for obtaining prime im-
Mixed
logic,
45
87 Iterative network (see Reiterative netplicants,
m-out-of-n codes, 175, 180 m-out-of-n functions, 127

Multi-output networks, 88
contact, 65
work)
K
Karnaugh map, 105 (see also method of simplification)
Map
67 66 network and complement, 65 Multiple-output prime implicants, 88 Multiple secondary states to a row, 230
like contacts, parallel paths,
like contacts, series paths,
patterns,
Literal, 6
232
Multiplication, 9 (see also and)

logic,
Logic (see Mixed
Negative
logic,
Multivibrator, 255
single-shot,
Positive logic)
255
a ^
336
INDEX
N
nand:
circuit, 40, 43,
Parity code, 174

Partial trees, minimization,
Patterns,
45
1 14 secondary states {see Spare secondary states, patterns)
spare
transistor, 53
vacuum tube, 50
function, 37, 38,
Perfect induction,
8,
14
45-47
Pierce
Arrow
function, 38
Position, relay, 61
Negative
logic,
41
Positional circuit, 145

Positive logic, 39
application, 44
application, 44
Node, 64
Noncritical race, 210
Nonequivalence, 199 tabular approach, 199 Nonplanar networks, 63
Boolean algebra, 5 summary, 23 Power-on output state, 196

Postulates,
Primary, 182
nor:
45 transistor, 53 vacuum tube, 50 function, 37, 38, 45-47 Normal form, 30 not, 4 circuit, 41, 44
circuit, 40, 43,
Prime implicants, 74 essential, 78 iterative method, 87

multiple-output, 88
weighting, 82
Primitive flow table, 194
Product, 9 {see also and)

canonical, 30
transistor, 51
vacuum
tube, 49
function, 37
Number systems, 156

binary, 160
standard, 30 Product of sums, 9 expanded, 27, 28 minimum, 27, 30 Prototype relay, 146
Numeric
codes, nonchecking, 167
Pseudo-equivalence, 200, 266

Pulse,
252
Pulse-input sequential circuits, 252, 256
Odd
parity code, 174 One-shot multivibrator, 255 Optional combinations, 72 with map method, 106 with tabular method, 79
or, 3
circuit, 40, 43,
elimination of redundant states, 266

flip flops
{see Flip flops)
flow diagram, 259, 261 flow table, 260, 261
45
diode, 49
transistor, 53
most-economical circuit, 298 output, 295 secondary assignment, 269 synthesis, 258
vacuum
tube,
exclusive, 4, 21,
50 46
Q
Quibinary code, 176
function, 37, 45 Ordering {see Binary ordering) Outputs, transient, 241
Races, 210
critical,
211
Parallel paths:
noncritical,
210
lines,
contacts in, 60
like contacts in,
67
Radical point, 156 Redundant input
reiterative
net-
Parity, cross-,
180
works, 151
INDEX
337
down, 133
Redundant
Reflected
states, 197,
266
Shift
BCD code,
170
with three or more subscripts, 136

Simplification:
Reflected binary code, 169
Reflected binary ordering, 98, 105

Reflected excess-3 code, 170
Reiterative networks, 145
map
method, 97
tabular method, 71, 73
theorems, 18
Single-error correction codes, 176
redundant input
lines,
151
sequence representation, 150
with double-error detection, 179

Single-error detection codes, 174
Relay contact networks {see Contact net-
works)
Relay contacts {see Contacts) Relay
trees,
112
partial,
minimization of
114
Single-shot multivibrator, 255 Spare secondary states, 217 assignments, 222 multiple secondary states to a row, 230 patterns, 220, 232
summary, 233
Special forms of Boolean expressions, 27
Secondary, 182 excitation, 182

excitation
state
expanded product of sums, 28 expanded sum of products, 28 minimum expressions, 30
map, 191
{see also
minimum
factored form, 33
assignment, 212, 269
Spring, relay, 61
Spare secondary states)

Sequential circuits, 182 {see also Pulseinput sequential circuits)
basic operation, 185
cycles 209
cyclic specifications, 241
S-R flip flop, 253, 278 S-R-SR flip flop, 281 S-R-SR-T flip flop, 291 S-R-T-mp flop, 287
Stability,
184
Stable secondary, 184
elimination of redundant states, 197
Standard
State
sum and
product, 30
flow table {see

hazards, 243
Flow
table)
State, secondary,
182
merger diagram, 206 most-economical circuit, 247 power-on output state, 196 pseudo-equivalence, 200 races, 210 secondary state assignment, 212
spare secondary states {see Spare secstability,
assignment {see Secondary state assignment) {see also Spare sec-
ondary
states)
States, equivalent, 197, States, redundant, 197,
266 266
ondary states) 184
Subsume, 13 Sum, 9 {see also or) canonical, 30 standard, 30
Sum of products,
synthesis, 193
intuitive approach, 185
9 expanded, 27, 28
transient outputs, 241
map, 212 F-map, 190, 212, 214 Z-map 190, 236

transition
Series-parallel contact network,
minimum, 27, 30 Symmetric functions, 126 Boolean operations, 128

contact networks, 129 {see also Symmetric relay contact networks)
60
in design of electronic switching circuits,
Series paths:
161
contacts
in,
59 66
detection and identification, 137

outline, 138 m-out-of-n functions, 127 variables of symmetry, 126
like contacts in,
278 Sheffer Stroke function, 38

Set-reset flip flop, 253,
338
Symmetric relay contact networks, 129
identification of transfer contacts, 131
INDEX
Transition map, 212
Transposition theorems, 20
Trees:
electronic, 119
symmetric
131
circuits with multiple m's,
complemention, 135
most-economical, 119
relay, 112
complemented variables of symmetry,

136
elimination
contacts,
of
redundant
transfer
minimization of partial, 114 symmetric, 130

Trigger, 255,
132
284
14
175
equivalent points, 134

shift down, 133 symmetric tree, 130 Symmetry, variables of {see Variables of symmetry)
Truth
table,
Two-out-of-five code,
U
Unstable secondary, 184
T flip flop,
255, 284
Table, flow {see Table, truth, 14
Flow
table)
Vacuum tube:
inverter,
49
Tabular method of simplification, 71, 73 algebraic solution of final table, 80 complementary approach, 85 with optional combinations, 79 weighting prime implicants, 82 Theorems, Boolean algebra, 7
logic blocks, 49
nand circuit, 50 nor circuit, 50 not circuit, 49

or
circuit,
50
Variables, 6
summary, 23 Timing chart, 186

Transfer contacts, 61
Transfer trees {see Relay trees)
Transient outputs, 241
Transistor, 51
Variables of symmetry, 126
complemented, 129, 136

Veitch chart, 105
w
Weighting prime implicants, 82
and circuit, 53
emitter-follower, 51
inverter, 51
logic blocks, 51
y-map, 190, 212, 214
nand circuit, 53 nor circuit, 53 not circuit, 51 or circuit, 53
Z-map, 190, 236
(Continued from front
flap)
vantage of
this
method
is
that exci-
tation expressions for

flip-flop
any type of can be read from a single
map
set.
is
There
a strong emphasis
sequential circuits
almost
on
50 per
cent of the book.
Mitchell
tion.
P.
Marcus
is
a Senior
Engineer with the

In
IBM
his
Corpora-
addition to
switching circuit
plication
to
work in theory and its apdesign of
the logical
IBM
IBM
nals,
products, he has been teach-
ing courses in switching circuits at
since 1954,
in
He
has had
many
jour-
publications
professional
has been granted numerous
patents,
and has received an IBM!
Outstanding Invention Award.
Englewood
PRENTICE-HALL, Inc. Cliffs, New Jersey

167
Printed in U.S. of America
Other recommended books of interest
DIGITAL
by
COMPUTER ENGINEERING HARRY J. GRAY, University of Pennsylvania

is
This book
directed at the analytical and practical problems
which must be
systematically solved in designing a high-speed digital-computer system. It treats digital circuit theory, signal transmission and noise, statistical design, and the
integration of these into the digital
It
computer design
practice.
includes cross-talk prediction in a computing system, circuit analysis techniques
that are of practical application, circuit synthesis techniques that

to
have been found
be of value, statistical design, reliability consideration peculiar to digital computers, logical requirements for digital computer circuits, statement of the problem of synthesis for digital systems, general characteristics of synchronous and asynchronous systems, and areas where design automation has been of value.
Published 1963
381 pages
ALGEBRAIC STRUCTURE THEORY OF SEQUENTIAL MACHINES by J. HARTMANIS, Cornell University and

R. E.
STEARNS,
General Electric Research and Development Center
The authors
tial
present the first thorough treatment of the structure theory of sequenits applications to machine synthesis and machine decomposition into smaller component machines. The unified mathematical approach de-
machines and
veloped by the authors produces results that are easily understandable and directly applicable to the design of sequential machines.
All the structure and decomposition results, including those derived from semigroup analysis, are obtained through the appJication of partition algebra and its
The mathematical formalization expresses algebraically the intuiconcept of information, and makes possible the solution of prohlems related to the flow of this information in machines.
generalizations.
tive
Published 1966
211 pages
COMPUTATION: FINITE AND INFINITE MACHINES by MARVIN MlNSKY, Massachusetts Institute of Technology
Provides an introduction to the theories of finite-state machines, programmed computers, Turing machines and formal languages (in the form of Post Systems), Some of the outstanding features include: topics covered range from basic principles to current research problems extensive discussion of the meaning and motivation of the theory, its practical value and limitations. Brings together three different approaches: Neural Nets (of interest to Life Scientists), Turing Machines and abstract languages, which are usually treated as different, disconnected
topics.
Published 1967
320 pages
Englewood
PRENTICE-HALL, Cliffs, New
Inc.
Jersey
87986
iKb

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CE-HALL

and concise treatment

sequential switching circuits, with

In the second edition of this well-

covering the design

and simplification of combinational and sequential switching circuits,

material clearly and concisely, with

heavy emphasis on the practical

end-of-chapter problems for

the reader to test his knowledge

understanding of the subject; (2)

of these problems at the back of the

book; (3) Extensive bibliography

study; and (4) Extension of tabular method to multi-output networks.

Other outstanding features

shown exactly how

ognize the application of the theo-

pressions in the synthesis of pulse

input sequential circuits.

LEICESTER COLLEGES OF ART AND TECHNOLOGY

returned after this date.

26. GC7" 1975

PRENTICE-HALL ELECTRICAL ENGINEERING William L. Everitt, Editor

Electric Circuit Analysis

Chang, K. N, Parametric and Tunnel Diodes Chang, S. Energy Conversion*

and Active Network Analysis and Synthesis

Industrial Electronic Engineering

DekKKR Electrical Engineering Materials Del Toro Principles of Electrical Engineering

Goldman Goldman Gray

Transformation Calculus and Electrical Transients

Analysis and Synthesis of Sampled- Data Control Systems*

Automatic Control Systems, 2nd

Le Croissette Transistors LegroS & Martin Transform

Calculus for Electrical Engineers

Ma lev & Skiko

Field-Effect Transistors: Physics, Technology

* This title is also in the Prentice-Hall International Series in Electrical Engineering.

Prentice-Hall, Inc.; Prentice-Hall International, Inc., United

Hall of Canada, Ltd., Canada.

PRENTICE-HALL, INC., Englewood

621. 516 .5. 049

All rights reserved.

be reproduced in any form or by any

means without permission

Library of Congress Catalog Card No. 67-10748

referred to as logical design. Switching circuits can range

in complexity from a simple staircase lighting

upstairs and downstairs, to a complex circuit that performs arithmetic in an

interesting task of the logical designer

these ways require

logic blocks than others.

circuit that he can.

can usually be designed

dous growth of automatic

computers and the increasing complexity

of business machines and automatic control systems, logical design based on

reach a solution. Furthermore, the elimination of even a few redundant

down -time and