124

978-4-86348-009-4 2009 Symposium on VLSI Technology Digest of Technical Papers

6B-2 (Invited)
Graphene nanostructures for device applications
Joerg Appenzeller
1
, Yang Sui
1
, and Zhihong Chen
2
1
School of Electrical and Computer Engineering and Birck Nanotechnology Center, Purdue University
West Lafayette, IN 47907, USA
2
IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, USA
1
1-765-4941076 (phone), 01-765- 4968383 (fax), appenzeller@purdue.edu
Abstract
After an introduction that explains why graphene is in general
considered to be promising for electronic applications since a
few years, we will discuss several of our own new findings on
graphene field-effect transistors. In particular, this article
makes three points: 1) The material itself graphene offers
intrinsic advantages due to reduced scattering in
low-dimensional structures. 2) The particular energy
dispersion of graphene is a key enabler for operation in a new
regime called the quantum capacitance limit. 3) Scaling of
graphene devices is not following the classical, diffusive
theory.
In detail, we present a simple argument why graphene
nanostructures exhibit an intrinsic advantage when
considering the gate delay in three-terminal device structures
and explain why the possibility to operate in the quantum
capacitance C
q
limit provides additional benefits. We show
experimental data on the energy dependence of C
q
that support
our previous statements and show first experimental evidence
that scaling of the off-state in graphene transistors follows
percolation theory rather than conventional diffusive transport
equations.
Introduction
New materials are frequently discussed for electronic
devices with improved characteristics. In case of graphene the
certainly most exciting news that unrevealed in 2008 was that
an ultra-thin body structure with a body thickness of just
~0.4nm (the thickness of one layer of graphene) can exhibit
mobilities in the 10,000 to 100,000 cm
2
/Vs range [1,2,3].
However, the highest mobilities were reported only for very
low temperatures of a few Kelvin and interestingly were
obtained for free-standing graphene after removal of the
underlying substrate. It quickly became clear that, as many
other nanomaterials with a large surface to volume ration, the
electrical properties of graphene are strongly impacted by the
environment here the underlying silicon/silicon dioxide
substrate. This finding made a couple of scientists develop the
so-called puddle picture [4,5,6]. It implies that potential
fluctuations are creating electron and hole puddles in the
graphene layer that are responsible for the observed off-state
current in most devices today. In the last part of this article, we
discuss our novel findings on this particular topic and explain
how scaling of graphene devices is strongly impacted by
electron-hole puddles.
A little earlier, in 2005, it had become clear that carrier
transport through graphene a gapless semiconductor can be
modulated by means of a gate field [7,8], an obviously
important prerequisite for field-effect transistors. The key to
this unique behavior lies in the two dimensional density of
states (DOS) in graphene which is proportional to the energy
and vanishes at the so-called Dirac point. Figure 3 shows as an
inset the energy dispersion of graphene that resembles two
back-to-back cones, one describing the electron motion and
the other one the hole transport through graphene. When the
gate voltage is altered, the population of these cones is
changed and the current shows a V-shaped dependence on gate
voltage. The important underlying ingredient is the graphene
DOS. To capture the responds of the graphene bands to the
external gate voltage it is important to introduce this quantity
into the conventional current equations. This can be done by
means of a capacitance in series with the gate oxide
capacitance. We will refer to the additional capacitance that is
proportional to the graphene DOS as quantum capacitance Cq.
The second part of this abstract will show our experimental
data on the quantum capacitance and discuss its relevance for
device applications.
Improving on the current modulation of graphene devices
was another milestone in the quickly evolving field of
graphene electronics. Creating a bandgap in graphene by
defining small stripes of graphene so-called nanoribbons -
and introducing an energetically forbidden band through size
quantization has been recently demonstrated by a number of
groups [9,10]. The relevant question in this context is, in how
far the unique transport properties of the two-dimensional
graphene films survive the opening of a bandgap. In particular
since conventional wisdom teaches that the larger the bandgap,
the smaller the carrier mobility it is important to evaluate the
advantage of graphene nanoribbons if compared to
conventional bulk semiconductors. We will start the
discussion in the experiments and discussions section
addressing this critical question.
With these ingredients in place, graphene is believed to be a
hybrid that combines the outstanding transport properties of
carbon nanotubes with the possibility to employ top-down
fabrication techniques to create device structures at the desired
locations. At the same time the ultra-thin body of graphene
suggests the possibility for aggressive channel length scaling.
With all these encouraging news, it makes sense to take a
closer look at the implications of the above observations for
field-effect transistors from a device engineers prospective. In
particular, we want to emphasize in this article that graphene
offers some rather unique properties when looking at various
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2009 Symposium on VLSI Technology Digest of Technical Papers
scalability aspects, making it an interesting choice for high
performance field-effect transistor (FET) applications.
Experiments and Discussions
Considering various materials for FET applications we want to
suggest a useful metric that allows an insightful comparison.
Assuming diffusive transport in the mobility limited case, the
drain current I
d
is proportional to C
ox
/ L
2
(with C
ox
in units
of Farad and L being the gate length). Considering the gate
delay t
delay
= C
ox
V
dd
/ I
d
, and expressing mobility in terms of
bulk effective mass m* and scattering time t
scatt
, t
delay
is
proportional to L
2
m* / t
scatt
. The minimum channel length that
can be achieved with a certain material depends on its bandgap
E
g
and effective mass. Direct tunneling through the gated
region of the transistor ultimately limits scaling of L. The
tunneling probability from source to drain in WKB
approximation is
(1)
with being a constant. If we claim a fixed acceptable
leakage current, the minimum achievable L is defined by L (E
g
m*)
0.5
= const. accordingly. The gate delay thus becomes:
(2)
While small bandgap semiconductors exhibit a slightly higher
t
scatt
value (see table in Fig. 1), this positive effect gets
overcompensated by E
g
when plotting t
delay
according to eq.(2)
see figure 1. This statement holds true even if the low-field
mobility is replaced by a more comprehensive expression of
that includes the gate dependence explicitly. Carbon
nanotubes and graphene nanoribbons, both exhibiting a
bandgap [11] due to size quantization, do not follow the trend
observed for all other bulk-type materials. In fact, the
combination of high carrier mobility and sizable E
g
is the key
to this unique difference. (Note, that while in fact graphene
nanoribbons with the same electrical properties as carbon
nanotubes have not yet been fabricated, the excitement about
graphene is exactly motivated by the promise of small
scattering times similar to the case in carbon nanotubes.)
Fig. 1: Compound impact of the bandgap and scattering time t
scatt
on
the gate delay according to equation (2).
Next we want to turn our attention to another intrinsic
property of graphene that promises substantial advantages
over conventional devices. The quantum capacitance C
q
that
has been introduced above is a measure of the available states
in a semiconductor that can be populated by means of
sweeping the gate voltage.
(
exp *
WKB g
T a L E =
)
m
Fig. 2: Quantum capacitance of graphene. The gray line indicates the
calculated oxide capacitance for a 4nm HfO
2
gate dielectric. C
q
is
extracted from C
tot
employing the capacitance network shown. C
tr
is
associated with the presence of traps at the graphene/dielectric
interface.
Conventional wisdom teaches that a capacitance the
quantum capacitance in series with the oxide capacitance in
the gated channel region will unavoidably have a detrimental
impact on the charge control inside the device.
Correspondingly, one may conclude that it is desirable to work
with materials that exhibit a high density of states and thus a
large C
q
-value. In a recent article we pointed out that this is in
fact ignoring certain scaling advantages arising from a small
C
q
in low-dimensional systems when it comes to the power
delay product [12]. The central argument is that while the
oxide capacitance scales with L/t
ox
, the quantum capacitance
does not show any gate oxide thickness dependence and can
thus be reduced to decrease t
delay
without losing gate control.
(For a detailed discussion see [12].) Here we show
experimental data [13], proving that graphene devices can
indeed operate entirely in the desired quantum capacitance
limit defined by C
q
<<C
ox
. The presentation will further
elucidate this rather unusual point.
Fig. 3: Transfer characteristics of a patterned graphene device. The
cones illustrate the relative position of the graphene band to the
source and drain Fermi level at different gate voltage conditions.
1
delay
scatt g
E
t
t
a

126
978-4-86348-009-4 2009 Symposium on VLSI Technology Digest of Technical Papers
Figure 2 shows the measured capacitance C
q
of a top-gated
graphene device over a wide energy range corresponding to a
carrier concentration variation An
s
= 1.3*10
13
cm
-2
. For
comparison the same graph contains the oxide capacitance
calculated for a moderately scaled 4nm HfO
2
gate-dielectric
layer. From this plot it is clear that scaled graphene devices
will indeed operate entirely in the quantum capacitance limit
allowing for an unsurpassed control of the band position
through the gate.
Last, we want to discuss our recent observations on the width
scaling of graphene FETs. Devices with short and narrow
channels were fabricated and characterized. Figure 3 shows
the transfer characteristic of a device with L=300nm,
W=125nm, and an oxide thickness of t
ox
=90 (This device is
back-gated.). The presented characteristics show the largest so
far reported I
on
/I
off
ratio at room temperature. Part of the reason
for this improvement arises from the fact that scaling of I
d-off
(as defined in figure 3) in graphene devices differs from
conventional FETs.
In order to study the scaling properties of graphene devices we
have fabricated graphene ribbons as shown in figure 4(a). In
fact this SEM image shows how we patterned a graphene
ribbon I of given length L and width W
1
first, measured
transport through the same, and then employed e-beam
lithography again to pattern another ribbon II of smaller width
W
2
in the same graphene area. This particular approach
ensures that the same puddle configuration is probed by both
ribbons of different width. The experimental data shown in
figure 4(b) show for the first time evidence that I
d-off
does not
increase proportional to the channel width but follows a
relationship I
d-off
~ W
1.25 to 1.35
(solid lines in figure 4(b) that we
interpret within the framework of percolation theory. While
percolation has been discussed in the context of graphene
structures before [14] and low temperature experiments have
provided some evidence of its impact [15], no study on the
performance of graphene devices at room temperature had
been previously linked with this phenomenon. Employing the
picture of electron-hole puddles, the device off-state is not
characterized by uniform current flow across the entire device
width. Instead, current will pick the path of least resistance
through the arbitrary potential landscape that is a result of the
above discussed potential variation. This unique behavior
allows for an improved I
on
/I
off
ratio for scaled devices since the
on-current does follow the conventional width dependence
(see also figure 4(b) a critical insight that allows for
substantially improved FET characteristics.
Summary
In summary, we have provided evidence for a number of
unique properties of graphene devices. We have discussed
several material related advantages of graphene including the
quantum capacitance and demonstrated a novel type of width
scaling behavior that had not been previously noticed.
Fig. 4: (a) SEM image of graphene nanoribbon devices. Ribbon I is
fabricated first and characterized, ribbon II is subsequently fabricated
on the same graphene segment allowing for the comparison presented
in (b). The dashed lines are I
d-off
proportional to W for comparison.
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