AbhilashKatta

Email Id: abhilashk543@gmail.com Phone No:+91 9449336408,+91 9492254410

SUMMARY:
I have a Bachelor's degree in Engineering and my experience includes over one and half years of training in Digital ASIC Layout Design Engineering.My training experience includes working on digital ASICs layout design, implementation of the same with different nodes of technologies like 180nm, 130nm. Successfully implemented and verified the designs for power and timing.

ACADEMIC EDUCATION
B.TECH in Electronics and Communications Engineering from Chirala Engineering College, Chirala with an aggregate of 65%. INTERMEDIATE from SNEHA junior college, Kavali with an aggregate of 78 % . Secondary School Education from Viswasanthi High School, Kavali with an aggregate of 63%.

PROFESSIONAL TRAINING:
An Industry Oriented Trainee in VLSI PHYSICAL DESIGN and DIGITAL DESIGN from Institute of Silicon SystemsPvt Ltd., Hyderabad since July 2012 till oct 2013.

COURSE OUTLINE:
VLSI Fundamentals, CMOS Basics, Digital Design, Floor Planning, Power Planning, Placement and Routing, Clock tree synthesis, Static timing analysis, timing optimization, Cross talk analysis, IR drop analysis.

TOOLS:
Have hands on experience in ASIC physical design engineering in 130nm and 180nm technology nodes using Cadence tools. Cadence SOC Encounter Floor Planning, Place & Route, and clock tree synthesis. Encounter Timing System Static Timing Analysis and Crosstalk Analysis. RTL - Logic Synthesis.

SKILL SETS:
Operating Systems HDL Languages Scripting Languages : : : Windows, Linux, UNIX Verilog TCL

PROJECTS:
PHYSICAL DESIGN Project 1: (BLOCK LEVEL)
Objective Tools Gate count/Area Macros /STD Cells No. of Clocks Frequency Technology/Layers : : : : : : : Macro Placement, Timing Driven Layout SOC Encounter, QRC, ETS, Voltagestorm, PVS 2, 96,296 /1508801.9 um^2 12/25195 17 200MHz UMC 0.13 micron/5 Metal Layers

Role:
Performing sanity check, Design import, Floor Plan and Power Plan, Placement CTS and Detail Routing, RC Extraction and Power Analysis, Static Timing analysis and Physical Verification Digital Design

Project 2: (TOP LEVEL)

Objective Tools Gate count/Area Macros /STD Cells No. of Clocks : : : : : Pad placement, manual CTS, Timing Driven Layout SOC Encounter, ETS 1,28,961/15,72,915.3 um^2 12/24,450 4

Frequency Technology/Layers

: :

150MHz TSMC 0.18 micron/5 Metal Layers

Role:
Performing sanity check, Design import, Floor Plan, Power Plan, Placement and CTS, Detail Routing, RC Extraction, Power Analysis, Static Timing analysis and Physical Verification

Academic Project:
Title: Patient Monitoring System Description: It is an embedded system used for measuring the temperature, pulse & breathe count . We are using 89c51 Microcontroller .We are using LM35 for measuring the temperature. The temperature value, pulse value is read by the microcontroller through the ADC 0809 which is interfaced to it. The breathe count is shown in the form high and low pulses which is plotted in the PC simultaneously with the temperature and the pulse. Finally we conclude that PATIENT MONITORING SYSTEM is an essential module where in the doctor can be alerted about the status of his/her patient.