Institute for Integrated Systems Munich University of Technology Prof. Dr. techn.

Andreas Herkersdorf

Final Exam System on Chip Solutions in Networking SS 2007

Munich, July 30, 2007 Time: 9:00 am

Room: N1179

.. Name

Matriculation #

.. Signature

Seat

Examination Time: 75 minutes

At first, please fill in the title page with your name, matriculation number and the number of your seat. Do not forget to sign the exam! If you hand in any extra sheets of paper, they must also contain your name and matriculation number. We will check the student ID and passport during the exam. The numbers in parentheses are indicative for the number of credits you can earn for a correct answer of this question. The maximum number of credits to be earned is 77. Subquestions which may be answered independently of other parts are marked with an asterisk (*). Question 5 is worth 32 credits! Please note that in multiple-choice questions false answers lead to negative credits.

No materials allowed in the exam except: pen, non-programmable pocket calculator, one sheet A4 with your personal notes.

Good Luck!

Final Exam SoCN SS 2007 July 30, 2007

1) Right or wrong? (8) Remark: correct answer +1, wrong answer -1, no answer 0 points, min.: 0 Yes No Caches perform well because of a high spatial and temporal locality in general-purpose computing applications. SONET/SDH networks are deployed in full-mesh network topologies. Ceramic packages are better suited than plastic packages for high-end ICs that consume a lot of power. CISC processors were developed to obtain good code densities. Network Processors combine programmable resources, hardware accelerators and high capacity interconnect structures to meet the performance requirements of modern networking applications. Thermal radiation dominates convection when regarding the heat dissipation from a package in typical operating environments. Superscalar processors are more complex and larger than VLIW processors with the same amount of parallel execution units. The FIFOs for input buffered switches need a higher access bandwidth than those used in shared output buffered switches. 2) How do soft virtual components (VC) compare to firm and hard VCs with respect to area and power consumption in an SoC design? (2)

3) Name the three important components that are defined in an ISA (instruction set architecture)!

(3)

Final Exam SoCN SS 2007 July 30, 2007

4) Explain the difference between hardware and software multi-threading! (4)

5) SDH Framer Design (32) Consider the following design for the ingress processing unit of an STM-64 framer carrying ATM payloads.
L2 Interface ATM Cells Data Path Width w2 f2

Idle Cells

DEMUX

ATM HEC sync Payload Unscramble SDH Overhead Data Path Width w1 DEMUX
STM-64 SDH Framer

SDH Processing Data Path Width w1 Deserializer

f1 Clock Recovery

1 bit

SDH Line Interface (PHY) STM-64, (from optical receiver)

You are given the following technology parameters: 90 nm CMOS library, fmax, logic=600 MHz, fmax, SRAM=400 MHz, fmax, I/O=300 MHz Vcore=0.9 V, VI/O=3.3 V Analog design library: fmax=20 GHz, Vanalog=1.5 V a) * Derive the line rate of the STM-64 transmission scheme! (2)

Final Exam SoCN SS 2007 July 30, 2007

b) Right after the analog front end (deserializer and clock recovery circuit), you want to continue processing using the 90 nm CMOS library. What minimum data path width w1 (power of two) and frequency f1 do you choose? (2)

c) * The FIFO towards the L2 interface shall be implemented with a singleport memory technology. For what minimum memory access bandwidth do you have to provision it? What data word width is required (use powers of two)? If you could not solve a) assume a line rate of 10 Gbit/s! (3)

d) * You want to integrate four framers into a single-chip design. For the L2 interfaces, you have to consider a data valid and a clock line in addition to the data lines. There is no management interface. For packaging you have to choose between the following packages:
Package Total Leads I/O pins Die Size (M gates) A 180 120 2.0 B 210 150 2.0 C 250 175 2.4 D 450 350 3.0 E 550 390 3.0

The single framer design consumes 250k gates for the CMOS logic and the analog part consumes an area equivalent to 200k CMOS gates. What is the die size requirement of your design? (1)

e) * Now we have to consider the L2 data interfaces: What is an appropriate data path width w2 and operating frequency f2 with respect to the above given package sizes? What package would you choose? (3)

Final Exam SoCN SS 2007 July 30, 2007

f) Derive the chip's total power consumption! Each analog block consumes 300 mW, assume a CMOS power consumption of 4 nW/(MHz gate) and a switching factor of 15%. The I/O switching factor can be assumed at 40% and the I/O capacitance is 40pF. (6)

g) * For optimum power supply of your chip, you want to maintain almost equal currents through all of your Vdd-gnd pairs. How do you partition the power supply pins of your package to the three voltage islands with 0.9V, 1.5V and 3.3V? If you could not solve g) assume a core power of 200 mW and an I/O power of 7 W! (6)

Final Exam SoCN SS 2007 July 30, 2007

h) * Consider the following die-package combination:

Lid: hLid=20 W/mK Glue: kglue=0.8 W/mK Die Substrate: kSi=149 W/mK Junction (active area)
The substrate thickness is 0.25mm, the glue thickness is 0.05mm, and the lid has a surface area of 5000mm. The die has an area of 250mm. Derive the conductive thermal resistance between the active area and the lid (omit the lid itself)! (4)

i) * Determine the convective thermal resistance of the lid!

(2)

j) What is the maximum allowable air temperature, if the active area must be kept below 125C during operation? (3)

Final Exam SoCN SS 2007 July 30, 2007

6) Microprocessor Architecture Performance (17) Given is a single issue pipelined 32bit RISC CPU with a single level of cache memory. The CPU core and the L1 cache (64kB each for data and instructions, 16 byte cache lines) run at 1.6 GHz. The system bus (32 bit wide) is clocked at 400 MHz and is attached to a 200 MHz DDR-SDRAM with a 4-0.5 access pattern for data and a 400 MHz SRAM for code.
CPU L1 1.6 GHz SRAM 32b, 400 MHz

System bus (32b, 400 MHz) DDR-SDRAM Ctrl DDR-SDRAM 32b, 200 MHz

a) * What is the maximum achievable CPIcore of the CPU core?

(1)

b) * Now take a look at the memory sub-system. What is the CPImem contribution to the overall CPI (provide only the formula)?

(2)

c) * Derive the L1 miss penalties for data and instruction accesses (assume that the requested information is only available after the full cache line has been loaded into the cache)! (6)

Final Exam SoCN SS 2007 July 30, 2007

d) Assume a sequentially executed processing loop that has 40 kB instructions, the data access frequency is 10% and the L1 data cache miss rate is assumed at 35%. Compute the overall CPI for this system for the first iteration and later iterations! (7)

e) By how much does the CPI improve, if you replace the CPU core with a dual-issue superscalar architecture (neglect pipeline hazards)? (1)

7) Switch Architectures To what switch architecture do the following load/delay charts correspond? What is the problem in architecture B? (3) A: B:
10
Normalized Delay

10
Normalized Delay

8 6 4 2 0 20 40 60 80 100 Load [%]

8 6 4 2 0 20 40 60 80 100 Load [%]

Output buffered switch (1)

Input buffered switch (1) Head-of-line blocking (1)

Final Exam SoCN SS 2007 July 30, 2007

8) Networking SoC Challenges (8) In the following table, mark the aspects which are critical in the respective design. Give a keyword, why it is critical! SONET Framer LAN Switch Network Processor Power Memory Size On-chip interconnect Mixed-signal technology