Lec 11

Th U The University i it of fT Texas at tD Dallas ll
Erik Jonsson School of Engineering g g and Computer Science
Types of MIPS Instructions

The MIPS instruction set is small, and SPIM adds only a few pseudo-instructions. In addition to instructions, there are other functions to learn, such as directives and labels. MIPS i instructions t ti are di divided id d i into t several l groups. The fundamental instruction types, with examples, are:
Register-to-register Register to register instructions: Includes mathematical, logical, and manipulative instructions, such as add, subtract, multiply, divide, logical instructions such as AND, OR, and manipulations such as neg, move, rem, shift and rotate. We covered most of these last lecture.
1 Lecture #11 Registers, System Calls, and More Instructions
N. B. Dodge 09/09
Types of MIPS Instructions (2)

Instructions (continued):
Special instructions: Nop (no operation), syscall (input/output). Decision-making instructions (program control): Branch (beq, beqz, bge, ble, etc.), jump (j, jal, jr), comparison (seq, sge, sgt). Memory reference instructions (mainly load and store, since data in memory may only be accessed by loading and storing to/from a register lw, lb, sw, sb). Note: Load address (la) is covered with memory reference instructions, although it references a memory address dd only. l
Today we look at registers, instruction formats, some special p instructions, , system y calls, , directives, , labels, , comments, some examples, and a couple of exercises.
N. B. Dodge 09/09
Registers

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We remember that registers are collections of D flip-flops. Registers therefore can hold N-bit binary numbers, where N is the number of ffs ff s in each register register. The number of register bits (width) depends on the computer. The MIPS R-2000 computer has 32-bit data words, so that each register i t has h 32 fli flip-flops. fl The MIPS computer has 32 fixed-point data registers. There are rules (actually suggestions or policies) for register use. The rules may be violated; the assembler has no Register Police. However the violator does so at his/her own risk usage violations can result in incompatible p p programs, g which is very y bad p practice. In EE 2310, you must use registers as recommended in the rules.
Lecture #11 Registers, System Calls, and More Instructions
N. B. Dodge 09/09
MIPS Special-Purpose Registers

These registers are generally used only for the purposes noted below: Register Name or Value Purpose PC Program Counter Address of next instruction1 $ $0 Value always 0 C Comparisons; i clearing i registers i $1 $at Assembler temporary register2 $2 $v0 Value to be passed to function3 $3 $v1 $v Value V ue to o be p passed ssed to o function u c o $4 $a0 Argument passing to procedures4 $5 $a1 Argument passing to procedures5,6 $6 $a2 Argument passing to procedures5 $7 $a3 Argument passing to procedures5
Remember: the $ sign means register.

1 Not directly accessible by programmer. 2 Dont ever use this register! 3 Used in all system calls to load the s syscall scall n number; mber; also specifically specificall used sed in syscalls s scalls 5 & 12 for input inp t data. data 4 Specifically Specificall used sed in syscalls 1, 4, 8, and 11. 5 Argument passing past a total of four uses the stack. 6 Also used in syscall 8. 4 Lecture #11 Registers, System Calls, and More Instructions
N. B. Dodge 09/09
Special-Purpose Registers (2)

These registers are also generally used only for the purposes noted. Register Name Purpose $26 $k0 Reserved for use by (simulated) operating system.1 $27 $k1 Reserved for use by (simulated) operating system. system 1 $28 $gp Pointer to global area2 $29 $sp Points to current top of stack $30 $f $fp P i t to Points t current t top t of f frame f $31 $ra Return address to exit procedure
1 Don Dont t ever use these registers! 2 We will not use this register. register
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MIPS Temporary Registers

The t-registers hold temporary variables only. Contents of these registers are NOT required to be preserved across a procedure call. g Register
$8 $9 $10 $11 $12 $13 $14 $15 $24 $25
Name
$t0 $t1 $t2 $t3 $t4 $t5 $t6 $t7 $t8 $t9
Purpose p
Holds a local (temp) variable Holds a local (temp) variable Holds a local (temp) variable H ld a local Holds l l (temp) (t ) variable i bl Holds a local (temp) variable Holds a local (temp) variable Holds a local ( (temp) p) variable Holds a local (temp) variable Holds a local (temp) variable Holds a local (temp) variable
NOTE: You might think of t-registers as scratchpad registers.

N. B. Dodge 09/09
MIPS Saved Temporary Registers

S-registers also hold temporary variables, but contents of s-registers must be preserved across a procedure call. Register
$16 $17 $18 $19 $20 $21 $22 $23
Name
$s0 $s1 $s2 $s3 $s4 $s5 $s6 $s7
Purpose
Holds a saved temporary variable Holds a saved temporary variable Holds a saved temporary p y variable Holds a saved temporary variable Holds a saved temporary variable Holds a saved temporary variable Holds a saved temporary variable Holds a saved temporary variable
NOTE: In a stand stand-alone alone program, both ss and t-registers t registers may be used to store temporary variables.
N. B. Dodge 09/09
Instruction Processing
In all computers, an instruction is retrieved from memory, the fields of the instruction are decoded, and the decoded commands are processed.
Instruction I
Register R i t di divided id d into fields of bits Regi ister
Decoders
Result (to Registers or Memory)
Registers
Decoders
Instruct tion
Memory
Register Block
ALU
Instr.
Decoders
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Instruction Formats
There are only three basic MIPS instruction formats: Register (as seen in last lecture), Immediate, and Jump. Jump is shown below.
Bit 31 Bit 0
6 bits
26 bits
Op Code Field (tells computer what to do when decoded, in this case jump) case, jump).
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Address Field (added to a part of the Program Counter register contents to create the 32-bit jump address).
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Immediate Format Instructions

Immediate instruction formats are mainly for branch instructions and load/store instructions, which retrieve/store data in memory, and which we will study later. later Their format is shown below. below
Bit 31 Rs Rt Bit 0
6 bits
5 bits 5 bits
16 bits
Address Component p Field ( (16-bit signed g number). In a load or store, added to the contents of register Rs to create 32-bit address in memory from which data is loaded or to which data is stored. Added to PC contents when a branch is executed.
N. B. Dodge 09/09
Op Code Field (tells computer what to do ) when decoded).

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Register source of part of memory address address.
Data source/ destination register.
Register-Register Instructions
For most R-type instructions, the sixbit op code is 0x0 (00 0000) 0000). This 5-bit number tells the ALU the shift amount in a shift instruction. Rs = 0 for shifts Bit 0
Op Code No of bits: 6
Bit 31
Rs 5
Rt 5
Rd 5
Sh Amt 5
Fn Code 6
Register addresses are 5 bits (i (since 25=32). 32) Example: E l If Rt is i 0 1001 [09], then Rt = $9 = $t1.
Example p on next slide

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The function code is the register-register it i t function f ti to t be performed. Example: Function code 10 0000 [0x20] means add.
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Example Register-Register Instruction

For most R-type instructions, the six-bit op code* is 0 (00 0000). Rs = $8 = $t0 This is not a shift instruction, so the shift amount = 0. Bit 0
00 0000
Bit 31
0 1000
0 1001
0 1010
0 0000
10 0000
Rt = $9 = $t1
Rd = $10 = $t2 The function code* for add is 10 0000, or 0x 20 (this is technically add with overflow).
The assembly language acronym for this i instruction i is: i add dd $t2, $t2 $t0 $t0, $t1 $t1.
* A list of op/function codes can be found in the P&H inside front cover or back cover. (Note that if you have an older h d hard-cover b k with book ith codes d on th the i inside id b back k cover, th they are shown in decimal form).
N. B. Dodge 09/09
Th U The University i it of f Texas T at t Dallas D ll
Exercise 1
00 0000 1 1001 0 1110 0 1111 0 0000 10 0100
00 0000
0 0111
1 0011
0 1000
0 0000
01 1000
This problem will familiarize you with R-R instruction formats.

Instructions above are R-R. Write the SPIM acronym for them. Add function code = 0x20, Sub = 0x22, Mul = 0x18, AND = 0x24. Remember to convert register numbers to appropriate acronyms.
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Register-to-Register Instructions
A review of R-R instructions studied in the last lecture:

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add $s1, $t2, $t6: [$t2] + [$t6] [$s1]. addi $s1, $t2, 27: [$t2] + 27 [$s1]. sub $t3, $t4, $t5: [$t4] [$t5] [$t3]. Can also be immediate. mul $t0, $t1, $t2: [$t1] [$t2] [$t0]. div $t0, $t2, $t1: [$t2]/[$t1], quotient [LO] [$t0]. and d $t0 $t0, $t1 $t1, $t2 $t2: [$t1] [$t1] [$t2] [$t0]. [$t0] Al Also OR OR, NOT NOT, NOR NOR, XOR XOR. neg $t2, $s5: ([$s5]+1) [$t2]. abs $t1, $t0: |[$t0]| [$t1]. lui $t1, $t1 23: 23 (0000 0000 0001 0111) upper 16 bits of $t1. $t1 li $t1, 78645329: 78645329 $t1 (pseudo; uses $at). move $s5, $t3: [$t3] [$s5] rem $ $t0, ,$ $t1, ,$ $t2: [$ [$t1]/[$t2], ] [$ ], remainder [ [HI] ] [$ [$t0]. ]
N. B. Dodge 09/09
Note: In R-R instructions, the source register contents are NOT changed. Lecture #11 Registers, System Calls, and More Instructions
Miscellaneous Instructions
The following instructions are convenient to mention at this point:
nop: No operation. The computer does nothing for one instruction cycle. The set instructions: These instructions ( (which are technically register-register instructions) generally put a 1 or 0 into a destination register, depending on the comparative values of two other registers. We will cover these later in the lecture on branch instructions, as they are decision-making (or more properly, decision-support) instructions. Shift, and rotate instructions (also R-R instructions) will also be covered in that lecture.
N. B. Dodge 09/09
System Calls
System calls allow our simulated MIPS to communicate to the user and perform a few other functions functions. Most system calls either initiate a print sequence to the system console, or read data from the keyboard. Syscall 10 halts the program and computer simulation. Certain system calls use specific registers (primarily $v0 and d$ $a0). 0) The Th system t calls ll will ill not t execute t unless l the th designated registers contain the correct information. y calls are the user interface in SPIM. System
N. B. Dodge 09/09
System Calls of Interest

1 - Print int, $a0 = integer. $a0 contents printed as decimal integer. 4 - Print string; $a0 = pointer to string. ASCII string is printed out. 5 - Read int; $v0 holds integer. Numeric input characters read. * 8 - Read string; $a0 = buffer, $a1 = length. String is read from keyboard.* 10 - Exit E it program. Returns R t program control t l to t operating ti system. t 11 - Print character, $a0 = character (lower 8 bits printed as ASCII). 12 Read character. Keyboard character $v0 (lower 8 bits, ASCII). * System Calls 2, 3, 6, and 7 are related to floating-point operations, which we will not study. System calls 9 and 13-16 will also not be used. *Input I system calls ll are a little li l tricky; i k more about b system calls ll 5 and d 8 later l .
N. B. Dodge 09/09
Mechanics of Writing a System Call

Executing a system call requires two instruction:
(1) # of syscall $v0; (2) syscall For example, example syscall 10 ( (stop stop the program program): ): li $v0, 10 syscall 10 syscall
Sometimes $a0 or $a1 are used in syscalls syscalls. To print a number number, it is loaded into $a0, a 1 is put into $v0, and the syscall is executed:
syscall syscall 1 1
li $a0, 0x ab67 (this might also be loaded from memory) li $v0, $ 0 1 syscall
More examples of syscalls are on the next slide. We will cover s scalls 5 and 8 later in detail. syscalls detail
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More Example System Calls

la $a0, string li $v0, 4 syscall lb $ $a0,num 0 ( (or use li or move) ) li $v0,11 syscall li $v0,12 syscall y
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In syscall 4, $a0 is loaded with the memory address of the first byte in the ASCII string to be output output. Characters are output until a null (character = 0) is encountered. Syscall 11 prints out the lower 8 bits of $a0 as an ASCII character. In syscall 12, the 8 bits representing the ASCII character input from the keyboard the lowest 8 bits of $v0 (erasing the 12!).
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Directives
Directives give the SPIM assembler program information. The main ones of interest are shown here:*
.text text -- Program Program instructions follow follow. .data -- Data required by the program follows. .word [number] -- The data element that follows is a 32-bit number. Note: Can be used to define several elements at once. .space [number] -- Reserve the number of bytes in memory shown and clear them to 0. .asciiz [character string] g The following g characters should be stored in memory as a byte string and null terminated. .ascii [character string] Same as .asciiz but no null termination. .frame -- Reserve the frame as shown on the stack.
* See Pervin appendix D for full list of directives. All directives are preceded by a period. 20 Lecture #11 Registers, System Calls, and More Instructions
N. B. Dodge 09/09
Labels
Labels notify the program to attach a name to a data declaration or to a text (program) line. Labels allow easy reference to a specific place in the program or to an argument that is required in the program.
Each data entry must be labeled with a unique name, or label. The specific name main: MUST label the first line of text in a PCSPIM p g program. Labels are always followed by a colon (:).
Examples:
string: .asciiz Hello, Hello, world world -- Characters are named string. string. adder: add $t1,$t2,$t3 This instruction is named adder.* calc: mul $t5,$t5,$t6 -- This instruction is named calc.
* Note: Do NOT use an instruction acronym as a label. The assembler will reject it.
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Comments
Comments are VERY useful in describing what a program is doing. You may not think you need them, but in general, comments are crucial to (a) remind you what you did later on, and (b) let OTHERS know how the program works. k Comments are always preceded by a pound sign. The assembler ignores a line (or part of a line) after a #. Comment lines do not wrap wrap. A two or more line comment must have a # sign at the beginning of each line. A comment may be appended on any instruction or data line. Simply enter a # and then the comment. Examples: p add $t1,$t1,$t6 # Computing the value K. mul $s1,$t1,$t1 # Calculating the area of the square. temp: p .word 212 # Defining g temperature p constant. .main: and $t1,$t7,$t8 # Start program with logical AND.
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Reminder: Form of SPIM Program

Comments: Title, any special notes on the program, explanation of instructions or instruction groups. Comments always y defined/set off by yp pound sign g (#) only y 1/line. Text (the actual program):
Started with the .text directive. One SPIM instruction p per line; can comment on the instruction line. Each instruction must include operands and destination of result. Any text line may contain a label (but not required). The only required label is main: on the first line of text. A label must be followed by a colon (:). (:)
Data:
Starts with the .data directive. Data declarations covered later. Each data statement must include a definition and a label. Data may be listed before or after text.
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N. B. Dodge 09/09
Example Program
The example program on the following page demonstrates instructions which were covered today and last lecture. First we will examine the program listing to see the instructions and to note the terminology associated with the program, much as we did in the last lecture. Then we will see the program in execution, to get a feel for the properties of the SPIM simulator on the PC. Two notes:
We will be using PCSPIM, the MIPS assembler/simulator for the PC. SPIM versions also exist for Mac and Unix systems (XSPIM). There are differences between PCSPIM and XSPIM, many of which are minor. However, note that the program examples given are in PCSPIM. Program start is labeled differently in XSPIM.
N. B. Dodge 09/09
## ## ## ##
File lecture 11 demo program 1 Prints out answer to the question: Calculate 5*X2-3, where x=7 Output is: "answer = 242" nop li $t0, 7 move $a0, $t0 mul $a0, $a0, $t0 mul $a1, , $a0, ,5 sub $a2, $a1, 3 la $a0, ans li $v0, 4 syscall move $a0, $a2 li $v0, 1 syscall li $v0,10 syscall
Comments that name and describe i the program. Text directive: What follows is the program. main: label This is the
.text main: i
# load x (7) in $t0 start of the program. # Copy x (7) to Reg. a0 # Form X squared (7-squared or 7x7) # Form 5X squared q ( (5x7x7) ) # Form (5X squared)-3 ([5x7x7]-3) # Put string address into a0 # Load print string syscall code # Output "answer = " # Put answer in a0 (number printed out) # Load print integer syscall code # Print integer in a0 # "Done" -- i.e., stop
The program.
.data ans: .asciiz "answer = " #
Data directive: What follows is the program data. Program g data, ,p properly p y labeled. Note label followed by y a colon. Closing comment.
End of file program "lecture 11 demo program 1"
Exercise 2
Write the following program as an exercise:
Label the ASCII character group hello world (cr/lf) as str:. U th Use the appropriate i t syscall ll to t output t t th the string t i t to th the console. l Use the appropriate syscall to stop the program. Remember to use the directives for program and data. Remember to label the start of your program properly.
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N. B. Dodge 09/09
Homework
As usual:
Write down the two or three most important things you learned today and add to your list. Write down two or three things you did not clearly understand After finishing the assigned reading, understand. reading if you still have questions, see me during office hours.
Read Pervin 2-2.2 and appendices B and D. Read Patterson and Hennessy 2.4 and 2.5. Begin Homework #8.
N. B. Dodge 09/09
MIPS INTEGER and GENERAL INSTRUCTIONS Instruction * abs add addu addi addiu and/andi *b beq * beqz * bge b bgez bgt bgtz ble blez * blt bltz Arg1 rd rd rd rt rt rd label rs rs rs rs rs rs rs rs rs rs Arg2 rs rs rs rs rs rs rt label rt t label rt label rt label rt label Arg3 rt rt imm imm rt label l b l label label label label Description put the absolute value of rs into rd rd = rs + rt (with overflow) rd = rs + rt (without overflow) rt = rs + imm (with overflow) rt = rs + imm (without overflow) put rs AND rt into rd (imm (imm, not rt in andi) branch to label branch to label if (rs==rt) branch to label if (rs==0) b branch ht to l label b l if (rs>=rt) ( t) branch to label if (rs>=0) branch to label if (rs>rt) branch to label if (rs>0) branch to label if (rs<=rt) ( ) branch to label if (rs<=0) branch to label if (rs<rt) branch to label if (rs<0)
* Indicates a pseudoinstruction (assembler generates more than one instruction to produce the same result; note that the pseudoinstruction has no opcode).
MIPS INTEGER and GENERAL INSTRUCTIONS (Continued) bne * bnez div j jal jalr jr la lb lb lbu * li lui lw lw * move * mul * neg nop nor * not or ori rs rs rd label [rd] [rd] rs rd rt rt rd rt rd rd rd rd rd rd rd rd rt rt label rs label rs label address address dd number number address offset(base) ( ) rs rs rt rs rs rs rs rs rt rt imm label rt branch to label if (rsrt) branch to label if (rs0) rd = rs DIV rt jump to label jump to label; save next instruction in rd jump to instruction at (rs), save next in rd jump to instruction at (rs) load address of word at label into rd load byte at address into rt, sign xtnd l db load byte at address dd i into rt load number into rd upper halfword of rt = 16-bit number load the word at address into rd load word at addr offset+base into rd move rs to rd rd = rs rt rd = rs do nothing rd = rs NOR rt rs = bitwise logical negation of rd rd = rs OR rt rt = rs OR imm
* Indicates a pseudoinstruction (assembler generates more than one instruction to produce the same result; note that the pseudoinstruction has no opcode).
MIPS INTEGER and GENERAL INSTRUCTIONS (Concluded) * rem * rol(ror) sb * seq q * sge * sgt * sle sll slt * sne sra srl sub sw sw syscall xor rd rd rt rd rd rd rd rd rd rd rd rd rd rt rt rd rs rs address rs rs rs rs rt rs rs rt rt rt ra rt rt rt rt sa rt rt sa sa rd = rs MOD rt rd = rs rotated left(right) by ra store byte in rt to address if ( (rs==rt) ) rd=1;else ; rd=0 if (rs>=rt) rd=1;else rd=0 if (rs>rt) rd=1;else rd=0 if (rs<=rt) rd=1;else rd=0 rd = rt shifted left by distance sa if (rs<rt) rd=1;else rd=0 if (rs!=rt) rd=1;else rd=0 rd = rt shifted right by sa, sign-extended rd = rt shifted right by sa, sa 0-extended rd = rs - rt store the word in rt to address store word in rt to addr offset+base do a system call depending on contents of $v0 rd = rs XOR rt
rs rt address offset(base) rs rt
* Indicates a pseudoinstruction (assembler generates more than one instruction to produce the same result; note that the pseudoinstruction has no opcode). Note: The above list is not complete, but contains all instructions of interest in EE 2310.
Supplementary pp y Material
The following material will not be covered in the lecture. Read R d and d study d i it on your own, and d you will ill have the opportunity (last slide) to earn a homework bonus. bonus
33
N. B. Dodge 09/09
Rationale for a Computer Instruction Set

Another thing that writing programs in assembly language does for us is to give us visibility into the fundamentals of the computer instruction set. A great deal of research and development has gone into determining just what instructions a computer should embody in its repertoire, and why those instructions should exist. The study of what and how many instructions to include in a computer design is referred to as Instruction Set Architecture. The e Instruction s uc o Se Set Architecture, c ec u e, o or ISA, S ,o of a co computer pu e refers ee s not only to what instructions a computer will execute, but how those instructions relate to each other, and why a certain set of instructions make the computer effective at executing certain types of programs.
N. B. Dodge 09/09
34
Designing an Instruction Set

Many questions must be answered to determine the ISA. Some examples:
What kinds of programs will be run (graphical or media, or extended accuracy for scientific applications)? Device basis (type of manufacturing technology MOS, etc.) Integer unit size (bits) to support applications Instruction encoding (that is, how the bits in an instruction word will be p put together g to signify g y each instruction). ) Computational operations supported in hardware (for example, should there be a multiplier in hardware?). The types of data that will be manipulated and stored (fixed point or floating point, for example).
N. B. Dodge 09/09
Kinds of Instruction Set Architectures

Following are examples of some of the most pervasive ISAs over the last 30 years:
Accumulator Architecture:
CPU has 1 (and only 1) register, which is called the Accumulator. Operations always include memory reference. Example-- Add X: X + [contents of Accumulator] Accumulator, X the contents of a memory location
Memory Memory-Based Based Computational Architecture:

No registers in CPU; operations always involve operands in memory. Example p -- Add X, , Y, , Z: Contents of memory y locations Z and Y are added and stored in memory location X.
N. B. Dodge 09/09
Kinds of Instruction Set Architectures (2)

General-purpose register set: There are two classes: Non-restrictive design (may allow multiple-word instructions):
Instructions may involve both register-to-register and register-to-memory operations. Examples: add r1 r1,X,Y; X Y; rshift r3 r3, 4 4, X X, X and Y memory locations.
RISC* Load/store architecture:

All arithmetic/logical operations use register operands only. Data in memory accessible only via load and store instructions.
* Reduced Instruction Set Computer
N. B. Dodge 09/09
Advantages and Disadvantages of Architectures

Accumulator:
+ Minimizes CPU hardware and bus complexity. Maximizes memory-to-CPU traffic (slow).
M Memory:
+ Simplest possible CPU design. Very slow (was faster once upon a time, when memories were lots faster than CPUs). CPUs)
General-purpose register set, non-restrictive design:

+ Most general model for code generation, very flexible. Very V complex l CPU and d memory i interface; t f also l longer l (i.e., (i multi-word) lti d) instructions may be necessary.
General-purpose register set, RISC load/store design:

+ Single Si l memory access mode d simplifies i lifi design, d i ensures maximum i speed. d Increases total instruction count, makes programming less flexible.
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N. B. Dodge 09/09
Why RISC Load-Store Architecture is Superior*

Since 1980, logic circuits have become much faster than DRAM.
Registers are faster than main memory. Frequent memory references (except cache) slow computational speeds. speeds
Load-store architecture offers many advantages.

Operand registers can be used in any order. Do not have to go to memory to store data between computations (fast!). Load-store architectures allow very straightforward (though less flexible) programming. Fixed-length memory addresses fixed-length instructions (fast!). For a register machine, can optimize most frequently used instructions; also reduce the instructions complement to a minimum (fast!). CPU is generally less complex (fast and cheap!).
* For the present, of course things always change!
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N. B. Dodge 09/09
RISC Architecture is Effective

Consider the following analysis of Intel X86 programs: Rank 80x86 Instruction % Total executed 1 load 22% 2 conditional branch 20% 3 compare 16% 4 store 12% 5 add 8% 6 and 6% 7 sub 5% 8 move register-register 4% 9 call (procedure entry) 1% 10 return (procedure exit) 1% T t l Total 96%
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40
RISC Architecture is Effective (2)

From the previous chart, we see that although the X86 has hundreds of instructions, with tens of thousands of variations (20,000+ (20 000+ add instructions), instructions) only ten instruction types made up 96% of all instructions in most programs. general RISC load-store architecture ( (as Thus the g embodied, in our case, by the MIPS architecture), further improves efficiency by restricting the instruction set to a few very valuable (and most-used) instructions instructions. Keeping the instruction set small further reduces complexity and cost and, additionally, increases operating speed.
N. B. Dodge 09/09
Instruction Set Design and Computer Architecture

We see that the choice of ISA heavily influences the overall design, or architecture, of the computer. The clear winner is the RISC load-store architecture:
Fixed-length instructions (increases speed) Reduction in overall instructions (increases speed) Minimization of memory references (increases speed) Reduction in size and complexity of processor (speed and cost)
The MIPS, our target processor/assembly language to study is based on this victory of this ISA. The MIPS processor employs a RISC load/store ISA. ISA
N. B. Dodge 09/09
Bonus Homework Assignment

This homework assignment is worth 100 points on your homework average average. However However, it will be invisible invisible when calculating the average (thus you get an extra bundle of points, 100 maximum, without adding to the divisor when th average i the is calculated). l l t d) Turn in your answers on a separate sheet of paper. The true/false ue/ se ques questions o s may ys simply p y be marked ed T o or F, , along o g with the question number. This assignment is due at the beginning of the next class.
N. B. Dodge 09/09
Bonus Questions
Name ______________________ EE 2310 Class Section __________________ 1. 2. 3. 4. 5. 6 6. 7. 8.
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Provide a one-sentence definition of a computer ISA. (T___/F___) Fixed/floating point choice is not an important ISA condition. (T___/F___) The RISC architecture allows mathematical/logical operations directly on arguments in memory memory. (T___/F___) The old-fashioned accumulator architecture is very complex. (T___/F___) Computer memory is much faster than the CPU. (T /F ) Load and branch instructions combined occur much less often, (T___/F___) often on average, than a combination of add, and, sub, and move instructions. What does RISC stand for? (T___/F___) The fastest architecture is the accumulator architecture.
N. B. Dodge 09/09

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Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Types of MIPS Instructions

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Types of MIPS Instructions (2)

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

MIPS Special-Purpose Registers

Remember: the $ sign means register.

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Special-Purpose Registers (2)

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

MIPS Temporary Registers

NOTE: You might think of t-registers as scratchpad registers.

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

MIPS Saved Temporary Registers

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Register R i t di divided id d into fields of bits Regi ister

Lecture #11 Registers, System Calls, and More Instructions

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Lecture #11 Registers, System Calls, and More Instructions

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Immediate Format Instructions

Op Code Field (tells computer what to do ) when decoded).

Register source of part of memory address address.

Data source/ destination register.

Lecture #11 Registers, System Calls, and More Instructions

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Example p on next slide

Lecture #11 Registers, System Calls, and More Instructions

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Example Register-Register Instruction

Th U The University i it of f Texas T at t Dallas D ll

Erik Jonsson School of Engineering g g and Computer Science

This problem will familiarize you with R-R instruction formats.

Lecture #11 Registers, System Calls, and More Instructions

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science

System Calls of Interest

Th U The University i it of fT Texas at tD Dallas ll

Erik Jonsson School of Engineering g g and Computer Science