10CS 33 LOGIC DESIGN

UNIT 4 Clocks, Flip-Flops Flops

Unit 4 Session - 16 Flip-Flops

Objectives
State the cause of contact bounce and describe a solution for this problem Describe characteristic equation of flip flip-flops flops and analysis techniques of sequential circuit Describe excitation table of flip flip-flops

Switch Contact Bounce Circuits

In most of the digital systems mechanical contact switches are used for the purpose of conveying an electrical signal. Examples are the switches used on the keyboard of a digital computer system, toggle switches, and push buttons. Ideal Switch Operation Consider an ideal single pole single throw (SPST) switch circuit as shown below:

The voltage at point A, when the switch is open and closed position is shown:

B. S. Umashankar, BNMIT

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10CS 33 LOGIC DESIGN

UNIT 4 Clocks, Flip-Flops Flops

Contact Bounce When the contacts of any mechanical switch bang together they rebound a bit before settling, causing bounce. The voltage waveform at the switch output will have multiple transitions as shown below:

Debouncing is the process of removing the bounces. Debounce Circuit A simple RS latch can be used to debounce a mechanical switch switch. . The debounce circuit that uses a simple RS latch is as shown:

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10CS 33 LOGIC DESIGN

UNIT 4 Clocks, Flip-Flops Flops

The debounce circuit will eliminate the switch bounce as illustrated below:

Various Representations of Flip Flip-Flops

There are various ways a flip-flop can an be represented, each one suitable for certain application. application They are: Truth Tables or Characteristic Tables Characteristic Equations Finite State Machine Excitation Table

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10CS 33 LOGIC DESIGN

Truth Tables

UNIT 4 Clocks, Flip-Flops Flops

The truth tables of different flip-flops flops are shown below:

Characteristic Equations The characteristic equations of flip flip-flops flops are useful in analyzing circuits made of them. them Here, next output Qn+1 is expressed as a function of present output Qn and inputs to flip-flop. Characteristic Equation of SR Flip-Flop Flop The characteristic equation of SR flip flip-flop is obtained as shown below:

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10CS 33 LOGIC DESIGN

Characteristic Equation of D Flip-Flop Flop

UNIT 4 Clocks, Flip-Flops Flops

The characteristic equation of D flip flip-flop is obtained as shown below:

Characteristic Equation of JK Flip-Flop Flop The characteristic equation of JK flip flip-flop is obtained as shown below:

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10CS 33 LOGIC DESIGN

Characteristic Equation of T Flip-Flop Flop

UNIT 4 Clocks, Flip-Flops Flops

The characteristic equation of T flip flip-flop is obtained as shown below:

Drawback of Truth Table For a complex circuit a truth table is difficult to read as its size becom becomes es too large. large In finite state machine (FSM), functional behavior of the circuit is explained using finite number of states. states Finite State Machine In a sequential logic circuit the value of all the memory elements at a given time define the state of that circuit at that time. A FSM is a system that can be described by the states it can assume, the state it starts in, the input it receives, and how it changes state state. Flip-Flop as Finite State Machine flops can be conveniently represented by a finite state machine. State transition diagram is a very Flip-flops convenient tool to describe an FSM FSM. The state transition diagrams of different flip-flops flops are as shown: SR Flip-Flop

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10CS 33 LOGIC DESIGN

D flip-flop

UNIT 4 Clocks, Flip-Flops Flops

JK flip-flop

T flip-flop

Timing Relation The timing relation implicit in flip-flop flop truth tables are brought to the forefront by FSM concept and state transition diagram. The timing relation implicit in flip flip-flop flop truth tables are brought to the forefront by FSM concept and state transition diagram diagram.

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10CS 33 LOGIC DESIGN

Flip-Flop Excitation Table

UNIT 4 Clocks, Flip-Flops Flops

Truth tables are important in analysis problems problems. Excitation tables show the required input trigger signals required for the desired flip flip-flop state transition. Excitation tables are very useful in synthesis or design problems. The excitation tables ables of different flip flip-flops are as shown: Excitation Table of SR flip-flop

Excitation Table of D flip-flop

Excitation Table of JK flip-flop

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10CS 33 LOGIC DESIGN

Excitation Table of T flip-flop

UNIT 4 Clocks, Flip-Flops Flops

Example: flop with two inputs A and B functions like this. For AB=00 and 11 the output becomes 0 A fictitious flip-flop and 1 respectively. For AB = 01, flip flip-flop flop retains previous output while output complements for AB = 10. Draw the truth table and excitation table of this flip flip-flop. Solution The truth table and excitation table e of the Fictitious Flip-Flop is as shown:

Analysis of Sequential Circuits

A sequential logic circuit contains flip flip-flops flops as memory elements and may also contain logic gates as combinational circuit elements. Analysis of a circuit helps to explain its p performance. Example: Analyze the given sequential circuit:

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10CS 33 LOGIC DESIGN

UNIT 4 Clocks, Flip-Flops Flops

Solution: From the circuit diagram, we have the flip flip-flop input relations:

SA = An SB = AnBn

R A = An RB = AnBn

Using characteristic equation of SR flip flip-flop: Qn+1 = S + RQn, we can write for flip-flop flop A:

An+1

= SA + RAAn = An + An An = An

For flip-flop B we have:

Bn+1

= SB + RBBn = AnBn + (AnBn)Bn = AnBn + (An + Bn)Bn = AnBn + AnBn = An + Bn

The output from the given circuit,

Xn = AnBn
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10CS 33 LOGIC DESIGN

UNIT 4 Clocks, Flip-Flops Flops

If present state is An = 0 and Bn = 0, then present output Xn = 0.0 =0 At the end of the first clock cycle we get the next state:

An+1 = An = 0 = 1

Bn+1 = An + Bn = 0
State Analysis Table

State Transition Diagram

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10CS 33 LOGIC DESIGN

Timing Diagram

UNIT 4 Clocks, Flip-Flops Flops

Questions
1. Find out characteristic equations of J J-K flip-flop and D flip-flop. 2. Write the excitation table of J-K K flip flip-flop.

Further Reading
Donald P Leach, Albert Paul Malvino & Goutam Saha: Digital Principles and Applications, 7th Edition, Tata McGraw Hill, 2010.

B. S. Umashankar, BNMIT

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