[1]

PREFACE
Radiation detection and measurement are principle techniques for nuclear and
particle physics experiments. A spectroscopy operated with good resolution at high
DAQ speed should be considered in further researches.
To achieve the goal, research groups, companies, universities, etc. has spent
time in developing every part of a spectroscopy, such as: power supply, detector,
amplifier, preamplifier, multichannel analyzer, etc. Traditionally, a spectroscopy is
built by an analog chain, which is combined from a number of analog devices. In
recent decades, FPGA chip with DPP algorithm and LabVIEW
TM
interface were
experimented and aimed some advantages with low-cost [8], better resolution [7]
and ease of migration of technology between different experiments [8], [10].
With the achieved benefits, a project on development of MCA based on Flash-
ADC/FPGA with DPP algorithm, and LabVIEW
TM
interface has been triggered
since 2010. So far, the MCA (Flash-ADC/FPGA) has been able to detect and
digitally present analog signals from analog amplifier with high accuracy by
analogy with digital oscilloscope [2], [3], [13]. Especially, in 2011, the development
of MCA reached a new step when the calculation for precise tasks of MCA, such as
trigger timing, height of pulse, integration of pulse, pedestal, etc., was managed
inside FPGA chip and simultaneously built up a radiation histogram in LabVIEW
TM

interface [2].
However, the DAQ speed of MCA (Flash-ADC/FPGA) is not high and may
be caused by the DPP algorithm is not suitable with transmission speed of RS-232
cable. To solve this problem, a memory already created inside FPGA chip is used.
In this memory, storing digitalized data and downloading data to computer work
independently with each other. In a presence of the memory, which is a supplement
to DPP algorithm, the MCA (Flash-ADC/FPGA) is functioned with faster and more
accurate DAQ.
[2]

The MCA (Flash-ADC/FPGA) with new supplied DPP algorithm is evaluated
with pulse generator to figure its DAQ speed. With expected consequence, a
spectroscopy is set up with the updated MCA (Flash-ADC/FPGA), and two
radioisotopes
133
Ba and
152
Eu for evaluation of new responses. Results from two
experiments are compared with the results of old DPP algorithm. Useful details of
this thesis are described below:
- Chapter 1: Introduction to basic interactions of radiations, scintillator
detector, Flash-ADC, and FPGA.
- Chapter 2: Introduction of MCA module used in this thesis with DPP,
Histogram Memory in VHDL code, and LabVIEW
TM
interface.
- Chapter 3: Experiments and results with pulse generator and radioisotopes
and comparison with old VHDL code.
The conclusions give summary of results. In proposals section, some
recommended ideas to improve the system are suggested.
[3]

Chapter 1
BACKGROUND
1.1. Radiation Interaction with matter[1], [11]
Nuclear radiations contain the radiations generated from conversions related to
nuclei or atoms such as: radioactive transformation, nuclear reaction, etc. For this
reason, nuclear radiations can be divided into two types:
- Charged particulate radiation: light charged particles including electron and
positron; heavy charged particles such as alpha, proton, fission fragments
and products of nuclear reactions.
- Uncharged radiation: electromagnetic radiation (consists of X-ray and -ray
(gamma ray)) and neutron.
When a charged particle penetrates matter, it interacts with atomic electrons.
By its electromagnetic field, atoms are excited or ionized. Charged particle loses its
energy gradually due to inelastic collision and elastic scattering (Fig.1.1) with
matter before it stops. This means the range of a charged particle in matter is
restricted. In addition, a light charged particle also loses its energy by
bremsstrahlung (Fig.1.2). In particular, losing energy by bremsstrahlung occurs
obviously with a high-energy light charged particle and causes considerable
inaccuracy in detection using ionization effects.

Fig.1.1. Collision of charged particle Fig.1.2. Bremsstrahlung of beta
Charged
particle
Electron
Nucleus
Bremsstrahlung
Beta
particle
Electron
Nucleus
[4]


Fig.1.3. Diagram of photoelectric effect Fig.1.4. Graph of cross section of
. photoelectric effect [12]

Fig.1.5. Diagram of Compton scattering Fig.1.6. Graph of cross section of
. Compton scattering [12]

Fig.1.7. Diagram of pair production Fig.1.8. Graph of cross section of
. pair production [12]
Gamma ray (-ray) is a kind of electromagnetic wave whose range is greater
than those of charge particle. Beside the wave characteristic, gamma ray also
behaves with the characteristic of particle so that we can call it gamma quantum.
Electron
Nucleus



Electron
Nucleus


K
p

K
e

Electron
Nucleus

Positron
[5]

Like charged particle, gamma ray also interacts with matter and be absorbed by
medium around it, almost caused by electromagnetic interaction. Three main
interactions of gamma ray with matter are: photoelectric effect (Fig.1.3), Compton
scattering (Fig.1.5), and pair creation (Fig.1.7) with cross sections (Fig.1.4, Fig.1.6,
and Fig.1.8).
1.2. Scintillator detector [1], [11], [12]
Scintillator detector is commonly used in nuclear and particle experiments
nowadays. It makes use of flashes of light emitted by interactions of radiations with
material.
Flash light in organic scintillator
Flashes are emitted by transmission in energy level. When a radiation arrives
and ionizes one atom, atomic electron transmits to a higher electron level so that
atom also reaches to a greater energy level. As we can see in Fig.1.9, electron
transmits from S
0
(ground state) to the higher level (excited level S
3
). After that, it
returns to the ground state by vibration and photon emission. The emitted photon
excites another electron and makes it transmit to state S
2
. Likewise, photon
emission makes the electron be back to the lowest level, and also excites a nearby
electron. However, the next emitted photon, regarding to the transmission of
electron from S
1
state back to S
0
state, is the last one because its energy cannot
excite any more electrons. The latest photon is used in further electronic processes.
Fig.1.9. Flash light in Organic Scintillator
S
1
S
0
S
2
S
3
[6]
Flash light in inorganic scintillator
Whereas the mechanism in organic scintillator is related to molecular, flash of
light in inorganic material is generated by characteristic of crystals electronic band
structure. Electronics band consists of: conducting band, forbidden energy trap, and
valence band as be shown in Fig.1.10. When a radiation ionizes an atom, an atomic
electron, in valence band, moves to conducting band. If this excited electron returns
back to valence band and not be hold back by crystal lattice defect, photon emitted
in this transition would be absorbed. Impurity atoms are included inside the
structure of scintillator in order to create energy gaps. The aforementioned electron
is struck at these gaps, and emits photon with the left energy.

Fig.1.10. Flash light in Inorganic Scintillator
Photomultiplier tube
After photon is generated, it is conducted to photomultiplier tube (PMT) for
converting photon to electronic signal (Fig.1.11). As be shown in Fig.1.12, PMT
consists of: photocathode, electron optical input system, focusing electrode, electron
multiplier section (or dynode string), and anode. Incident photon strikes the
photocathode, which is made of a photosensitive material, and electron is emitted
via photoelectric effect. High voltage is applied during the operation along the
length of cathode dynodes anode as a voltage ladder. Due to this high voltage,
the electron is directed and accelerated and then hits the first dynode and generates
secondary electron. These electrons immediately hit the second dynode by higher
Forbidden
Energy trap
Impurity
traps
Valence band
Conduction band
[7]
voltage applied to this dynode and more electrons are produced in this next strike.
The following collisions are continued in turn and the result is an electron cascade.
This electron cascade is collected by anode and becomes a current for amplifying
and analyzing.

Fig.1.11. Scintillator Detector Fig.1.12. Photomultiplier Tube [12]
1.3. Multichannel analyzer [11]
A multichannel analyzer (MCA) is a device which can sort out and present in-
coming pulse from amplifier according to height of pulse (or also integration of
pulse). To facilitate this, a MCA is operated through number of devices: Analog-to-
Digital Converter (ADC), control logic, and a memory, which is illustrated in
Fig.1.13. Function of ADC is to digitize in-coming pulse which is an analog pulse.
In order to give the ADC sufficient time to digitize input signals, a number of
modules exist used for adapting signals. After that, the logic control unit analyzes,
locates, and counts a number of these heights. Analyzed heights are stored in the
memory. In this way, MCA takes not only in-coming pulses, but also increments of
memory. The number of channels into which the height of pulse is digitized is
called conversion gain. Conversion gains dictate the resolution of MCA and can be
up to 8000 or 16000 channels, which is found in commercial MCAs.

Fig.1.13. MCA architecture
Radiation
ray
Scintillator Light
guide
PMT
Scintillator
molecule
Photon Electron
First dynode Photocathode
Electron
optical
input
Focusing
electrode
Multiplier
(dynodes)
Anode
ADC
Control Logic
Memory
Display
[8]
1.4. Flash-ADC/FPGA
1.4.1. Flash-ADC (Flash Analog-to-Digital Converter) [9], [11]
Flash-ADC is a simplest ADC with a fastest architecture. In Flash-ADC, there
are a number of resistors and comparators. A Flash-ADC is always considered by
two properties: resolution and sampling speed. Resolution of a Flash-ADC is up to
8 bits at sampling speed in hundreds of MHz for variety applications. In Fig.1.14,
strobe affects the frequency (speed) of Flash-ADC, whereas, comparators, resistors,
and V
FS
affect the resolution. The higher resolution, the Flash-ADC digitizes, the
more number of comparators, and resistors are contained. An n-bit Flash-ADC
needs 2
n
resistors and 2
n
-1 comparators. The resistors help to divide the V
FS
voltage
and the comparators function is to compare the input voltage with divided voltage.
By thermometer code, the result of comparison is a binary number which
corresponding to bits of Flash-ADC. More particularly, in the binary string, 1 is
written on when input voltage is higher the divided one, and 0 is written in the
other case.

Fig.1.14. Flash-ADC architecture [9]
[9]
1.4.2. FPGA [5], [6]
FPGA is one of three categories of high-capacity FPD (Field-Programmable
Device) beside Simple Programmable Logic Device (SPLD) and Complex
Programmable Logic Device (CPLD). A FPGA contains IOBs (Input/Output
Blocks), CLBs (Configurable Logic Blocks), and Interconnects (Fig.1.15). CLBs
are the programmable blocks, which we can calculate, or process, digital signals.
IOBs are the connections between FPGA with other DAQ hardware, and computer.
Interconnects connect CLBs to CLBs or CLBs to IOBs. Operation and combination
in FPGA are modified in C code, MATLAB code, LabVIEW
TM
graphical block
diagrams, and HDL (Hardware Description Language), such as: VHDL, Verilog,
AHDL (Altera Hardware Description Language), etc. As time gone by, FPGAs
become common all over the world in many educations, developments, and projects
related to DPP.

Fig.1.15. FPGA architecture [6]
I/O
pad
Logic
Block
Interconnects
[10]
Chapter 2
DEVELOPPING MCA (FLASH-ADC/FPGA)
In this chapter, we describe the development of Multi-Channel Analyzer
(MCA) based on Flash-ADC 250MHz-8bit resolution and embedded FPGA trigger.
The development of MCA (Flash-ADC/FPGA) includes embedded-VHDL code for
digital pulse processing (DPP) and histogram memory. Computer LabVIEW
interface is developed for trigger and DPP controlling, histogram-data taking, and
histogram displaying.

2.1. MCA (Flash-ADC/FPGA)

Fig.2.1. Diagram of Radiation Spectrometry using Flash-ADC/FPGA

Fig.2.2. Module Flash-ADC/FPGA (top view and side view)
The MCA based on Flash-ADC and FPGA analyzes pulse signal in two main
steps. First step, MCA detects and digitalizes signals with Flash-ADC. Second,
digitalized data is computed in FPGA. Data flow and conversions are described in
Fig.2.1. Fig.2.2 is the combination board of Flash-ADC and FPGA.
Upload to
computer
Multichannel Analyzer
(MCA)
Detector Pre-Amp Amp Flash-ADC FPGA
Flash-ADC
FPGA
[11]

Fig.2.3. Module Flash-ADC 250 MHz 8-bit

Fig.2.4. Module FPGA
Flash-ADC (Flash Analog to Digital Converter)
The Flash-ADC module in Fig.2.3 contains two input channels: channel A and
channel B. This module can digitalize analog signal at 250 MHz speed (i.e.
2.5x10
8
samples/second or 4ns/sample) in 8-bit resolution (is equivalent to 256
amplitude channels). Maximum amplitude that Flash-ADC can handle is 1000mV.
Converting signal consists of converting in amplitude versus time and converting in
timing. Converting in Amplitude fixes 1000mV with 256 amplitude channels or
4mV corresponds to 1 channel. Converting in Timing is 4nsec/bin [9].
FPGA (Field of Programmable Gate Array)
FPGA chip in this module (Fig.2.4) is the Cyclone II EP2C8Q208C7
manufactured by Altera Corporation. This chip contains 182 PORTs (input, output,
and in-out), 8256 logic blocks, 165888 RAM bits, etc. [4]. FPGA is programmed by
VHDL to compute specific tasks with digital signal such as: trigger timing,
integration of pulse, height of pulse, etc.

Channel A
Voltage offset A
Channel B
Voltage offset B
FPGA chip
RS-232
COM
PORT
+5V input
-5V input
JTAG
USB
Blaster
[12]
2.2. VHDL code

Fig.2.5. Flow chart of processing in FPGA
The VHDL code consists of five components: Local Trigger, L1_delay,
executer, bus_ctrl_232c and finesse_PLL [2]. The operation of these components
can be divided in two processing: Digital Pulse Processing and Storing in
Histogram Memory. Schematic algorithm for VHDL code is shown as in Fig.2.5.
Section 2.2.1 and section 2.2.2 are simply explanations for these two processes.
RS232
Upload:
Stored histogram
Computer
Flash-ADC

Trigger
Store in
buffer
- Height of pulse
- Integration of pulse

- Integration = Memory
Channel
- Store in Histogram
Memory

Digital
Pulse
Processing
Histogram
Memory
[13]
2.2.1. Digital Pulse Processing (DPP)
Free-running Flash-ADC transmits digitized data, whose shape is shown in
Fig.2.6, to FPGA.

Fig.2.6. Digitized pulse signal
The development of DPP is performed in steps as follows:
First step: Triggering data: The FPGA receives digitized signal from Flash-
ADC in certain frequency. For triggering, digitized data is to compare with trigger
level. There are two different triggering modes: rising edge and falling edge. In this
work, rising edge triggering is considered for gamma spectroscopy. This
demonstrated in Fig.2.7.

Fig.2.7. Rising edge
Second step, data are kept in a buffer, which functions as a matrix does. This
buffer contains a variable named pointer functioning as a writing cursor. Size of
this buffer, or maximum value of pointer in this buffer, is set manually in order to
detect all single data of digital signal. In this step, a datum is kept in the buffer
when pointer is assigned 0. Repeatedly, other data are stored in buffer and
A
m
p
l
i
t
u
d
e

C
h
a
n
n
e
l
s

Time bin
Single
datum
A
m
p
l
i
t
u
d
e

(
V
)

Time bin
Trigger level
[14]
pointer is increased until this buffer is full. Afterwards, data of digital signal are
all kept in the same buffer. Digital pulse signal is stored in buffer as shown in
Fig.2.8.

Fig.2.8. Storing data in buffer
Based on data in the buffer, we calculate two important tasks used in building
radiation histogram: height of pulse and integration of pulse. In the VHDL code,
calculating integration depends on height of the pulse. Therefore, height of pulse is
carried out formerly. The process to find and locate height of pulse occurs in the
buffer. At first, pointer and a variable max are assigned value 0. Then, we
compare max with a datum which corresponds to pointer. Only if this
datum is greater than max, max is assigned value of datum and posi_max
(position of maximum value) is assigned value of pointer. Next, pointer is
increased by one and datum at the new pointer is compare with max. This
loop redoes until pointer reaches its maximum value. Finally, result of this
process is height of pulse (variable max) with its position in buffer (variable
posi_max). The algorithm to find and locate the height of pulse is shown in
Fig.2.9.
A
m
p
l
i
t
u
d
e

C
h
a
n
n
e
l
s

Elements
(Time bin)
[15]

Fig.2.9. Flow chart of algorithm for height of pulse
After having the height of pulse and its position (posi_max) in buffer, we
calculate the integration of pulse with included parameters: left peak and right peak
(Fig.2.10). These two parameters bound the number of buffers elements which are
used for calculating integration. Left peak stands for number of elements on the left
side of posi_max. Likewise, right peak stands for number of elements on the right
side of posi_max. To describe more simply, we imply that left peak and right
peak are corresponding to L elements and R elements. In the bounded range,
data are combined and become integration of pulse.
In this algorithm, two variables pointer and sum are assigned value 0. If
value of pointer is in range of posi_max L to posi_max + R, sum is
increased by value of datum corresponding to pointer. Nothing occurs if
pointer is not in the aforementioned range. Afterwards, one is added to value of
max = datum(pointer)
posi_max = pointer

pointer = 0
Max = 0

datum(pointer) >
max
TRUE
FALSE
TRUE
pointer = pointer + 1

pointer =
[size of buffer]
Integration process
FALSE
[16]
the pointer. If value of pointer reaches its maximum value, this loop is stopped.
In contrast, the process is repeated and sum is added data value corresponding to
the value of pointer which must be in range. At the end, after combining all the
data, result is the integration of pulse as the value of variable sum. Diagram of
algorithm is shown in Fig.2.11.

Fig.2.10. Integration and calculated variables

Fig.2.11. Flow chart of algorithm for integration
Integration
of Pulse
A
m
p
l
i
t
u
d
e

C
h
a
n
n
e
l
s

Elements in Buffer
(Time bin)
Height of
Pulse
Left Peak
Right Peak
FALSE
posi_max - L
< pointer <
posi_max + R
sum = sum + datum(pointer)
pointer = pointer +1
pointer = 0
sum = 0

pointer =
[size of buffer]
Storing in HM
TRUE
FALSE
TRUE
[17]
2.2.2. Histogram Memory

Fig.2.12. Flow chart of building histogram up in memory
The VHDL code embedded into FPGA allows MCA speeds DAQ up and
analyzes in higher resolution. To achieve goals, a memory contained already inside
in the FPGA is used to build up a histogram inside FPGA. Fig.2.12 should be
concerned to figure the memorys operation. The variable m is the input value of
the memory. Variety value of m effects different elements of memory. Actually, the
m
th
element would be increased by one. Due to own ability and function, the
memory is named histogram memory (HM).
HM contains 6 main variables (Fig.2.13):
- data: the pulses integration, which is also the major input for processing.
- wraddress: assigned a value corresponds to an element of the matrix.
This element is the HMs position which a new computed value is written to.
- rdaddress_a and rdaddress_b: used for readout value of elements.
- qa and qb: the value of output data.
0
a[0] a[1] a[2] a[i] a[n]
a[0]
+ 1
a[1]
+ 1
a[2]
+ 1
a[i]
+ 1
a[n]
+ 1

1
2
i
n

[18]

Fig.2.13. HMs variables
The memory is built on the idea of cursors and matrices. Three cursors in this
process are: wraddress for writing data to the memory, otherwise rdaddress_a
and rdaddress_b are used for reading data out. Moreover, there are two matrices
(matrix A and matrix B) inside the memory and each matrix has reading cursor and
output data which are independent to writing cursor. To make use of this advantage,
rdaddress_a and qa in matrix A are used in calculating while rdaddress_b and
qb transmit data continuously. This idea results in the separation between
processing and transmission. Because of this separation, we divide the explanation
of the operation into two parts: writing data to histogram memory and updating data
from histogram memory.
Write data to Histogram Memory
To separate the processing and the transmission of data, a Boolean variable
stop is created. If stop is equal to 0, processing occurs, and transmission is
carried out if 1 is assigned value to stop. Three input variables rdaddress_a,
wraddress, and data are assigned 0. After abovementioned process, if sum is
in the range of 0 to 4095, it is assigned value to rdaddress_a. This means reading
cursor moves to the corresponding elements in matrix A (matrix of processing) and
to read out a datum. This datum is increased by one then assigned to data. The
wraddress moves to the aforementioned element right after then. Therefore, value
[19]
of that element is increased by one. These steps redo step by step so that HM is
updated every moment. Algorithm of writing data on HM is shown in Fig.2.14.

Fig.2.14. Flow chart of writing data to HM
Update data from Histogram Memory

Fig.2.15. Flow chart of states of system in reading process
TRUE
FALSE
TRUE
rdaddress_a = 0
wraddress = 0
data = 0
sum < 4095
rdaddress_a = sum

data = qa(sum) + 1
wraddress = sum

stop = 0
Reset
Histogram Memory
Reading process
Update latest data
Update data
continuously
stop = 0
TRUE FALSE
[20]
The reading process (uploading process) is also controlled by the Boolean
variable stop, as the writing process is. However, the writing process works only
if value of stop is 0. In reading process, there are two cases, or two states of
system, based on the Boolean value of stop for the process works. First of them is
the state that FPGA uploads data to the computer continuously. The writing process
and the reading process in this case can be understood as the parallel processing. In
the second state, uploading processing is carried out with a frequency. This
frequency is manipulated purposely by users. To simplify the explanation, we name
two states continuous uploading and frequent uploading, which are shown in
Fig.2.15.

Fig.2.16. Flow chart of continuous uploading in reading process
First, we discuss the continuous uploading whose algorithm is described in
Fig.2.16. Since data is uploaded continuously, histogram in the computer is built up
continually. This state is processed parallel with writing process because value of
TRUE
rdaddress_b = 0

FALSE
Upload: qb, stop,
rdaddress_b
stop = 0
TRUE
rdaddress_b =
rdaddress_b + 1
rdaddress_b
= 4095
[21]
stop is 0.Variable rdaddress_b is firstly assigned 0. After assigning, qb, as
the output corresponding to rdaddress_b, is uploaded to computer with
rdaddress_b and stop. The reason why stop must be uploaded is discussed
furthermore in the frequent uploading. By the time uploading is finished,
rdaddress_b is increased by one. If rdaddress_b is lower than 4095, FPGA,
again, uploads it with the new qb and stop. When rdaddress_b is equal to
4095 and keep the continuous uploading up. The process works in this state
uninterruptedly until stop is equal to 1.When experimenting with the MCA
(Flash-ADC/FPGA), we prefer to save data on a file to analyze. Using data in
continuous uploading state is not convenient because calculation of the huge
amount of data after long time measurement should be carried out before analyzing.
Therefore, frequent uploading is considered to save file with no calculating.
As we can see in Fig.2.15, frequent uploading is processed only if stop is
assigned 1, the case that writing process stops. Consequently, writing
process does not happen during frequent uploading. Two steps conducted in
turn in the frequent uploading are: updating latest data to computer and
resetting Histogram Memory. When stop is equal to 1, writing process is
stopped, and the FPGA updates latest data. At this time, FPGA does not write any
more data to HM so that the uploaded data is the latest data. Updating latest data
happens in the same way as continuous uploading does. After updating latest data
finishes or rdaddress_b is equal to 4095, the HM is reset. This means all HMs
elements are assigned 0. The input data is assigned 0 during resetting time. Variable
wraddress is assigned 0 at first, and then it is increased by one every time after
assigning 0 to a corresponding element. Resetting Histogram Memory is totally
completed when 4096
th
element is assigned 0. After finishing continuous
uploading, the process assigns 0 to rdaddress_b and chooses state to read data
by checking value of stop. This reading process occurs again and again as a loop.
Fig.2.17 shows the algorithm of frequent uploading.
[22]

Fig.2.17. Flow chart of frequent uploading in reading process
The switch from continuous uploading to frequent uploading is caused
by the change of Boolean variable stop. The change of stop is described to see
the connection between these two states. A control parameter time_in is
transferred from computer to FPGA. This parameters value is the time, in second
unit, to change the value of stop from 0 to 1. At the beginning, value of stop
TRUE
FALSE
FALSE
TRUE
Upload: qb, stop,
rdaddress_b
rdaddress_b
= 4095
wraddress = 0
data = 0
wraddress =
wraddress +1
rdaddress_b =
rdaddress_b + 1
wraddress =
4095
rdaddress_b = 0
stop = 0
FALSE
[23]
is 0. A variable named count_time is increased every second until it is equal to
the time_in. When count_time is equal to time_in, stop is assigned 1 and
count_time is reset to value 0. The opposite convert of stop occurs only if
reading process is at the last step of resetting Histogram Memory. Fig.2.18 shows
the algorithm of stop process.

Fig.2.18. Diagram of stop process
2.3. Computer Interface using LabVIEW
TM
software

Fig.2.19. LabVIEW
TM
Interface
count_time
time_in
count_time =
count_time + 1
stop = 0
stop = 1
FALSE
TRUE
Resetting
is done
TRUE
1 2 3 4
5 6 7 8
9
10
11
12
14
15
13
[24]
The interface program built on LabVIEW
TM
software interacts with the FPGA.
In Front Panel, the interface for users, the program not only exhibits received data
in indicators (numbered in blue) but also transfer parameters to manipulate MCA
with controls (numbered in red), as shown in Fig.2.19.
#1: trigA
Function: sets trigger for input data, trig means trigger and A means channel A.
#2: LeftPeakA and #3: RightPeakA
Function: the Left Peak and Right peak have been concerned in 2.2.1.
#4: Time to stop (s)
Function: time of measurement, the variable Time_in has been concerned in 2.2.2.
#5: COM PORT
Function: select the computers COM PORT where data is transmitted to.
#6: Number Data Out
Function: the size of buffer, which has been concerned in 2.2.1.
#7: Delay
Function: the number of buffers elements between writing cursor and reading
cursor.
#8: Time_bin
Function: the interval between two detecting events times.
#9: Type Data out
Function: choose 1 to present pulse signals or choose 2 to present the spectrum.
#10: Trigger up/down
Function: choose 1 for rising edge case or choose 2 for falling edge case.
#11: Trigger Channel
Function: choose 1 to detect only channel A of Flash-ADC, choose 2 to detect
only channel B of Flash-ADC or choose 4 to detect both channel A and B of
Flash-ADC.
#12: write data
Function: if this button is pressed, the data is written into a file.
[25]
#13: (signals or spectrum)
Function: presents pulse signals if Type Data out is equal to 1 or spectrum if
Type Data Out is equal to 2
#14: (counts of events)
Function: presents the number detected events in an acceptable range
#15: (transmitted data)
Function: presents number of events in #14, channel, counts as in Fig.2.20.

Fig.2.20. Indicator of transmitted data (in Hexadecimal-base 16)
The file contains data in two columns (channels and counts) can be saved in
different formats. Moreover, for convenient uses, we can save it as file.tka
(Fig.2.21) and then use Genie2K for analysis (Fig.2.22).

Fig.2.21. Saved data Fig.2.22. Analysis in Genie2K
Number of events
Channel Counts per Channel
Channels
(0 to 4095)
Counts
[26]
Chapter 3
EVALUATION OF MCA AND
GAMMA SPECTROMETRY NaI(Tl) 3inch x 3 inch
In chapter 2, we discussed in detail the development of MCA (Flash-
ADC/FPGA). In this chapter, we use a pulse generator to evaluate the dead-time of
the MCA (Flash-ADC/FPGA), in section 3.1. Two standard radioisotopes
133
Ba and
152
Eu including multi gamma energies ranging from several tens keV to MeV are
used to figure the gamma response and energy resolution for gamma spectroscopy
with the uses of MCA (Flash-ADC/FPGA) and scintillator detector NaI(Tl) 3inch x
3inch, in section 3.2.
3.1. Evaluation of MCA using Pulse Generator

Fig.3.1. Pulse Generator layout in laboratory

Fig.3.2. Diagram of pulse generator experiment
LabVIEW
TM
interface
MCA (Flash-ADC/FPGA) Pulse Generator
Amplifier
Oscilloscope
RS-232
Digital Oscilloscope for monitoring
Pulse
Generator
Amplifier
MCA
(Flash-ADC/
FPGA)
Computer
LabVIEW
interface
[27]
Experiments with pulse generator are carried out with the same layout (in
Fig.3.1 and Fig.3.2). Microcal Origin 6.0 is used to display spectrum and analyze
data. Pulse Generator is a module made in Osaka University, Japan. Pulse
Generator is a module containing EP1C6T144C8 FPGA chip which is embedded a
VHDL code to generate square pulses (Fig.3.3). These pulses are fed into a shaping
amplifier, type CANBERRA 2026 amplifier, and then connected to the input
channel of MCA (Flash-ADC/FPGA). Data out of FPGA module is downloaded to
computer via RS-232 cable.

Fig.3.3. Trigger module as Pulse Generator
The VHDL code embedded into FPGA makes the Pulse Generator module
generate pulses in different frequencies by variable freq and amplitudes by
variable width. Value of frequencies and amplitudes are indicated in Table 3.1
and Table 3.2.
The frequencies generated in Table 3.1 are connected with variable freq by
equation 3.1.

6
(freq+1)
25 . 10
Frequency (Hz) =
2

(3.1)

Amplitudes detected by LabVIEW
TM
interface in Table 3.2 are resulted from
the equation 3.2

Channel
Amplitude (mV) = x 1000 (3.2)
255

NIM out
ports
FPGA
chip
Power
supply
ports
[28]
Table 3.1. Variable freq and frequency
freq
Freq
(Hz)
0 12500000
1 6250000
2 3125000
3 1562500
4 781250
5 390625
6 195313
7 97656
8 48828
9 24414
10 12207
11 6104
12 3052
13 1526
14 763
15 381
16 191
17 95
18 48
19 24
20 12



[29]

Table 3.2. Amplitudes of pulses in oscilloscope and LabVIEW
TM
interface
width
Amplitude in
oscilloscope
(mV)
Amplitude in
LabVIEW
(mV)
1 60 51.0
2 110 101.9
3 160 149.0
4 210 207.8
5 260 258.8
6 300 298.0
7 330 325.5
8 350 345.1
9 380 372.5
10 400 396.1
11 420 419.6
12 450 443.1
13 470 466.6
14 490 486.3
15 520 513.7
16 540 537.2
17 560 556.8
18 580 576.5
19 610 600
width
Amplitude in
oscilloscope
(mV)
Amplitude in
LabVIEW
(mV)
20 630 623.5
21 650 647.0
22 670 666.6
23 700 686.3
24 720 709.8
25 740 733.3
26 760 749.0
27 780 768.6
28 800 792.1
29 820 815.7
30 840 835.3
31 860 858.83
32 880 874.5
33 900 898.0
34 920 917.6
35 940 945.1
36 960 964.7
37 980 984.3
38 1000 1000.0

First experiment is time response experiment with stable amplitude and varied
frequencies to figure the highest speed of MCA (Flash-ADC/FPGA). Next, the
suitable parameters are adapted for later experiments.
[29]
3.1.1. Evaluate the time response
We examine at the frequency varied from 12Hz to 12207Hz, and 400mV
amplitude in oscilloscope, during this experiment. Detected pulses are parallel
displayed in GW INSTEK GDS-1000A oscilloscope and LabVIEW
TM
pulse
interface (Fig.3.4a), which is used in previous thesis [2]. The pulses dimensions
(time bin and amplitude) in oscilloscope and in LabVIEW
TM
pulse interface are
similar to each other [2], [3].
Table 3.3. Set up parameters in time response experiment
Apparatus Parameters Value
Canberra 2026 amplifier
Coarse gain 20
Fine gain 5-1.0
Shaping time 6sec
LabVIEW
TM
spectrum interface
Time to stop 100sec

Left Peak 30
Right Peak 30
Number Data Out 100
Delay 60
Time bin 50
TrigA 70

Fig.3.4. LabVIEW
TM
pulse interface (a) and LabVIEWTM spectrum interface (b)
(a) (b)
[30]
Because a full pulse scale results in a best resolution for later experiments [2],
parameters in LabVIEW
TM
pulse interface are manipulated to reach this quality.
Table 3.3 is the parameters of amplifier and LabVIEW spectrum interface.
Table.3.4. DAQ speed of MCA (Flash-ADC/FPGA)
Frequency (Hz) DAQ speed (ms/event) Events/sec (sec
-1
)
12 82.99 12.05
24 41.51 24.09
48 20.76 48.17
95 10.38 96.33
191 5.19 192.65
381 2.59 385.29
763 1.30 770.57
1526 0.66 1541.12
3052 0.33 3082.24
6104 0.33 3082.24
12207 0.24 4109.96

Fig.3.5.Graph of DAQ of MCA
[32]
Appropriate parameters are used in LabVIEW
TM
spectrum interface (Fig.3.4b)
to detect events and examine the spectrum. Time of measurement is 100 seconds.
Table 3.4 indicates the detected events per second, and the DAQ speed which are
caused by varied generating frequencies of pulse generator with new VHDL code.
Fig.3.5 plotted in Origin 6.0 software is the graph of events detected every second
with different frequencies with new VHDL code and old VHDL code [2]. The
information helps to compare the speed and accuracy of old and new VHDL code.
In previous experiments [2], the events per second at different frequencies
cannot be accepted because they are much greater than the frequencies, the numbers
of input events every single second. Within the range of 12Hz to 380Hz, events per
second and generating frequencies are linear, and the corresponding equation is
equation 3.3 (Appendix C).
y = (22.2430 28.5028) + (1.3980 0.1260)x (3.3)
Variable y stands for events per second, variable x stands for frequency, and
correlation coefficient (R-square) is 0.99596. For the purpose of building an ideal
MCA, the angular efficiency calculated from number of events per second and
corresponding frequency is close to 1. The old VHDL code cannot make the MCA
(Flash-ADC/FPGA) works like an ideal device does in just a small range of
frequency (angular efficiency is too greater than 1). From 12Hz to 3052Hz, MCA
(Flash-ADC/FPGA) embedded new VHDL code works stable and the angular
efficiency is 1.0099. Linear equation of events per second and varied frequencies is
equation 3.4.
y = (0.0105 0.1186) + (1.0099 0.0001)x (3.4)
In equation 3.4, y stands for events per second, x stands for frequency, and
correlation coefficient is 1. Although the stability just occurs at low frequencies, the
ratio of detected events and input events is nearly 1. Moreover, new evaluated DAQ
speed in stable range is 3052 events/sec and it is more than five times (5.6 times)
faster than old DAQ speed (547 events/sec).
[33]
The conclusion from this experiment is MCA (Flash-ADC/FPGA) works at a
higher stable state (proportion 1.0099 of detected events to input events) at more
than five times higher the DAQ speed (3052 events/sec and 547 events/sec).
3.1.2 Examine the peak distribution
Table 3.5. Set up parameters in peak distribution experiment
Apparatus Parameters Value
Canberra 2026 amplifier
Coarse gain 20

Fine gain 5-1.0

Shaping time
6sec
LabVIEW spectrum interface
Time to stop 100sec

Left Peak 15
Right Peak 25

Number Data Out 150

Delay 60

Time bin 94

The purpose of this next experiment is manipulating parameters in
LabVIEWTM to detect all pulses from free-running Flash-ADC based on the result
of DAQ speed in previous section. Further experiments with suitable parameters
would have ablitiy to detect as many pulses as possible by parameters estimated
from this experiment. The experiment layout is the same with section 3.1.1, but
MCA (Flash-ADC/FPGA) works at stable frequency and variety of amplitudes,
which are generated by pulse generator. In section 3.1.1, stability of MCA (Flash-
ADC/FPGA) occurs in range of 12Hz to 3052Hz so that in this experiment, the
frequency at which the MCA works is 1526Hz. Amplitudes are varied from 60mV
to 1000mV, estimated by oscilloscope, corresponds with the variety of variable
width from 1 to 38 (Table .3.2). To detect all pulses whose amplitudes are not
higher than 1000mV, parameters in pulse generators VHDL code are set up to
[34]
generate pulses of 1000mV, and parameters are turned to advantage to detect a full
pulse, and a full spectrum of 1000mV pulses. Therefore, first step of this
experiment is to find the appropriate parameters for 1000mV (pulse and spectrum,
as in Fig.3.6). The result is shown in Table 3.5.

Fig.3.6. Spectrum of 1000mV pulses

Fig.3.7. Spectrum of peaks distribution
NumberDataOut: 150
LeftPeak: 15
RightPeak: 25
delay: 60
time_bin: 94
Channel
C
o
u
n
t
s

4000 3000 2000 1000 0
25000
20000
15000
10000
5000
0
[35]
With these parameters, variable width is varied from 38 to 1, and causes the
amplitudes generated are varied from 1000mV downto 60mV in oscilloscope, or
1000mV to 51mV (in LabVIEW
TM
interface). Spectrum of all generated pulses is
shown in Fig.3.7. With the spectrum in Fig.3.7, channel of each peak is located.
Table 3.6 indicates the amplitudes and channels of peaks. By the recorded
information, the calibration line is created.
Table 3.6. Amplitudes in LabVIEW interface and channels of peaks
Amplitude
(mV)
Channel
51 140
101.9 300
149 509
207.8 736
258.8 955
298 1123
325.5 1229
345.1 1325
372.5 1436
396.1 1539
419.6 1618
443.1 1731
466.6 1822
486.3 1926
513.7 2018
537.2 2096
556.8 2190
576.5 2281
600 2374
Amplitude
(mV)
Channel
623.5 2467
647 2558
666.6 2657
686.3 2746
709.8 2838
733.3 2927
749 3002
768.6 3093
792.1 3179
815.7 3267
835.3 3353
858.8 3444
874.5 3531
898 3614
917.6 3682
945.1 3781
964.7 3875
984.3 3963
1000 4050
[36]

Fig.3.8. Linear fit of amplitudes and located channels
With the spectrum of pulse amplitudes, channel of each amplitude peak is
located and indicated in graph of amplitude calibration (Fig.3.8). The amplitudes
and channels are linear and relate to each other by equation 3.5.
y ( 107.90 5.02) (4.14 0.01)x = + (3.5)
In equation 3.5, y stands for channel, x stands for amplitude (mV), and
correlation coefficient is 0.99994. The energy of a radiation is in direct ratio to the
charge integration or amplitude of pulse. Therefore, with good linearity, the MCA
(Flash-ADC/FPGA) is good enough to be include in a spectroscopy for radiation
experiments.
In conclusion, experiment with pulse generator in section 3.1.1 help us figure
the maximum DAQ speed is 3052 events per second with no dead-time of the
system. The parameters evaluated in section 3.1.2 help us detect all output signals
from free-running Flash-ADC. The manipulated parameters avoid losing data of the
MCA (Flash-ADC/FPGA). The ability in processing digital data is proved to be
good enough for radiation experiments due to the linearity of varied amplitudes and
located channels.
[37]
3.2. NaI(Tl) 3inchx3inch Gamma Spectrometry
Intention of this section is to check the ability of MCA (Flash-ADC/FPGA)
when it is used in radiation measurements. The MCA (Flash-ADC/FPGA) is
included in a gamma spectroscopy using NaI(Tl) scintillator detector 3inch x 3inch.
This gamma spectroscopys schematic arrangement is shown in Fig.3.9, and real
layout in Fig.3.10. The experiments are carried out with two disc-shape
radioisotopes
133
Ba ( 0.1Ci ) and
152
Eu (1.05Ci ), products of Spectrum
Techniques, Ins. To lower the dead-time in the experiments, we set up parameters,
indicated in Table 3.7, based on the result in section 3.1.
Table 3.7. Set up parameters in gamma spectroscopy experiments
Apparatus Parameters Value
Canberra 3106D High Voltage Supply High Voltage (positive) 0.8kV

Canberra 2026 amplifier
Coarse gain 20

Fine gain 5-1.0

Shaping time 6sec
LabVIEW
TM
spectrum interface
Time to stop 1000sec

Left Peak 15

Right Peak 25

Number Data Out 150

Delay 60

Time bin 94

TrigA 5


Fig.3.9. Diagram of Experiment layout with gamma spectroscopy
RS-232
MCA
(Flash-ADC/
FPGA)
Computer
LabVIEW
interface
Detector
NaI(Tl)
Pre-Amp
Amp
[38]

Fig.3.10. Experiment layout with gamma spectroscopy in laboratory

Fig.3.11a. Geometry layout Fig.3.11b. Detectors position

Fig.3.11.c. Top view of geometry layout Fig.3.11.d. Side view of geometry layout
Fig.3.11. Geometry layout of NaI(Tl) and radiation sources
NaI(Tl) detector, model CANBERRA 802 3x3m and photomultiplier tube
base/preamplifier, model CANBERRA 2007P are standed against together to reach
a high efficiency of amplification in pre-amplifier. The detector is coverd in
LabVIEW
TM

interface
MCA
(Flash-ADC/FPGA)
High
Voltage
Supply
Amplifier
Pre- Amplifier
Detector NaI(Tl)
3inchx3inch covered in
cylindrical lead
(a)
Radioisotope
(b)
(c) (d)
[39]

cylindrical lead. The radiation sources are shielded around by lead. Positions, and
sizes of lead and sources are described more clearly in Fig.3.11. Spectrums display
and data analysis are managed by Microcal Origin 6.0. Energies for calibration is
provided by Spectrum Techniques, Ins (Appendix A and Appendix B).
3.2.2.
152
Eu spectrum

Fig.3.12. Decay scheme of
152
Eu [15]

Fig.3.13. Spectrum of
152
Eu
244.69 keV
1818.8 keV
1874.3 keV
152
Eu

1474.5 keV
695.6 keV
152
Gd
8.17%
13.08%
27.9%
EC/
72.1%
1752.5 keV
1507.8 keV
788.5 keV
344.5 keV
152
Sm
1.70%
0.77%
21.35%
24.72%
1085.84 keV
1408.01 keV
964.08 keV
121.78 keV
344.28 keV
778.90 keV
[40]

Fig.3.12 is the decay scheme of
152
Eu with multi gamma energies ranging
from hundreds of keV to MeV.
152
Eu has two decay modes: electron capture and
eletron decay. Total number of detected events is 791342 after 1000 seconds of
measurement. Fig.3.13 is the spectrum of
152
Eu. In the spectrum we can see
apperances of some peaks which is accumulated by emitted photons or scattered
photons. Peak of 72.9 keV is X-rays peak, and peak of 36.6 keV is maybe created
from background radiation. Some energy peaks cannot be performed due to their
low intensities.
3.2.1.
133
Ba spectrum
`
Fig.3.14. Decay scheme of
133
Ba [15]

Fig.3.15. Spectrum of
133
Ba
14%
133
Ba
86%
437.013 keV
383.851 keV
160.614 keV
80.997 keV
133
Cs
356 keV
383.85 keV
302.85 keV
80.997 keV
EC
[41]

Fig.3.14 is the decay scheme of electron capture mode, as the only decay
mode, of
133
Ba. Total number of detected events is 726745 after 1000 seconds of
measurement. Fig.3.15 is the display of
133
Ba spectrum with energy peaks of
80.1 keV, 302.9 keV, 356 keV, and X-ray peak 33.1 keV. We can see that energy
peak of 383.85 keV is not performed due to its low intensity.
Both measurements result nearly the same number of detected events. The
reason for this similarity is mainly caused by the DAQ speed of MCA. The DAQ
speed is just 0.32msec/event wheather the other analog devices acquisition is about
microsecond or nanosecond to amplify and shape time for a signal [14], [16].
3.2.3. Gamma detection response
Table 3.8. Results of photo peak energies of
152
Eu
Radioisotope Energy (keV) Channel
152
Eu
121.78 220
244.70 462
344.28 653
778.90 1503
964.08 1830
1085.90 2096
1408.00 2650
Since
152
Eu has more photon energies than
133
Ba does,
152
Eu is used to
evaluate the energy calibration, and
133
Ba is used to evaluate the accuracy of
calibration equation. With detected different energy peaks of
152
Eu, channels
(positions of peaks) are looked for. Based on collected information, energy
calibration equation is computed afterward. Table 3.8 is indicated energy peaks and
channels. Fig.3.16 is graph of energy calibration.
[42]


Fig.3.16. Graph of energy calibration
Equation 3.6 is the energy calibration equation with correlation coefficient
(R-square) is 0.99977.
Energy(keV) = (0.487 8.061) + (0.525 0.005)Channel (3.6)

2 2
2 2 2
E E
E a b
a b
| | | |
o o
o = o + o
| |
o o
\ . \ .
(3.7)

2 2 2
E a b
( x ) o = o + o (3.8)
With the equation 3.7 and found channels of
133
Ba, we calculate the fitted
energies, and the deviations of fitted energies are computed by equation 3.8, with E
is energy (keV), x is channel, a is equal to 0.487, b is equal to 0.525,
a

is equal to
8.061, and
b
o
is equal to 0.005. As we can see in Table 3.8, every real energy is in
range of fitted energy increased or decreased by deviation. Therefore, we can
conclude that gamma spectroscopy using NaI(Tl) 3inch x 3inch detector and MCA
(Flash-ADC/FPGA) shows good linearity response.

[43]

Table 3.9. Fitted energy and energy deviation of
133
Ba
Energy (keV) Channel Fitted Energy (keV)
80.10 143 75.562 8.093
302.90 572 300.787 8.553
356.00 677 355.912 8.743
3.2.4 Energy resolution
To figure the energy resolution of the gamma spectroscopy, we use origin 6.0
to fit Gaussian measured points. Result of this work is mean and FWHM of each
gaussian peak. Fig.3.17 shows measured points in peak of 344.28 keV and Gaussian
fit line in
152
Eu spectrum.

Fig.3.17. Gaussian fit in Origin 6.0
With correlation coefficient of each fitted Gaussian peak is quite good,
computation of energy resolution is worked out by equation 3.9.

FWHM
Resolution(%) = x100
Mean
(3.9)
[44]

Table 3.10 shows the energies, mean, FWHM, resolution (R), and correlation
coefficient. Fig.3.18 is graph of energy resolution. In comparison to many theses,
the energy resolutions here is not good although energy peaks are fitted many times.
However, the energy resolutions is quite good for a gamma spectroscopy using
NaI(Tl) detector (resolution of energy of about 1MeV is 7% [12], but 6% with
1085keV, and 4.9% with 964.08keV in this experiment).
Table 3.10. Obtained results of Gaussian fit
Radioisotopes Energy (keV) Channel FWHM R (%) R-square
152
Eu
121.78 220 27.9 12.6 0.972
244.70 462 43.3 9.4 0.971
344.28 654 54.8 8.4 0.990
778.90 1503 85.3 5.7 0.905
964.08 1830 91.0 4.9 0.890
1085.90 2096 126.1 6.0 0.964
1408.00 2650 133.3 5.0 0.954
133
Ba
80.10 143 25.6 17.9 0.98
302.90 572 43.2 7.6 0.976
356.00 677 57.1 8.4 0.996

Fig.3.18. Graph of energy resolution
[45]

Modifying VHDL for MCA (Flash-ADC/FPGA) by building a histogram
inside FPGA chip aims some benefits. By varying frequencies of input pulses, the
greatest speed of MCA (Flash-ADC/FPGA) is evaluated about 3052 events per
second, or 0.32 milisecond to detect and process a pulse. The speed with new
modified VHDL code is three times higher than the speed of the old one. MCA
(Flash-ADC/FPGA) now can be used in higher dose rate measurements. Parameters
in LabVIEW
TM
is manipulated as the most suitable to detect all pulses with variety
of amplitudes from Flash-ADC.
With the equation 3.4, the gamma spectroscopy using NaI(Tl) 3inch x 3inch
detector and MCA (Flash-ADC/FPGA) satisfies experiments with energy range of
2.1MeV with same set up parameters in Table 3.4. Additionally, a huge advantage
of the MCA (Flash-ADC/FPGA) is an ability to focus on smaller or larger energy
range by changing parameters in LabVIEW
TM
interface, high voltage supply and
amplifier. Energy resolution of the gamma spectrosopy used in this thesis is quite
good in comparison with resolution of NaI(Tl) detector usually known.
[46]

CONCLUSIONS
In this thesis, the problem with data transmission via COM port RS-232
connecting between MCA (Flash-ADC/FPGA) is solved by creating a Histogram
Memory right inside FPGA chip to separate transmitting data to computer and
writing data to MCA (Flash-ADC/FPGA). With some experiments, the highest
speed of MCA (Flash-ADC/FPGA) is figured at 3052 events per second. The speed
with new solution is suitable for higher dose rate (about three times higher)
radiation sources measurements in comparison with the old solution. However, the
speed is much slower compared with other commercial MCA of Canberra or Ortec
[15], [17]. Therefore, MCA (Flash-ADC/FPGA) is good enough in purpose of low
dose rate experiments. The most suitable parameters are found out to detect and
process all pulses with variety of amplitudes from free-running Flash-ADC.
In purpose of evaluation with real nuclear physics experiments, the MCA
(Flash-ADC/FPGA) is included in a gamma spectroscopy using NaI(Tl) 3inch x
3inch detector. Experiments are carried out with two standard radioisotopes
133
Ba (
0.1Ci ) and
152
Eu (1.05Ci ) with multi energies ranging from tens of keV to MeV.
Calibration equation is built by energy peaks and corresponding channels has a
quite good linearity with correlation coefficient is 0.99982.
Energy(keV) = (0.487 8.061) + (0.525 0.005)Channel
The gamma spectroscopy using the MCA (Flash-ADC/FPGA) can work with
high energy sources, up to about 2.1 MeV. Moreover, the energy resolution is quite
good with resolution of 6.0% of 1085keV. In addition to the benefit of MCA (Flash-
ADC/FPGA) in nuclear physics experiments, we can talk about the changeable
parameters in LabVIEW
TM
interface helps us focus on considered energy range with
good resolution by using charge integration to accumulate a radiation histogram.
[47]

PROPOSALS
To speed up the DAQ of MCA (Flash-ADC/FPGA) more, we must change the
frequency of each component in VHDL code and also transmit data via another
transmission cable. In future work, data will be transmitted via USB (Universal
Serial Bus) port for the speed of 480Mbytes/sec.
If there was more time available, some other experiments to figure the
efficiency, dead time, etc. would be carried out to find all responses of a gamma
spectroscopy. Those responses are foundations for further developments. The
results are foundations for further development of MCA (Flash-ADC/FPGA).
[48]

REFERENCES
Vietnamese references:
[1] Trn Phong Dng, Chu Vn To, Nguyn Hi Dng (2003), Phng
php ghi bc x ion ha, Nh xut bn i hc Quc Gia TP.HCM
[2] Nguyn Quc Hng (2011), Xy dng chng trnh nhng VHDL tnh cc
thng s c trng cho h MCA (Flash-ADC/FPGA), Master of Science
thesis, Can Tho University.
[3] V Mnh Hunh (2011), Kho st ph gamma ca mt s mu mi trng
bng detector HPGe vi h MCA (Flash-ADC/FPGA), Master of Science
thesis, Can Tho University.
English references:
[4] Cyclone II Device Handbook, Volume 1 (2006), ALTERA, Co.
http://www.altera.com/literature/lit-cyc2.jsp
[5] Christian Baumann (2010), Field Programmable Gate Array (FPGA),
University of Innbruck, Austria.
http://informatik.uibk.ac.at/teaching/ws2009/esa/fpga.pdf
[6] Stephen Brown and Jonathan Rose (1996), Architecture of FPGAs and
CPLDs: A Tutorial, University of Toronto, Canada.
http://www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdf
[7] Charge Integration: Analog Vs. Digital (2010), CAEN, Inc.
http://www.caen.it/documents/News/9/Analog_digital_app_note.pdf
[8] Joo M. Cardoso, Vitor Amorim, Rui Bastos, Rui Madeira, J. Baslio
Simes, and Carlos M. B. A. Correia (2001), A Very Low-Cost Portable
Multichannel Analyzer, 2000 IEEE Nuclear Science Symposium
Conference Record Cat No00CH37149, pages: 12/164 12/167.
[9] Sebastian Hoyos (2009), Flash-ADC, Texas A&M University, USA.
http://amesp02.tamu.edu/~jsilva/610/Lecture%20notes/Flash.pdf
[49]

[10] Yohei Ihara, Wataru Kada, Fuminobu Sata, Toshiyuki Ilda, Junji
Yamamoto, Sumasu Yamada, Tetsuo Horiguchi, and Kengo Hashimoto
(2011), Development of Compact Pulse Height Analyzer Modules Based
on FPGA for E-Learning Type Exercises on Nuclear Reactor, NUCLEAR
SCIENCE and TECHOLOGY, Vol. 1, pages: 244 247.
http://www.aesj.or.jp/publication/pnst001/data/244.pdf
[11] Glenn F. Knoll (1999), Radiation Detection and Measurement Third
Edition, John Wiley & Sons, Inc., USA.
[12] William R. Leo (1993), Techniques for Nuclear and Particle Physics
Experiments Second Revised Edition, Springer Verlag Press.
[13] Nguyn Thnh Trc (2010), 250MSa/s FADC and FPGA for Cosmic ray
measurement system, Bachelor of Science thesis, University of Science, Ho
Chi Minh city.
Websites:
[14] http://www.canberra.com
[15] http://www.nucleide.org
[16] http://www.ortec.com











[50]

APPENDIX A: ENERGY PEAKS AND INTENSITIES OF
133
Ba
Certificate of Calibration by SPECTRUM TECHNIQUES, Inc.
(detected by HPGe detector whose effciency was established with NI ST traceable
mixed nuclide standard SRS: 80899-854)
Radionuclide: Ba
133

Half-Life: 10.51 years
Decay Constant: 0.0001808
Calibration Date: Feb 17
th
, 2012
Activity: 0.10 Ci = 3.552 Bq
Table A. Photon energy (keV) and Intesity of
133
Ba detected by HPGe
Photon Energy
(keV)
Intensity
(%)
80.1 28.58
276.4 7.58
302.9 26.5
356 2.23
383.9 2.82

[51]

APPENDIX B: ENERGY PEAKS AND INTENSITIES OF
152
Eu
Certificate of Calibration by SPECTRUM TECHNIQUES, Inc.
(detected by HPGe detector whose effciency was established with NI ST traceable
mixed nuclide standard SRS: 80899-854)
Radionuclide: Eu
152

Half-Life: 13537 years
Decay Constant: 0.0512
Calibration Date: Feb 13
th
, 2012
Activity: 1.05 Ci = 38850 Bq
Table B. Photon Energy (keV) and Intensity of
152
Eu detected by HPGe
Photon Energy
(keV)
Intensity
(%)
121.78 28.58
244.7 7.58
344.28 26.5
411.12 2.23
443.97 2.82
778.9 12.94
867.38 4.25
964.08 14.61
1085.74 10.21
1089.74 1.73
1112.07 13.64
1212.95 1.42
1299.14 1.62
1408.01 21.01

[52]

APPENDIX C: DAQ SPEED WITH OLD VHDL CODE
Table C. DAQ speed and detected events per second with old VHDL code
Frequency
(Hz)
DAQ speed
(ms/event)
Events/sec
(sec
-1
)
12 54.67 18.29
95 5.5 181.82
380 1.83 547.45
1526 1.93 517.98
6104 1.52 657.4
12207 1.12 893.78
97656 0.94 1068.85
Base on the information from Table C, we have a linear equation between
number of acquired events per second and frequencies:
Y = (22.2430 28.5028) + (1.3980 0.1260)X

Fig.C. DAQ of MCA with old VHDL code
[53]

APPENDIX D: MEGAWIZARD PLUG-IN MANAGER

Fig.D. MegaWizard Plug-In Mangager
The MegaWizard Plug-In Manager is a very convenient tool of Quartus II 9.0
software. In the VHDL code embedded into FPGA chip, MegaWizard is included in
some component to limit the memory must be used. The Histogram Memory is
created based on RAM-3PORT, which is also an application of MegaWizard.
[54]

APPENDIX E: WRITING DATA PROCESS IN VHDL CODE
WHEN s2_hiA_0=>
rdpointer_hiA1<=X"000;
wrpointer_hiA <=X"000";
data_hiA:=X"0000";
data_hiA_in<=X"0000";
s2<=s2_hiA_1;
WHEN s2_hiA_1 =>
rdpointer_hiA1<=sumA(12 DOWNTO 0);
IF sumA<=X"FFF" THEN
s2<=s2_hiA_11;
ELSE
s2<=s2_idle;
END IF;
WHEN s2_hiA_11=>
s2<=s2_hiA_12;
WHEN s2_hiA_12=>
s2<=s2_hiA_2;
WHEN s2_hiA_2 =>
data_hiA:=data_hiA1_out+1;
wrpointer_hiA<=sumA(12 DOWNTO 0);
s2<=s2_hiA_3;
WHEN s2_hiA_3 =>
data_hiA_in<=data_hiA;
s2<=s2_hiA_record;
WHEN s2_hiA_record=>
s2<=s2_idle;
[55]

APPENDIX F: CONTINUOUS READING PROCESS IN VHDL CODE
WHEN h2_idle =>
ready_out <= '0';
rdpointer_hiA2 <=
'0'&X"000";
str <= '0';
IF (go_sync = '1') THEN
IF stop_sync='1' THEN
h2 <= histo_1;
rdpointer_hiA2
<= '0'&X"000";
ELSE h2<=h2_dump_1;
END IF;
END IF;
WHEN h2_dump_1 =>
IF dump_busy_sync = '0'
THEN
h2 <= h2_dump_2;
END IF;
WHEN h2_dump_2 =>
dump_out_2(31 DOWNTO 0)
<=count_event(31 DOWNTO 0);
dump_out_1(31 DOWNTO
16)<="000"& rdpointer_hiA2;
dump_out_1(15 DOWNTO 0)
<=data_hiA2_out;
str <= '1';
IF dump_busy_sync ='1' THEN
h2 <= h2_dump_3;
END IF;
WHEN h2_dump_3 =>
str <= '0';
rdpointer_hiA2 <=
rdpointer_hiA2+1;
IF rdpointer_hiA2
='1'&X"FFF" THEN
h2 <= h2_idle;
ELSE
<=h2_dump_1;
END IF;

[56]

APPENDIX G: FREQUENT READING PROCESS AND RESETTING
HISTOGRAM MEMORY PROCESS IN VHDL CODE
WHEN histo_1=>
IF dump_busy_sync = '0'
THEN
h2 <= histo_2;
END IF;
WHEN histo_2 =>
dump_out_2(31 DOWNTO 0)
<=count_event(31 DOWNTO 0);
dump_out_1(31 DOWNTO 16)
<="000"&rdpointer_hiA2;
dump_out_1(15 DOWNTO 0)
<=data_hiA2_out;
str <= '1';
IF dump_busy_sync ='1' THEN
h2 <= histo_3;
END IF;
WHEN histo_3 =>
str <= '0';
rdpointer_hiA2 <=
rdpointer_hiA2+1;
IF rdpointer_hiA2
='1'&X"FFF" THEN
h2 <= h2_reset_1;
ELSE h2<=histo_1;
END IF;
WHEN h2_reset_1=>
wrpointer_hiA <='0'&X"000";
data_hiA_in<=X"0000";
h2 <= h2_reset_2;
WHEN h2_reset_2 =>
wrpointer_hiA <=
wrpointer_hiA + 1;
IF wrpointer_hiA='1'&X"FFF"
THEN
h2 <= h2_reset_3;
END IF;
WHEN h2_reset_3 =>
count_event<=X"00000000";
IF stop_sync='0' THEN
h2<=h2_idle;
END IF;



[57]

APPENDIX H: STOP PROCESS IN VHDL CODE
Stopprocess:PROCESS (clock)
VARIABLE cnt: integer:=0;
BEGIN
IF clock'EVENT AND clock = '1' THEN
CASE st IS
WHEN st_idle=>
stop_sync <= '0';
cnt:=cnt+1;
IF cnt=50000000 then
cnt:=0;
IF count_time>=Time_in THEN
st<=st_tick; count_time<=X"0000";
ELIF count_time<Time_in THEN
count_time<=count_time+1;
END IF;
END IF;
WHEN st_tick=>
stop_sync <= '1';
IF (h2 = h2_reset_3) THEN
st<=st_idle; stop_sync <= '0';
END IF;
END CASE;
END IF;
END PROCESS Stopprocess;
[58]

APPENDIX I: PULSE GENERATING WITH VHDL CODE
Library IEEE, SYNOPSYS;
use IEEE.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use SYNOPSYS.attributes.all;

entity pulse_generator is
generic(width : integer := 0;freq: integer := 13);
--width=integer*8nsec; freq=25MHz/(2^(integer+1))
port (
LED : out std_logic_vector(3 downto 0);
NIM_IN : in std_logic_vector(15 downto 0);
L_AD : in std_logic_vector(7 downto 0);
L_DATA : inout std_logic_vector(15 downto 0);
L_RS : in std_logic;
L_WS : in std_logic;
L_ACK : out std_logic;
L_ATT : out std_logic;
L_RES : in std_logic;
LVDS_OUT : out std_logic_vector(15 downto 0);
TTL_OUT : out std_logic_vector(7 downto 0);
NIM_OUT : out std_logic_vector(7 downto 0);
CLK25 : in std_logic
);
end;
architecture Behavior of pulse_generator is
COMPONENT ALTPLLa is
PORT
[59]

(
inclk0 : IN STD_LOGIC ;
c0 : OUT STD_LOGIC
);
END COMPONENT;
signal time : std_logic_vector(31 downto 0);
signal clk_out : std_logic;
signal out_delay : std_logic_vector(width downto 0);
signal sig_out_delay : std_logic;
--signal sig_out_delay1 : std_logic;
signal out_width : std_logic_vector(width downto 0);
signal sig_out_width : std_logic;
signal out_pulse : std_logic_vector(width downto 0);
signal sig_out_pulse : std_logic;
signal coin : std_logic;
BEGIN
clk200 : ALTPLLa
port map (inclk0=>CLK25,c0=>clk_out);

---------------------- GENERATE CLOCK ---------------------------------------------
generate_clock : process (CLK25) is
begin
if CLK25'event and CLK25 = '1' then
time <= time + 1;
end if;
end process generate_clock;

---------------------- DELAY SIGNAL -------------------------------------------------
delay: process (clk_out) is
[60]

variable i : integer ;
begin
if clk_out'event and clk_out = '1' then
out_delay(0) <= time(freq);
out_width(0) <= time(freq);
for i in 0 to (width-1) loop
out_delay(i+1) <= out_delay(i);
-- out_width(i+1) <= out_width(i) or time(freq);
end loop;
end if;
sig_out_delay <= out_delay(width);
-- sig_out_width <= out_width(width-1);
-- sig_out_delay1 <= out_delay(width-250);
-- NIM_OUT(6) <= sig_out_delay; NIM_OUT(7) <=
sig_out_width;

-- NIM_OUT(5) <= sig_out_width and not sig_out_delay;
NIM_OUT(4) <= clk_out and sig_out_delay;
-- NIM_OUT(1) <= sig_out_delay;
-- NIM_OUT(2) <= sig_out_width;
NIM_OUT(6) <= clk_out and (time(freq) and not sig_out_delay);
-- NIM_OUT(0) <= NIM_IN(0) and NIM_IN(1);
-- NIM_OUT(4) <= sig_out_width and not sig_out_delay;
-- NIM_OUT(4) <= time(9);
-- NIM_OUT(5) <= time(freq);
NIM_OUT(5) <= clk_out;
-- TTL_OUT(7 downto 0) <= ('1','1','1','1','1','1','1','1');
-- TTL_OUT(0)<= time(freq)and not sig_out_delay;
LED(1) <= time(freq)and not sig_out_delay;
[61]

NIM_OUT(0)<=time(freq)and not sig_out_delay;
NIM_OUT(1)<=time(freq)and not sig_out_delay;
TTL_OUT(0) <= '1';

-- NIM_OUT(6) <= time(7);

LED(0)<='1';
end process delay;
--coincidence: process (clk_out) is
-- begin
-- coin <= NIM_IN(0) and NIM_IN(1);
-- NIM_OUT(7) <= coin;
-- end process coincidence;
----------------------- GENERATE PULSE FROM DELAY AND WIDTH ------------
----------------


END Behavior;